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Change tap_state naming to be consistent with SVF documentation. 

Courtesy of Dick Hollenbeck <dick@softplc.com>


git-svn-id: svn://svn.berlios.de/openocd/trunk@1232 b42882b7-edfa-0310-969c-e2dbd0fdcd60
__archive__
kc8apf 2008-12-13 06:25:50 +00:00
parent 6c27550f6e
commit c45de8073d
30 changed files with 1463 additions and 1468 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

64
src/flash/str9xpec.c
View File

@ -145,7 +145,7 @@ u8 str9xpec_isc_status(jtag_tap_t *tap)
scan_field_t field; scan_field_t field;
u8 status; u8 status;
if (str9xpec_set_instr(tap, ISC_NOOP, TAP_PI) != ERROR_OK) if (str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE) != ERROR_OK)
return ISC_STATUS_ERROR; return ISC_STATUS_ERROR;
field.tap = tap; field.tap = tap;
@ -158,7 +158,7 @@ u8 str9xpec_isc_status(jtag_tap_t *tap)
field.in_handler = NULL; field.in_handler = NULL;
field.in_handler_priv = NULL; field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI); jtag_add_dr_scan(1, &field, TAP_IDLE);
jtag_execute_queue(); jtag_execute_queue();
LOG_DEBUG("status: 0x%2.2x", status); LOG_DEBUG("status: 0x%2.2x", status);
@ -181,7 +181,7 @@ int str9xpec_isc_enable(struct flash_bank_s *bank)
return ERROR_OK; return ERROR_OK;
/* enter isc mode */ /* enter isc mode */
if (str9xpec_set_instr(tap, ISC_ENABLE, TAP_RTI) != ERROR_OK) if (str9xpec_set_instr(tap, ISC_ENABLE, TAP_IDLE) != ERROR_OK)
return ERROR_TARGET_INVALID; return ERROR_TARGET_INVALID;
/* check ISC status */ /* check ISC status */
@ -207,7 +207,7 @@ int str9xpec_isc_disable(struct flash_bank_s *bank)
if (!str9xpec_info->isc_enable) if (!str9xpec_info->isc_enable)
return ERROR_OK; return ERROR_OK;
if (str9xpec_set_instr(tap, ISC_DISABLE, TAP_RTI) != ERROR_OK) if (str9xpec_set_instr(tap, ISC_DISABLE, TAP_IDLE) != ERROR_OK)
return ERROR_TARGET_INVALID; return ERROR_TARGET_INVALID;
/* delay to handle aborts */ /* delay to handle aborts */
@ -238,7 +238,7 @@ int str9xpec_read_config(struct flash_bank_s *bank)
LOG_DEBUG("ISC_CONFIGURATION"); LOG_DEBUG("ISC_CONFIGURATION");
/* execute ISC_CONFIGURATION command */ /* execute ISC_CONFIGURATION command */
str9xpec_set_instr(tap, ISC_CONFIGURATION, TAP_PI); str9xpec_set_instr(tap, ISC_CONFIGURATION, TAP_IRPAUSE);
field.tap = tap; field.tap = tap;
field.num_bits = 64; field.num_bits = 64;
@ -250,7 +250,7 @@ int str9xpec_read_config(struct flash_bank_s *bank)
field.in_handler = NULL; field.in_handler = NULL;
field.in_handler_priv = NULL; field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI); jtag_add_dr_scan(1, &field, TAP_IDLE);
jtag_execute_queue(); jtag_execute_queue();
status = str9xpec_isc_status(tap); status = str9xpec_isc_status(tap);
@ -349,10 +349,10 @@ int str9xpec_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, ch
armv4_5 = bank->target->arch_info; armv4_5 = bank->target->arch_info;
arm7_9 = armv4_5->arch_info; arm7_9 = armv4_5->arch_info;
jtag_info = &arm7_9->jtag_info; jtag_info = &arm7_9->jtag_info;
str9xpec_info->tap = jtag_TapByAbsPosition( jtag_info->tap->abs_chain_position - 1); str9xpec_info->tap = jtag_TapByAbsPosition( jtag_info->tap->abs_chain_position - 1);
str9xpec_info->isc_enable = 0; str9xpec_info->isc_enable = 0;
str9xpec_build_block_list(bank); str9xpec_build_block_list(bank);
/* clear option byte register */ /* clear option byte register */
@ -390,7 +390,7 @@ int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
} }
/* execute ISC_BLANK_CHECK command */ /* execute ISC_BLANK_CHECK command */
str9xpec_set_instr(tap, ISC_BLANK_CHECK, TAP_PI); str9xpec_set_instr(tap, ISC_BLANK_CHECK, TAP_IRPAUSE);
field.tap = tap; field.tap = tap;
field.num_bits = 64; field.num_bits = 64;
@ -402,7 +402,7 @@ int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
field.in_handler = NULL; field.in_handler = NULL;
field.in_handler_priv = NULL; field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI); jtag_add_dr_scan(1, &field, TAP_IDLE);
jtag_add_sleep(40000); jtag_add_sleep(40000);
/* read blank check result */ /* read blank check result */
@ -416,7 +416,7 @@ int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
field.in_handler = NULL; field.in_handler = NULL;
field.in_handler_priv = NULL; field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_PI); jtag_add_dr_scan(1, &field, TAP_IRPAUSE);
jtag_execute_queue(); jtag_execute_queue();
status = str9xpec_isc_status(tap); status = str9xpec_isc_status(tap);
@ -506,7 +506,7 @@ int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last)
LOG_DEBUG("ISC_ERASE"); LOG_DEBUG("ISC_ERASE");
/* execute ISC_ERASE command */ /* execute ISC_ERASE command */
str9xpec_set_instr(tap, ISC_ERASE, TAP_PI); str9xpec_set_instr(tap, ISC_ERASE, TAP_IRPAUSE);
field.tap = tap; field.tap = tap;
field.num_bits = 64; field.num_bits = 64;
@ -518,7 +518,7 @@ int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last)
field.in_handler = NULL; field.in_handler = NULL;
field.in_handler_priv = NULL; field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI); jtag_add_dr_scan(1, &field, TAP_IDLE);
jtag_execute_queue(); jtag_execute_queue();
jtag_add_sleep(10); jtag_add_sleep(10);
@ -569,9 +569,9 @@ int str9xpec_lock_device(struct flash_bank_s *bank)
str9xpec_set_address(bank, 0x80); str9xpec_set_address(bank, 0x80);
/* execute ISC_PROGRAM command */ /* execute ISC_PROGRAM command */
str9xpec_set_instr(tap, ISC_PROGRAM_SECURITY, TAP_RTI); str9xpec_set_instr(tap, ISC_PROGRAM_SECURITY, TAP_IDLE);
str9xpec_set_instr(tap, ISC_NOOP, TAP_PI); str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE);
do { do {
field.tap = tap; field.tap = tap;
@ -658,7 +658,7 @@ int str9xpec_set_address(struct flash_bank_s *bank, u8 sector)
tap = str9xpec_info->tap; tap = str9xpec_info->tap;
/* set flash controller address */ /* set flash controller address */
str9xpec_set_instr(tap, ISC_ADDRESS_SHIFT, TAP_PI); str9xpec_set_instr(tap, ISC_ADDRESS_SHIFT, TAP_IRPAUSE);
field.tap = tap; field.tap = tap;
field.num_bits = 8; field.num_bits = 8;
@ -747,7 +747,7 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
while (dwords_remaining > 0) while (dwords_remaining > 0)
{ {
str9xpec_set_instr(tap, ISC_PROGRAM, TAP_PI); str9xpec_set_instr(tap, ISC_PROGRAM, TAP_IRPAUSE);
field.tap = tap; field.tap = tap;
field.num_bits = 64; field.num_bits = 64;
@ -759,12 +759,12 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
field.in_handler = NULL; field.in_handler = NULL;
field.in_handler_priv = NULL; field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI); jtag_add_dr_scan(1, &field, TAP_IDLE);
/* small delay before polling */ /* small delay before polling */
jtag_add_sleep(50); jtag_add_sleep(50);
str9xpec_set_instr(tap, ISC_NOOP, TAP_PI); str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE);
do { do {
field.tap = tap; field.tap = tap;
@ -807,7 +807,7 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
bytes_written++; bytes_written++;
} }
str9xpec_set_instr(tap, ISC_PROGRAM, TAP_PI); str9xpec_set_instr(tap, ISC_PROGRAM, TAP_IRPAUSE);
field.tap = tap; field.tap = tap;
field.num_bits = 64; field.num_bits = 64;
@ -819,12 +819,12 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
field.in_handler = NULL; field.in_handler = NULL;
field.in_handler_priv = NULL; field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI); jtag_add_dr_scan(1, &field, TAP_IDLE);
/* small delay before polling */ /* small delay before polling */
jtag_add_sleep(50); jtag_add_sleep(50);
str9xpec_set_instr(tap, ISC_NOOP, TAP_PI); str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE);
do { do {
field.tap = tap; field.tap = tap;
@ -889,7 +889,7 @@ int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd
buffer = calloc(CEIL(32, 8), 1); buffer = calloc(CEIL(32, 8), 1);
str9xpec_set_instr(tap, ISC_IDCODE, TAP_PI); str9xpec_set_instr(tap, ISC_IDCODE, TAP_IRPAUSE);
field.tap = tap; field.tap = tap;
field.num_bits = 32; field.num_bits = 32;
@ -901,7 +901,7 @@ int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd
field.in_handler = NULL; field.in_handler = NULL;
field.in_handler_priv = NULL; field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI); jtag_add_dr_scan(1, &field, TAP_IDLE);
jtag_execute_queue(); jtag_execute_queue();
idcode = buf_get_u32(buffer, 0, 32); idcode = buf_get_u32(buffer, 0, 32);
@ -1014,7 +1014,7 @@ int str9xpec_write_options(struct flash_bank_s *bank)
str9xpec_set_address(bank, 0x50); str9xpec_set_address(bank, 0x50);
/* execute ISC_PROGRAM command */ /* execute ISC_PROGRAM command */
str9xpec_set_instr(tap, ISC_PROGRAM, TAP_PI); str9xpec_set_instr(tap, ISC_PROGRAM, TAP_IRPAUSE);
field.tap = tap; field.tap = tap;
field.num_bits = 64; field.num_bits = 64;
@ -1026,12 +1026,12 @@ int str9xpec_write_options(struct flash_bank_s *bank)
field.in_handler = NULL; field.in_handler = NULL;
field.in_handler_priv = NULL; field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI); jtag_add_dr_scan(1, &field, TAP_IDLE);
/* small delay before polling */ /* small delay before polling */
jtag_add_sleep(50); jtag_add_sleep(50);
str9xpec_set_instr(tap, ISC_NOOP, TAP_PI); str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE);
do { do {
field.tap = tap; field.tap = tap;
@ -1303,13 +1303,13 @@ int str9xpec_handle_flash_enable_turbo_command(struct command_context_s *cmd_ctx
} }
/* enable turbo mode - TURBO-PROG-ENABLE */ /* enable turbo mode - TURBO-PROG-ENABLE */
str9xpec_set_instr(tap2, 0xD, TAP_RTI); str9xpec_set_instr(tap2, 0xD, TAP_IDLE);
if ((retval = jtag_execute_queue()) != ERROR_OK) if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval; return retval;
/* modify scan chain - str9 core has been removed */ /* modify scan chain - str9 core has been removed */
tap1->enabled = 0; tap1->enabled = 0;
return ERROR_OK; return ERROR_OK;
} }
@ -1337,11 +1337,11 @@ int str9xpec_handle_flash_disable_turbo_command(struct command_context_s *cmd_ct
if (tap == NULL) if (tap == NULL)
return ERROR_FAIL; return ERROR_FAIL;
/* exit turbo mode via TLR */ /* exit turbo mode via TLR */
str9xpec_set_instr(tap, ISC_NOOP, TAP_TLR); str9xpec_set_instr(tap, ISC_NOOP, TAP_RESET);
jtag_execute_queue(); jtag_execute_queue();
/* restore previous scan chain */ /* restore previous scan chain */
if (tap->next_tap) { if (tap->next_tap) {
tap->next_tap->enabled = 1; tap->next_tap->enabled = 1;

106
src/jtag/amt_jtagaccel.c
View File

@ -109,13 +109,13 @@ u8 amt_jtagaccel_tap_move[6][6][2] =
{{0x1f, 0x00}, {0x0c, 0x00}, {0x07, 0x00}, {0x97, 0x00}, {0x08, 0x00}, {0x00, 0x00}}, /* PI */ {{0x1f, 0x00}, {0x0c, 0x00}, {0x07, 0x00}, {0x97, 0x00}, {0x08, 0x00}, {0x00, 0x00}}, /* PI */
}; };
jtag_interface_t amt_jtagaccel_interface = jtag_interface_t amt_jtagaccel_interface =
{ {
.name = "amt_jtagaccel", .name = "amt_jtagaccel",
.execute_queue = amt_jtagaccel_execute_queue, .execute_queue = amt_jtagaccel_execute_queue,
.speed = amt_jtagaccel_speed, .speed = amt_jtagaccel_speed,
.register_commands = amt_jtagaccel_register_commands, .register_commands = amt_jtagaccel_register_commands,
.init = amt_jtagaccel_init, .init = amt_jtagaccel_init,
.quit = amt_jtagaccel_quit, .quit = amt_jtagaccel_quit,
@ -127,7 +127,7 @@ int amt_jtagaccel_register_commands(struct command_context_s *cmd_ctx)
COMMAND_CONFIG, NULL); COMMAND_CONFIG, NULL);
register_command(cmd_ctx, NULL, "rtck", amt_jtagaccel_handle_rtck_command, register_command(cmd_ctx, NULL, "rtck", amt_jtagaccel_handle_rtck_command,
COMMAND_CONFIG, NULL); COMMAND_CONFIG, NULL);
return ERROR_OK; return ERROR_OK;
} }
@ -142,7 +142,7 @@ void amt_jtagaccel_reset(int trst, int srst)
aw_control_rst |= 0x1; aw_control_rst |= 0x1;
else if (srst == 0) else if (srst == 0)
aw_control_rst &= ~0x1; aw_control_rst &= ~0x1;
AMT_AW(aw_control_rst); AMT_AW(aw_control_rst);
} }
@ -151,7 +151,7 @@ int amt_jtagaccel_speed(int speed)
aw_control_baudrate &= 0xf0; aw_control_baudrate &= 0xf0;
aw_control_baudrate |= speed & 0x0f; aw_control_baudrate |= speed & 0x0f;
AMT_AW(aw_control_baudrate); AMT_AW(aw_control_baudrate);
return ERROR_OK; return ERROR_OK;
} }
@ -170,11 +170,11 @@ void amt_wait_scan_busy(void)
{ {
int timeout = 4096; int timeout = 4096;
u8 ar_status; u8 ar_status;
AMT_AR(ar_status); AMT_AR(ar_status);
while (((ar_status) & 0x80) && (timeout-- > 0)) while (((ar_status) & 0x80) && (timeout-- > 0))
AMT_AR(ar_status); AMT_AR(ar_status);
if (ar_status & 0x80) if (ar_status & 0x80)
{ {
LOG_ERROR("amt_jtagaccel timed out while waiting for end of scan, rtck was %s, last AR_STATUS: 0x%2.2x", (rtck_enabled) ? "enabled" : "disabled", ar_status); LOG_ERROR("amt_jtagaccel timed out while waiting for end of scan, rtck was %s, last AR_STATUS: 0x%2.2x", (rtck_enabled) ? "enabled" : "disabled", ar_status);
@ -186,15 +186,15 @@ void amt_jtagaccel_state_move(void)
{ {
u8 aw_scan_tms_5; u8 aw_scan_tms_5;
u8 tms_scan[2]; u8 tms_scan[2];
tms_scan[0] = amt_jtagaccel_tap_move[tap_move_map[cur_state]][tap_move_map[end_state]][0]; tms_scan[0] = amt_jtagaccel_tap_move[tap_move_map[cur_state]][tap_move_map[end_state]][0];
tms_scan[1] = amt_jtagaccel_tap_move[tap_move_map[cur_state]][tap_move_map[end_state]][1]; tms_scan[1] = amt_jtagaccel_tap_move[tap_move_map[cur_state]][tap_move_map[end_state]][1];
aw_scan_tms_5 = 0x40 | (tms_scan[0] & 0x1f); aw_scan_tms_5 = 0x40 | (tms_scan[0] & 0x1f);
AMT_AW(aw_scan_tms_5); AMT_AW(aw_scan_tms_5);
if (jtag_speed > 3 || rtck_enabled) if (jtag_speed > 3 || rtck_enabled)
amt_wait_scan_busy(); amt_wait_scan_busy();
if (tms_scan[0] & 0x80) if (tms_scan[0] & 0x80)
{ {
aw_scan_tms_5 = 0x40 | (tms_scan[1] & 0x1f); aw_scan_tms_5 = 0x40 | (tms_scan[1] & 0x1f);
@ -202,7 +202,7 @@ void amt_jtagaccel_state_move(void)
if (jtag_speed > 3 || rtck_enabled) if (jtag_speed > 3 || rtck_enabled)
amt_wait_scan_busy(); amt_wait_scan_busy();
} }
cur_state = end_state; cur_state = end_state;
} }
@ -213,27 +213,27 @@ void amt_jtagaccel_runtest(int num_cycles)
u8 aw_scan_tms_1to4; u8 aw_scan_tms_1to4;
enum tap_state saved_end_state = end_state; enum tap_state saved_end_state = end_state;
/* only do a state_move when we're not already in RTI */ /* only do a state_move when we're not already in RTI */
if (cur_state != TAP_RTI) if (cur_state != TAP_IDLE)
{ {
amt_jtagaccel_end_state(TAP_RTI); amt_jtagaccel_end_state(TAP_IDLE);
amt_jtagaccel_state_move(); amt_jtagaccel_state_move();
} }
while (num_cycles - i >= 5) while (num_cycles - i >= 5)
{ {
aw_scan_tms_5 = 0x40; aw_scan_tms_5 = 0x40;
AMT_AW(aw_scan_tms_5); AMT_AW(aw_scan_tms_5);
i += 5; i += 5;
} }
if (num_cycles - i > 0) if (num_cycles - i > 0)
{ {
aw_scan_tms_1to4 = 0x80 | ((num_cycles - i - 1) & 0x3) << 4; aw_scan_tms_1to4 = 0x80 | ((num_cycles - i - 1) & 0x3) << 4;
AMT_AW(aw_scan_tms_1to4); AMT_AW(aw_scan_tms_1to4);
} }
amt_jtagaccel_end_state(saved_end_state); amt_jtagaccel_end_state(saved_end_state);
if (cur_state != end_state) if (cur_state != end_state)
amt_jtagaccel_state_move(); amt_jtagaccel_state_move();
@ -251,9 +251,9 @@ void amt_jtagaccel_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_s
u8 tms_scan[2]; u8 tms_scan[2];
if (ir_scan) if (ir_scan)
amt_jtagaccel_end_state(TAP_SI); amt_jtagaccel_end_state(TAP_IRSHIFT);
else else
amt_jtagaccel_end_state(TAP_SD); amt_jtagaccel_end_state(TAP_DRSHIFT);
amt_jtagaccel_state_move(); amt_jtagaccel_state_move();
amt_jtagaccel_end_state(saved_end_state); amt_jtagaccel_end_state(saved_end_state);
@ -263,7 +263,7 @@ void amt_jtagaccel_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_s
{ {
aw_tdi_option = 0x30 | (((scan_size - 1) % 8) - 1); aw_tdi_option = 0x30 | (((scan_size - 1) % 8) - 1);
AMT_AW(aw_tdi_option); AMT_AW(aw_tdi_option);
dw_tdi_scan = buf_get_u32(buffer, bit_count, (scan_size - 1) % 8) & 0xff; dw_tdi_scan = buf_get_u32(buffer, bit_count, (scan_size - 1) % 8) & 0xff;
AMT_DW(dw_tdi_scan); AMT_DW(dw_tdi_scan);
if (jtag_speed > 3 || rtck_enabled) if (jtag_speed > 3 || rtck_enabled)
@ -275,11 +275,11 @@ void amt_jtagaccel_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_s
dr_tdo = dr_tdo >> (8 - ((scan_size - 1) % 8)); dr_tdo = dr_tdo >> (8 - ((scan_size - 1) % 8));
buf_set_u32(buffer, bit_count, (scan_size - 1) % 8, dr_tdo); buf_set_u32(buffer, bit_count, (scan_size - 1) % 8, dr_tdo);
} }
bit_count += (scan_size - 1) % 8; bit_count += (scan_size - 1) % 8;
bits_left -= (scan_size - 1) % 8; bits_left -= (scan_size - 1) % 8;
} }
while (bits_left - 1 >= 8) while (bits_left - 1 >= 8)
{ {
dw_tdi_scan = buf_get_u32(buffer, bit_count, 8) & 0xff; dw_tdi_scan = buf_get_u32(buffer, bit_count, 8) & 0xff;
@ -292,11 +292,11 @@ void amt_jtagaccel_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_s
AMT_DR(dr_tdo); AMT_DR(dr_tdo);
buf_set_u32(buffer, bit_count, 8, dr_tdo); buf_set_u32(buffer, bit_count, 8, dr_tdo);
} }
bit_count += 8; bit_count += 8;
bits_left -= 8; bits_left -= 8;
} }
tms_scan[0] = amt_jtagaccel_tap_move[tap_move_map[cur_state]][tap_move_map[end_state]][0]; tms_scan[0] = amt_jtagaccel_tap_move[tap_move_map[cur_state]][tap_move_map[end_state]][0];
tms_scan[1] = amt_jtagaccel_tap_move[tap_move_map[cur_state]][tap_move_map[end_state]][1]; tms_scan[1] = amt_jtagaccel_tap_move[tap_move_map[cur_state]][tap_move_map[end_state]][1];
aw_tms_scan = 0x40 | (tms_scan[0] & 0x1f) | (buf_get_u32(buffer, bit_count, 1) << 5); aw_tms_scan = 0x40 | (tms_scan[0] & 0x1f) | (buf_get_u32(buffer, bit_count, 1) << 5);
@ -310,7 +310,7 @@ void amt_jtagaccel_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_s
dr_tdo = dr_tdo >> 7; dr_tdo = dr_tdo >> 7;
buf_set_u32(buffer, bit_count, 1, dr_tdo); buf_set_u32(buffer, bit_count, 1, dr_tdo);
} }
if (tms_scan[0] & 0x80) if (tms_scan[0] & 0x80)
{ {
aw_tms_scan = 0x40 | (tms_scan[1] & 0x1f); aw_tms_scan = 0x40 | (tms_scan[1] & 0x1f);
@ -328,12 +328,12 @@ int amt_jtagaccel_execute_queue(void)
enum scan_type type; enum scan_type type;
u8 *buffer; u8 *buffer;
int retval; int retval;
/* return ERROR_OK, unless a jtag_read_buffer returns a failed check /* return ERROR_OK, unless a jtag_read_buffer returns a failed check
* that wasn't handled by a caller-provided error handler * that wasn't handled by a caller-provided error handler
*/ */
retval = ERROR_OK; retval = ERROR_OK;
while (cmd) while (cmd)
{ {
switch (cmd->type) switch (cmd->type)
@ -351,7 +351,7 @@ int amt_jtagaccel_execute_queue(void)
#endif #endif
if (cmd->cmd.reset->trst == 1) if (cmd->cmd.reset->trst == 1)
{ {
cur_state = TAP_TLR; cur_state = TAP_RESET;
} }
amt_jtagaccel_reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst); amt_jtagaccel_reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
break; break;
@ -397,7 +397,7 @@ int amt_jtagaccel_execute_queue(void)
} }
cmd = cmd->next; cmd = cmd->next;
} }
return retval; return retval;
} }
@ -409,16 +409,16 @@ int amt_jtagaccel_get_giveio_access(void)
version.dwOSVersionInfoSize = sizeof version; version.dwOSVersionInfoSize = sizeof version;
if (!GetVersionEx( &version )) { if (!GetVersionEx( &version )) {
errno = EINVAL; errno = EINVAL;
return -1; return -1;
} }
if (version.dwPlatformId != VER_PLATFORM_WIN32_NT) if (version.dwPlatformId != VER_PLATFORM_WIN32_NT)
return 0; return 0;
h = CreateFile( "\\\\.\\giveio", GENERIC_READ, 0, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL ); h = CreateFile( "\\\\.\\giveio", GENERIC_READ, 0, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL );
if (h == INVALID_HANDLE_VALUE) { if (h == INVALID_HANDLE_VALUE) {
errno = ENODEV; errno = ENODEV;
return -1; return -1;
} }
CloseHandle( h ); CloseHandle( h );
@ -437,7 +437,7 @@ int amt_jtagaccel_init(void)
u8 status_port; u8 status_port;
#endif #endif
u8 ar_status; u8 ar_status;
#if PARPORT_USE_PPDEV == 1 #if PARPORT_USE_PPDEV == 1
if (device_handle > 0) if (device_handle > 0)
{ {
@ -447,7 +447,7 @@ int amt_jtagaccel_init(void)
snprintf(buffer, 256, "/dev/parport%d", amt_jtagaccel_port); snprintf(buffer, 256, "/dev/parport%d", amt_jtagaccel_port);
device_handle = open(buffer, O_RDWR); device_handle = open(buffer, O_RDWR);
if (device_handle < 0) if (device_handle < 0)
{ {
LOG_ERROR("cannot open device. check it exists and that user read and write rights are set"); LOG_ERROR("cannot open device. check it exists and that user read and write rights are set");
@ -468,7 +468,7 @@ int amt_jtagaccel_init(void)
LOG_ERROR(" cannot set compatible mode to device"); LOG_ERROR(" cannot set compatible mode to device");
return ERROR_JTAG_INIT_FAILED; return ERROR_JTAG_INIT_FAILED;
} }
control_port = 0x00; control_port = 0x00;
i = ioctl(device_handle, PPWCONTROL, &control_port); i = ioctl(device_handle, PPWCONTROL, &control_port);
@ -484,57 +484,57 @@ int amt_jtagaccel_init(void)
#if PARPORT_USE_GIVEIO == 1 #if PARPORT_USE_GIVEIO == 1
if (amt_jtagaccel_get_giveio_access() != 0) { if (amt_jtagaccel_get_giveio_access() != 0) {
#else /* PARPORT_USE_GIVEIO */ #else /* PARPORT_USE_GIVEIO */
if (ioperm(amt_jtagaccel_port, 5, 1) != 0) { if (ioperm(amt_jtagaccel_port, 5, 1) != 0) {
#endif /* PARPORT_USE_GIVEIO */ #endif /* PARPORT_USE_GIVEIO */
LOG_ERROR("missing privileges for direct i/o"); LOG_ERROR("missing privileges for direct i/o");
return ERROR_JTAG_INIT_FAILED; return ERROR_JTAG_INIT_FAILED;
} }
/* prepare epp port */ /* prepare epp port */
/* clear timeout */ /* clear timeout */
status_port = inb(amt_jtagaccel_port + 1); status_port = inb(amt_jtagaccel_port + 1);
outb(status_port | 0x1, amt_jtagaccel_port + 1); outb(status_port | 0x1, amt_jtagaccel_port + 1);
/* reset epp port */ /* reset epp port */
outb(0x00, amt_jtagaccel_port + 2); outb(0x00, amt_jtagaccel_port + 2);
outb(0x04, amt_jtagaccel_port + 2); outb(0x04, amt_jtagaccel_port + 2);
#endif #endif
if (rtck_enabled) if (rtck_enabled)
{ {
/* set RTCK enable bit */ /* set RTCK enable bit */
aw_control_fsm |= 0x02; aw_control_fsm |= 0x02;
} }
/* enable JTAG port */ /* enable JTAG port */
aw_control_fsm |= 0x04; aw_control_fsm |= 0x04;
AMT_AW(aw_control_fsm); AMT_AW(aw_control_fsm);
amt_jtagaccel_speed(jtag_speed); amt_jtagaccel_speed(jtag_speed);
if (jtag_reset_config & RESET_TRST_OPEN_DRAIN) if (jtag_reset_config & RESET_TRST_OPEN_DRAIN)
aw_control_rst &= ~0x8; aw_control_rst &= ~0x8;
else else
aw_control_rst |= 0x8; aw_control_rst |= 0x8;
if (jtag_reset_config & RESET_SRST_PUSH_PULL) if (jtag_reset_config & RESET_SRST_PUSH_PULL)
aw_control_rst &= ~0x2; aw_control_rst &= ~0x2;
else else
aw_control_rst |= 0x2; aw_control_rst |= 0x2;
amt_jtagaccel_reset(0, 0); amt_jtagaccel_reset(0, 0);
/* read status register */ /* read status register */
AMT_AR(ar_status); AMT_AR(ar_status);
LOG_DEBUG("AR_STATUS: 0x%2.2x", ar_status); LOG_DEBUG("AR_STATUS: 0x%2.2x", ar_status);
return ERROR_OK; return ERROR_OK;
} }
int amt_jtagaccel_quit(void) int amt_jtagaccel_quit(void)
{ {
return ERROR_OK; return ERROR_OK;
} }
@ -568,6 +568,6 @@ int amt_jtagaccel_handle_rtck_command(struct command_context_s *cmd_ctx, char *c
rtck_enabled = 0; rtck_enabled = 0;
} }
} }
return ERROR_OK; return ERROR_OK;
} }

78
src/jtag/bitbang.c
View File

@ -41,24 +41,24 @@ bitbang_interface_t *bitbang_interface;
/* DANGER!!!! clock absolutely *MUST* be 0 in idle or reset won't work! /* DANGER!!!! clock absolutely *MUST* be 0 in idle or reset won't work!
* *
* Set this to 1 and str912 reset halt will fail. * Set this to 1 and str912 reset halt will fail.
* *
* If someone can submit a patch with an explanation it will be greatly * If someone can submit a patch with an explanation it will be greatly
* appreciated, but as far as I can tell (ØH) DCLK is generated upon * appreciated, but as far as I can tell (ØH) DCLK is generated upon
* clk=0 in TAP_RTI. Good luck deducing that from the ARM documentation! * clk=0 in TAP_IDLE. Good luck deducing that from the ARM documentation!
* The ARM documentation uses the term "DCLK is asserted while in the TAP_RTI * The ARM documentation uses the term "DCLK is asserted while in the TAP_IDLE
* state". With hardware there is no such thing as *while* in a state. There * state". With hardware there is no such thing as *while* in a state. There
* are only edges. So clk => 0 is in fact a very subtle state transition that * are only edges. So clk => 0 is in fact a very subtle state transition that
* happens *while* in the TAP_RTI state. "#&¤"#¤&"#&"#& * happens *while* in the TAP_IDLE state. "#&¤"#¤&"#&"#&
* *
* For "reset halt" the last thing that happens before srst is asserted * For "reset halt" the last thing that happens before srst is asserted
* is that the breakpoint is set up. If DCLK is not wiggled one last * is that the breakpoint is set up. If DCLK is not wiggled one last
* time before the reset, then the breakpoint is not set up and * time before the reset, then the breakpoint is not set up and
* "reset halt" will fail to halt. * "reset halt" will fail to halt.
* *
*/ */
#define CLOCK_IDLE() 0 #define CLOCK_IDLE() 0
int bitbang_execute_queue(void); int bitbang_execute_queue(void);
@ -76,10 +76,10 @@ void bitbang_end_state(enum tap_state state)
} }
void bitbang_state_move(void) { void bitbang_state_move(void) {
int i=0, tms=0; int i=0, tms=0;
u8 tms_scan = TAP_MOVE(cur_state, end_state); u8 tms_scan = TAP_MOVE(cur_state, end_state);
for (i = 0; i < 7; i++) for (i = 0; i < 7; i++)
{ {
tms = (tms_scan >> i) & 1; tms = (tms_scan >> i) & 1;
@ -87,7 +87,7 @@ void bitbang_state_move(void) {
bitbang_interface->write(1, tms, 0); bitbang_interface->write(1, tms, 0);
} }
bitbang_interface->write(CLOCK_IDLE(), tms, 0); bitbang_interface->write(CLOCK_IDLE(), tms, 0);
cur_state = end_state; cur_state = end_state;
} }
@ -113,7 +113,7 @@ void bitbang_path_move(pathmove_command_t *cmd)
LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition", tap_state_strings[cur_state], tap_state_strings[cmd->path[state_count]]); LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition", tap_state_strings[cur_state], tap_state_strings[cmd->path[state_count]]);
exit(-1); exit(-1);
} }
bitbang_interface->write(0, tms, 0); bitbang_interface->write(0, tms, 0);
bitbang_interface->write(1, tms, 0); bitbang_interface->write(1, tms, 0);
@ -121,7 +121,7 @@ void bitbang_path_move(pathmove_command_t *cmd)
state_count++; state_count++;
num_states--; num_states--;
} }
bitbang_interface->write(CLOCK_IDLE(), tms, 0); bitbang_interface->write(CLOCK_IDLE(), tms, 0);
end_state = cur_state; end_state = cur_state;
@ -130,16 +130,16 @@ void bitbang_path_move(pathmove_command_t *cmd)
void bitbang_runtest(int num_cycles) void bitbang_runtest(int num_cycles)
{ {
int i; int i;
enum tap_state saved_end_state = end_state; enum tap_state saved_end_state = end_state;
/* only do a state_move when we're not already in RTI */ /* only do a state_move when we're not already in RTI */
if (cur_state != TAP_RTI) if (cur_state != TAP_IDLE)
{ {
bitbang_end_state(TAP_RTI); bitbang_end_state(TAP_IDLE);
bitbang_state_move(); bitbang_state_move();
} }
/* execute num_cycles */ /* execute num_cycles */
for (i = 0; i < num_cycles; i++) for (i = 0; i < num_cycles; i++)
{ {
@ -147,7 +147,7 @@ void bitbang_runtest(int num_cycles)
bitbang_interface->write(1, 0, 0); bitbang_interface->write(1, 0, 0);
} }
bitbang_interface->write(CLOCK_IDLE(), 0, 0); bitbang_interface->write(CLOCK_IDLE(), 0, 0);
/* finish in end_state */ /* finish in end_state */
bitbang_end_state(saved_end_state); bitbang_end_state(saved_end_state);
if (cur_state != end_state) if (cur_state != end_state)
@ -158,13 +158,13 @@ void bitbang_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
{ {
enum tap_state saved_end_state = end_state; enum tap_state saved_end_state = end_state;
int bit_cnt; int bit_cnt;
if (!((!ir_scan && (cur_state == TAP_SD)) || (ir_scan && (cur_state == TAP_SI)))) if (!((!ir_scan && (cur_state == TAP_DRSHIFT)) || (ir_scan && (cur_state == TAP_IRSHIFT))))
{ {
if (ir_scan) if (ir_scan)
bitbang_end_state(TAP_SI); bitbang_end_state(TAP_IRSHIFT);
else else
bitbang_end_state(TAP_SD); bitbang_end_state(TAP_DRSHIFT);
bitbang_state_move(); bitbang_state_move();
bitbang_end_state(saved_end_state); bitbang_end_state(saved_end_state);
@ -181,7 +181,7 @@ void bitbang_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
/* if we're just reading the scan, but don't care about the output /* if we're just reading the scan, but don't care about the output
* default to outputting 'low', this also makes valgrind traces more readable, * default to outputting 'low', this also makes valgrind traces more readable,
* as it removes the dependency on an uninitialised value * as it removes the dependency on an uninitialised value
*/ */
tdi=0; tdi=0;
if ((type != SCAN_IN) && (buffer[bytec] & bcval)) if ((type != SCAN_IN) && (buffer[bytec] & bcval))
tdi=1; tdi=1;
@ -192,7 +192,7 @@ void bitbang_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
val=bitbang_interface->read(); val=bitbang_interface->read();
bitbang_interface->write(1, tms, tdi); bitbang_interface->write(1, tms, tdi);
if (type != SCAN_OUT) if (type != SCAN_OUT)
{ {
if (val) if (val)
@ -201,21 +201,21 @@ void bitbang_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
buffer[bytec] &= ~bcval; buffer[bytec] &= ~bcval;
} }
} }
/* TAP_SD & TAP_SI are illegal end states, so we always transition to the pause /* TAP_DRSHIFT & TAP_IRSHIFT are illegal end states, so we always transition to the pause
* state which is a legal stable state from which statemove will work. * state which is a legal stable state from which statemove will work.
* *
* Exit1 -> Pause * Exit1 -> Pause
*/ */
bitbang_interface->write(0, 0, 0); bitbang_interface->write(0, 0, 0);
bitbang_interface->write(1, 0, 0); bitbang_interface->write(1, 0, 0);
bitbang_interface->write(CLOCK_IDLE(), 0, 0); bitbang_interface->write(CLOCK_IDLE(), 0, 0);
if (ir_scan) if (ir_scan)
cur_state = TAP_PI; cur_state = TAP_IRPAUSE;
else else
cur_state = TAP_PD; cur_state = TAP_DRPAUSE;
if (cur_state != end_state) if (cur_state != end_state)
bitbang_state_move(); bitbang_state_move();
} }
@ -227,18 +227,18 @@ int bitbang_execute_queue(void)
enum scan_type type; enum scan_type type;
u8 *buffer; u8 *buffer;
int retval; int retval;
if (!bitbang_interface) if (!bitbang_interface)
{ {
LOG_ERROR("BUG: Bitbang interface called, but not yet initialized"); LOG_ERROR("BUG: Bitbang interface called, but not yet initialized");
exit(-1); exit(-1);
} }
/* return ERROR_OK, unless a jtag_read_buffer returns a failed check /* return ERROR_OK, unless a jtag_read_buffer returns a failed check
* that wasn't handled by a caller-provided error handler * that wasn't handled by a caller-provided error handler
*/ */
retval = ERROR_OK; retval = ERROR_OK;
if(bitbang_interface->blink) if(bitbang_interface->blink)
bitbang_interface->blink(1); bitbang_interface->blink(1);
@ -259,7 +259,7 @@ int bitbang_execute_queue(void)
#endif #endif
if ((cmd->cmd.reset->trst == 1) || (cmd->cmd.reset->srst && (jtag_reset_config & RESET_SRST_PULLS_TRST))) if ((cmd->cmd.reset->trst == 1) || (cmd->cmd.reset->srst && (jtag_reset_config & RESET_SRST_PULLS_TRST)))
{ {
cur_state = TAP_TLR; cur_state = TAP_RESET;
} }
bitbang_interface->reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst); bitbang_interface->reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
break; break;
@ -313,7 +313,7 @@ int bitbang_execute_queue(void)
} }
if(bitbang_interface->blink) if(bitbang_interface->blink)
bitbang_interface->blink(0); bitbang_interface->blink(0);
return retval; return retval;
} }

12
src/jtag/bitq.c
View File

@ -195,7 +195,7 @@ void bitq_runtest(int num_cycles)
int i; int i;
/* only do a state_move when we're not already in RTI */ /* only do a state_move when we're not already in RTI */
if (cur_state != TAP_RTI) bitq_state_move(TAP_RTI); if (cur_state != TAP_IDLE) bitq_state_move(TAP_IDLE);
/* execute num_cycles */ /* execute num_cycles */
for (i = 0; i < num_cycles; i++) for (i = 0; i < num_cycles; i++)
@ -240,8 +240,8 @@ void bitq_scan_field(scan_field_t *field, int pause)
if (pause) { if (pause) {
bitq_io(0,0,0); bitq_io(0,0,0);
if (cur_state==TAP_SI) cur_state=TAP_PI; if (cur_state==TAP_IRSHIFT) cur_state=TAP_IRPAUSE;
else if (cur_state==TAP_SD) cur_state=TAP_PD; else if (cur_state==TAP_DRSHIFT) cur_state=TAP_DRPAUSE;
} }
} }
@ -250,8 +250,8 @@ void bitq_scan(scan_command_t *cmd)
{ {
int i; int i;
if (cmd->ir_scan) bitq_state_move(TAP_SI); if (cmd->ir_scan) bitq_state_move(TAP_IRSHIFT);
else bitq_state_move(TAP_SD); else bitq_state_move(TAP_DRSHIFT);
for (i=0; i < cmd->num_fields-1; i++) for (i=0; i < cmd->num_fields-1; i++)
bitq_scan_field(&cmd->fields[i], 0); bitq_scan_field(&cmd->fields[i], 0);
@ -285,7 +285,7 @@ int bitq_execute_queue(void)
#endif #endif
if ((cmd->cmd.reset->trst == 1) || (cmd->cmd.reset->srst && (jtag_reset_config & RESET_SRST_PULLS_TRST))) if ((cmd->cmd.reset->trst == 1) || (cmd->cmd.reset->srst && (jtag_reset_config & RESET_SRST_PULLS_TRST)))
{ {
cur_state = TAP_TLR; cur_state = TAP_RESET;
} }
bitq_interface->reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst); bitq_interface->reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
if (bitq_interface->in_rdy()) bitq_in_proc(); if (bitq_interface->in_rdy()) bitq_in_proc();

406
src/jtag/ft2232.c
View File

File diff suppressed because it is too large Load Diff

98
src/jtag/gw16012.c
View File

@ -97,13 +97,13 @@ int gw16012_quit(void);
int gw16012_handle_parport_port_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); int gw16012_handle_parport_port_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
jtag_interface_t gw16012_interface = jtag_interface_t gw16012_interface =
{ {
.name = "gw16012", .name = "gw16012",
.execute_queue = gw16012_execute_queue, .execute_queue = gw16012_execute_queue,
.speed = gw16012_speed, .speed = gw16012_speed,
.register_commands = gw16012_register_commands, .register_commands = gw16012_register_commands,
.init = gw16012_init, .init = gw16012_init,
.quit = gw16012_quit, .quit = gw16012_quit,
@ -113,7 +113,7 @@ int gw16012_register_commands(struct command_context_s *cmd_ctx)
{ {
register_command(cmd_ctx, NULL, "parport_port", gw16012_handle_parport_port_command, register_command(cmd_ctx, NULL, "parport_port", gw16012_handle_parport_port_command,
COMMAND_CONFIG, NULL); COMMAND_CONFIG, NULL);
return ERROR_OK; return ERROR_OK;
} }
@ -125,7 +125,7 @@ void gw16012_data(u8 value)
#ifdef _DEBUG_GW16012_IO_ #ifdef _DEBUG_GW16012_IO_
LOG_DEBUG("%2.2x", value); LOG_DEBUG("%2.2x", value);
#endif #endif
#if PARPORT_USE_PPDEV == 1 #if PARPORT_USE_PPDEV == 1
ioctl(device_handle, PPWDATA, &value); ioctl(device_handle, PPWDATA, &value);
#else #else
@ -134,7 +134,7 @@ void gw16012_data(u8 value)
#else #else
outb(value, gw16012_port); outb(value, gw16012_port);
#endif #endif
#endif #endif
} }
void gw16012_control(u8 value) void gw16012_control(u8 value)
@ -209,15 +209,15 @@ void gw16012_state_move(void)
{ {
int i=0, tms=0; int i=0, tms=0;
u8 tms_scan = TAP_MOVE(cur_state, end_state); u8 tms_scan = TAP_MOVE(cur_state, end_state);
gw16012_control(0x0); /* single-bit mode */ gw16012_control(0x0); /* single-bit mode */
for (i = 0; i < 7; i++) for (i = 0; i < 7; i++)
{ {
tms = (tms_scan >> i) & 1; tms = (tms_scan >> i) & 1;
gw16012_data(tms << 1); /* output next TMS bit */ gw16012_data(tms << 1); /* output next TMS bit */
} }
cur_state = end_state; cur_state = end_state;
} }
@ -243,12 +243,12 @@ void gw16012_path_move(pathmove_command_t *cmd)
LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition", tap_state_strings[cur_state], tap_state_strings[cmd->path[state_count]]); LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition", tap_state_strings[cur_state], tap_state_strings[cmd->path[state_count]]);
exit(-1); exit(-1);
} }
cur_state = cmd->path[state_count]; cur_state = cmd->path[state_count];
state_count++; state_count++;
num_states--; num_states--;
} }
end_state = cur_state; end_state = cur_state;
} }
@ -256,20 +256,20 @@ void gw16012_runtest(int num_cycles)
{ {
enum tap_state saved_end_state = end_state; enum tap_state saved_end_state = end_state;
int i; int i;
/* only do a state_move when we're not already in RTI */ /* only do a state_move when we're not already in RTI */
if (cur_state != TAP_RTI) if (cur_state != TAP_IDLE)
{ {
gw16012_end_state(TAP_RTI); gw16012_end_state(TAP_IDLE);
gw16012_state_move(); gw16012_state_move();
} }
for (i = 0; i < num_cycles; i++) for (i = 0; i < num_cycles; i++)
{ {
gw16012_control(0x0); /* single-bit mode */ gw16012_control(0x0); /* single-bit mode */
gw16012_data(0x0); /* TMS cycle with TMS low */ gw16012_data(0x0); /* TMS cycle with TMS low */
} }
gw16012_end_state(saved_end_state); gw16012_end_state(saved_end_state);
if (cur_state != end_state) if (cur_state != end_state)
gw16012_state_move(); gw16012_state_move();
@ -283,12 +283,12 @@ void gw16012_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
u8 scan_out, scan_in; u8 scan_out, scan_in;
/* only if we're not already in the correct Shift state */ /* only if we're not already in the correct Shift state */
if (!((!ir_scan && (cur_state == TAP_SD)) || (ir_scan && (cur_state == TAP_SI)))) if (!((!ir_scan && (cur_state == TAP_DRSHIFT)) || (ir_scan && (cur_state == TAP_IRSHIFT))))
{ {
if (ir_scan) if (ir_scan)
gw16012_end_state(TAP_SI); gw16012_end_state(TAP_IRSHIFT);
else else
gw16012_end_state(TAP_SD); gw16012_end_state(TAP_DRSHIFT);
gw16012_state_move(); gw16012_state_move();
gw16012_end_state(saved_end_state); gw16012_end_state(saved_end_state);
@ -302,20 +302,20 @@ void gw16012_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
bit_count += 7; bit_count += 7;
bits_left -= 7; bits_left -= 7;
} }
gw16012_control(0x0); /* single-bit mode */ gw16012_control(0x0); /* single-bit mode */
while (bits_left-- > 0) while (bits_left-- > 0)
{ {
u8 tms = 0; u8 tms = 0;
scan_out = buf_get_u32(buffer, bit_count, 1); scan_out = buf_get_u32(buffer, bit_count, 1);
if (bits_left == 0) /* last bit */ if (bits_left == 0) /* last bit */
{ {
if ((ir_scan && (end_state == TAP_SI)) if ((ir_scan && (end_state == TAP_IRSHIFT))
|| (!ir_scan && (end_state == TAP_SD))) || (!ir_scan && (end_state == TAP_DRSHIFT)))
{ {
tms = 0; tms = 0;
} }
else else
{ {
@ -329,20 +329,20 @@ void gw16012_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
{ {
gw16012_input(&scan_in); gw16012_input(&scan_in);
buf_set_u32(buffer, bit_count, 1, ((scan_in & 0x08) >> 3)); buf_set_u32(buffer, bit_count, 1, ((scan_in & 0x08) >> 3));
} }
bit_count++; bit_count++;
} }
if (!((ir_scan && (end_state == TAP_SI)) || if (!((ir_scan && (end_state == TAP_IRSHIFT)) ||
(!ir_scan && (end_state == TAP_SD)))) (!ir_scan && (end_state == TAP_DRSHIFT))))
{ {
gw16012_data(0x0); gw16012_data(0x0);
if (ir_scan) if (ir_scan)
cur_state = TAP_PI; cur_state = TAP_IRPAUSE;
else else
cur_state = TAP_PD; cur_state = TAP_DRPAUSE;
if (cur_state != end_state) if (cur_state != end_state)
gw16012_state_move(); gw16012_state_move();
} }
@ -355,12 +355,12 @@ int gw16012_execute_queue(void)
enum scan_type type; enum scan_type type;
u8 *buffer; u8 *buffer;
int retval; int retval;
/* return ERROR_OK, unless a jtag_read_buffer returns a failed check /* return ERROR_OK, unless a jtag_read_buffer returns a failed check
* that wasn't handled by a caller-provided error handler * that wasn't handled by a caller-provided error handler
*/ */
retval = ERROR_OK; retval = ERROR_OK;
while (cmd) while (cmd)
{ {
switch (cmd->type) switch (cmd->type)
@ -378,7 +378,7 @@ int gw16012_execute_queue(void)
#endif #endif
if (cmd->cmd.reset->trst == 1) if (cmd->cmd.reset->trst == 1)
{ {
cur_state = TAP_TLR; cur_state = TAP_RESET;
} }
gw16012_reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst); gw16012_reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
break; break;
@ -410,7 +410,7 @@ int gw16012_execute_queue(void)
scan_size = jtag_build_buffer(cmd->cmd.scan, &buffer); scan_size = jtag_build_buffer(cmd->cmd.scan, &buffer);
type = jtag_scan_type(cmd->cmd.scan); type = jtag_scan_type(cmd->cmd.scan);
#ifdef _DEBUG_JTAG_IO_ #ifdef _DEBUG_JTAG_IO_
LOG_DEBUG("%s scan (%i) %i bit end in %i", (cmd->cmd.scan->ir_scan) ? "ir" : "dr", LOG_DEBUG("%s scan (%i) %i bit end in %i", (cmd->cmd.scan->ir_scan) ? "ir" : "dr",
type, scan_size, cmd->cmd.scan->end_state); type, scan_size, cmd->cmd.scan->end_state);
#endif #endif
gw16012_scan(cmd->cmd.scan->ir_scan, type, buffer, scan_size); gw16012_scan(cmd->cmd.scan->ir_scan, type, buffer, scan_size);
@ -431,7 +431,7 @@ int gw16012_execute_queue(void)
} }
cmd = cmd->next; cmd = cmd->next;
} }
return retval; return retval;
} }
@ -443,16 +443,16 @@ int gw16012_get_giveio_access()
version.dwOSVersionInfoSize = sizeof version; version.dwOSVersionInfoSize = sizeof version;
if (!GetVersionEx( &version )) { if (!GetVersionEx( &version )) {
errno = EINVAL; errno = EINVAL;
return -1; return -1;
} }
if (version.dwPlatformId != VER_PLATFORM_WIN32_NT) if (version.dwPlatformId != VER_PLATFORM_WIN32_NT)
return 0; return 0;
h = CreateFile( "\\\\.\\giveio", GENERIC_READ, 0, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL ); h = CreateFile( "\\\\.\\giveio", GENERIC_READ, 0, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL );
if (h == INVALID_HANDLE_VALUE) { if (h == INVALID_HANDLE_VALUE) {
errno = ENODEV; errno = ENODEV;
return -1; return -1;
} }
CloseHandle( h ); CloseHandle( h );
@ -468,7 +468,7 @@ int gw16012_init(void)
int i = 0; int i = 0;
#endif #endif
u8 status_port; u8 status_port;
#if PARPORT_USE_PPDEV == 1 #if PARPORT_USE_PPDEV == 1
if (device_handle>0) if (device_handle>0)
{ {
@ -486,7 +486,7 @@ int gw16012_init(void)
snprintf(buffer, 256, "/dev/parport%d", gw16012_port); snprintf(buffer, 256, "/dev/parport%d", gw16012_port);
device_handle = open(buffer, O_WRONLY); device_handle = open(buffer, O_WRONLY);
#endif #endif
if (device_handle<0) if (device_handle<0)
{ {
LOG_ERROR("cannot open device. check it exists and that user read and write rights are set"); LOG_ERROR("cannot open device. check it exists and that user read and write rights are set");
@ -525,7 +525,7 @@ int gw16012_init(void)
gw16012_port = 0x378; gw16012_port = 0x378;
LOG_WARNING("No gw16012 port specified, using default '0x378' (LPT1)"); LOG_WARNING("No gw16012 port specified, using default '0x378' (LPT1)");
} }
LOG_DEBUG("requesting privileges for parallel port 0x%lx...", (long unsigned)(gw16012_port) ); LOG_DEBUG("requesting privileges for parallel port 0x%lx...", (long unsigned)(gw16012_port) );
#if PARPORT_USE_GIVEIO == 1 #if PARPORT_USE_GIVEIO == 1
if (gw16012_get_giveio_access() != 0) if (gw16012_get_giveio_access() != 0)
@ -545,19 +545,19 @@ int gw16012_init(void)
outb(0x0, gw16012_port + 2); outb(0x0, gw16012_port + 2);
#endif #endif
#endif /* PARPORT_USE_PPDEV */ #endif /* PARPORT_USE_PPDEV */
gw16012_input(&status_port); gw16012_input(&status_port);
gw16012_msb = (status_port & 0x80) ^ 0x80; gw16012_msb = (status_port & 0x80) ^ 0x80;
gw16012_speed(jtag_speed); gw16012_speed(jtag_speed);
gw16012_reset(0, 0); gw16012_reset(0, 0);
return ERROR_OK; return ERROR_OK;
} }
int gw16012_quit(void) int gw16012_quit(void)
{ {
return ERROR_OK; return ERROR_OK;
} }

222
src/jtag/jlink.c
View File

@ -146,92 +146,92 @@ int jlink_execute_queue(void)
int scan_size; int scan_size;
enum scan_type type; enum scan_type type;
u8 *buffer; u8 *buffer;
while (cmd != NULL) while (cmd != NULL)
{ {
switch (cmd->type) switch (cmd->type)
{ {
case JTAG_END_STATE: case JTAG_END_STATE:
DEBUG_JTAG_IO("end_state: %i", cmd->cmd.end_state->end_state); DEBUG_JTAG_IO("end_state: %i", cmd->cmd.end_state->end_state);
if (cmd->cmd.end_state->end_state != -1) if (cmd->cmd.end_state->end_state != -1)
{ {
jlink_end_state(cmd->cmd.end_state->end_state); jlink_end_state(cmd->cmd.end_state->end_state);
} }
break; break;
case JTAG_RUNTEST: case JTAG_RUNTEST:
DEBUG_JTAG_IO( "runtest %i cycles, end in %i", cmd->cmd.runtest->num_cycles, \ DEBUG_JTAG_IO( "runtest %i cycles, end in %i", cmd->cmd.runtest->num_cycles, \
cmd->cmd.runtest->end_state); cmd->cmd.runtest->end_state);
if (cmd->cmd.runtest->end_state != -1) if (cmd->cmd.runtest->end_state != -1)
{ {
jlink_end_state(cmd->cmd.runtest->end_state); jlink_end_state(cmd->cmd.runtest->end_state);
} }
jlink_runtest(cmd->cmd.runtest->num_cycles); jlink_runtest(cmd->cmd.runtest->num_cycles);
break; break;
case JTAG_STATEMOVE: case JTAG_STATEMOVE:
DEBUG_JTAG_IO("statemove end in %i", cmd->cmd.statemove->end_state); DEBUG_JTAG_IO("statemove end in %i", cmd->cmd.statemove->end_state);
if (cmd->cmd.statemove->end_state != -1) if (cmd->cmd.statemove->end_state != -1)
{ {
jlink_end_state(cmd->cmd.statemove->end_state); jlink_end_state(cmd->cmd.statemove->end_state);
} }
jlink_state_move(); jlink_state_move();
break; break;
case JTAG_PATHMOVE: case JTAG_PATHMOVE:
DEBUG_JTAG_IO("pathmove: %i states, end in %i", \ DEBUG_JTAG_IO("pathmove: %i states, end in %i", \
cmd->cmd.pathmove->num_states, \ cmd->cmd.pathmove->num_states, \
cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1]); cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1]);
jlink_path_move(cmd->cmd.pathmove->num_states, cmd->cmd.pathmove->path); jlink_path_move(cmd->cmd.pathmove->num_states, cmd->cmd.pathmove->path);
break; break;
case JTAG_SCAN: case JTAG_SCAN:
DEBUG_JTAG_IO("scan end in %i", cmd->cmd.scan->end_state); DEBUG_JTAG_IO("scan end in %i", cmd->cmd.scan->end_state);
if (cmd->cmd.scan->end_state != -1) if (cmd->cmd.scan->end_state != -1)
{ {
jlink_end_state(cmd->cmd.scan->end_state); jlink_end_state(cmd->cmd.scan->end_state);
} }
scan_size = jtag_build_buffer(cmd->cmd.scan, &buffer); scan_size = jtag_build_buffer(cmd->cmd.scan, &buffer);
DEBUG_JTAG_IO("scan input, length = %d", scan_size); DEBUG_JTAG_IO("scan input, length = %d", scan_size);
#ifdef _DEBUG_USB_COMMS_ #ifdef _DEBUG_USB_COMMS_
jlink_debug_buffer(buffer, (scan_size + 7) / 8); jlink_debug_buffer(buffer, (scan_size + 7) / 8);
#endif #endif
type = jtag_scan_type(cmd->cmd.scan); type = jtag_scan_type(cmd->cmd.scan);
jlink_scan(cmd->cmd.scan->ir_scan, type, buffer, scan_size, cmd->cmd.scan); jlink_scan(cmd->cmd.scan->ir_scan, type, buffer, scan_size, cmd->cmd.scan);
break; break;
case JTAG_RESET: case JTAG_RESET:
DEBUG_JTAG_IO("reset trst: %i srst %i", cmd->cmd.reset->trst, cmd->cmd.reset->srst); DEBUG_JTAG_IO("reset trst: %i srst %i", cmd->cmd.reset->trst, cmd->cmd.reset->srst);
jlink_tap_execute(); jlink_tap_execute();
if (cmd->cmd.reset->trst == 1) if (cmd->cmd.reset->trst == 1)
{ {
cur_state = TAP_TLR; cur_state = TAP_RESET;
} }
jlink_reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst); jlink_reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
break; break;
case JTAG_SLEEP: case JTAG_SLEEP:
DEBUG_JTAG_IO("sleep %i", cmd->cmd.sleep->us); DEBUG_JTAG_IO("sleep %i", cmd->cmd.sleep->us);
jlink_tap_execute(); jlink_tap_execute();
jtag_sleep(cmd->cmd.sleep->us); jtag_sleep(cmd->cmd.sleep->us);
break; break;
default: default:
LOG_ERROR("BUG: unknown JTAG command type encountered"); LOG_ERROR("BUG: unknown JTAG command type encountered");
exit(-1); exit(-1);
} }
cmd = cmd->next; cmd = cmd->next;
} }
return jlink_tap_execute(); return jlink_tap_execute();
} }
@ -239,19 +239,19 @@ int jlink_execute_queue(void)
int jlink_speed(int speed) int jlink_speed(int speed)
{ {
int result; int result;
if (speed <= JLINK_MAX_SPEED) if (speed <= JLINK_MAX_SPEED)
{ {
/* check for RTCK setting */ /* check for RTCK setting */
if (speed == 0) if (speed == 0)
speed = -1; speed = -1;
usb_out_buffer[0] = EMU_CMD_SET_SPEED; usb_out_buffer[0] = EMU_CMD_SET_SPEED;
usb_out_buffer[1] = (speed >> 0) & 0xff; usb_out_buffer[1] = (speed >> 0) & 0xff;
usb_out_buffer[2] = (speed >> 8) & 0xff; usb_out_buffer[2] = (speed >> 8) & 0xff;
result = jlink_usb_write(jlink_jtag_handle, 3); result = jlink_usb_write(jlink_jtag_handle, 3);
if (result == 3) if (result == 3)
{ {
return ERROR_OK; return ERROR_OK;
@ -266,14 +266,14 @@ int jlink_speed(int speed)
{ {
LOG_INFO("Requested speed %dkHz exceeds maximum of %dkHz, ignored", speed, JLINK_MAX_SPEED); LOG_INFO("Requested speed %dkHz exceeds maximum of %dkHz, ignored", speed, JLINK_MAX_SPEED);
} }
return ERROR_OK; return ERROR_OK;
} }
int jlink_khz(int khz, int *jtag_speed) int jlink_khz(int khz, int *jtag_speed)
{ {
*jtag_speed = khz; *jtag_speed = khz;
return ERROR_OK; return ERROR_OK;
} }
@ -286,16 +286,16 @@ int jlink_register_commands(struct command_context_s *cmd_ctx)
int jlink_init(void) int jlink_init(void)
{ {
int check_cnt; int check_cnt;
jlink_jtag_handle = jlink_usb_open(); jlink_jtag_handle = jlink_usb_open();
if (jlink_jtag_handle == 0) if (jlink_jtag_handle == 0)
{ {
LOG_ERROR("Cannot find jlink Interface! Please check connection and permissions."); LOG_ERROR("Cannot find jlink Interface! Please check connection and permissions.");
return ERROR_JTAG_INIT_FAILED; return ERROR_JTAG_INIT_FAILED;
} }
check_cnt = 0; check_cnt = 0;
while (check_cnt < 3) while (check_cnt < 3)
{ {
@ -305,7 +305,7 @@ int jlink_init(void)
jlink_get_status(); jlink_get_status();
break; break;
} }
check_cnt++; check_cnt++;
} }
@ -313,12 +313,12 @@ int jlink_init(void)
{ {
LOG_INFO("J-Link initial read failed, don't worry"); LOG_INFO("J-Link initial read failed, don't worry");
} }
LOG_INFO("J-Link JTAG Interface ready"); LOG_INFO("J-Link JTAG Interface ready");
jlink_reset(0, 0); jlink_reset(0, 0);
jlink_tap_init(); jlink_tap_init();
return ERROR_OK; return ERROR_OK;
} }
@ -350,20 +350,20 @@ void jlink_state_move(void)
int i; int i;
int tms = 0; int tms = 0;
u8 tms_scan = TAP_MOVE(cur_state, end_state); u8 tms_scan = TAP_MOVE(cur_state, end_state);
for (i = 0; i < 7; i++) for (i = 0; i < 7; i++)
{ {
tms = (tms_scan >> i) & 1; tms = (tms_scan >> i) & 1;
jlink_tap_append_step(tms, 0); jlink_tap_append_step(tms, 0);
} }
cur_state = end_state; cur_state = end_state;
} }
void jlink_path_move(int num_states, enum tap_state *path) void jlink_path_move(int num_states, enum tap_state *path)
{ {
int i; int i;
for (i = 0; i < num_states; i++) for (i = 0; i < num_states; i++)
{ {
if (path[i] == tap_transitions[cur_state].low) if (path[i] == tap_transitions[cur_state].low)
@ -379,32 +379,32 @@ void jlink_path_move(int num_states, enum tap_state *path)
LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition", tap_state_strings[cur_state], tap_state_strings[path[i]]); LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition", tap_state_strings[cur_state], tap_state_strings[path[i]]);
exit(-1); exit(-1);
} }
cur_state = path[i]; cur_state = path[i];
} }
end_state = cur_state; end_state = cur_state;
} }
void jlink_runtest(int num_cycles) void jlink_runtest(int num_cycles)
{ {
int i; int i;
enum tap_state saved_end_state = end_state; enum tap_state saved_end_state = end_state;
/* only do a state_move when we're not already in RTI */ /* only do a state_move when we're not already in RTI */
if (cur_state != TAP_RTI) if (cur_state != TAP_IDLE)
{ {
jlink_end_state(TAP_RTI); jlink_end_state(TAP_IDLE);
jlink_state_move(); jlink_state_move();
} }
/* execute num_cycles */ /* execute num_cycles */
for (i = 0; i < num_cycles; i++) for (i = 0; i < num_cycles; i++)
{ {
jlink_tap_append_step(0, 0); jlink_tap_append_step(0, 0);
} }
/* finish in end_state */ /* finish in end_state */
jlink_end_state(saved_end_state); jlink_end_state(saved_end_state);
if (cur_state != end_state) if (cur_state != end_state)
@ -416,25 +416,25 @@ void jlink_runtest(int num_cycles)
void jlink_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size, scan_command_t *command) void jlink_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size, scan_command_t *command)
{ {
enum tap_state saved_end_state; enum tap_state saved_end_state;
jlink_tap_ensure_space(1, scan_size + 8); jlink_tap_ensure_space(1, scan_size + 8);
saved_end_state = end_state; saved_end_state = end_state;
/* Move to appropriate scan state */ /* Move to appropriate scan state */
jlink_end_state(ir_scan ? TAP_SI : TAP_SD); jlink_end_state(ir_scan ? TAP_IRSHIFT : TAP_DRSHIFT);
jlink_state_move(); jlink_state_move();
jlink_end_state(saved_end_state); jlink_end_state(saved_end_state);
/* Scan */ /* Scan */
jlink_tap_append_scan(scan_size, buffer, command); jlink_tap_append_scan(scan_size, buffer, command);
/* We are in Exit1, go to Pause */ /* We are in Exit1, go to Pause */
jlink_tap_append_step(0, 0); jlink_tap_append_step(0, 0);
cur_state = ir_scan ? TAP_PI : TAP_PD; cur_state = ir_scan ? TAP_IRPAUSE : TAP_DRPAUSE;
if (cur_state != end_state) if (cur_state != end_state)
{ {
jlink_state_move(); jlink_state_move();
@ -444,7 +444,7 @@ void jlink_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size, sca
void jlink_reset(int trst, int srst) void jlink_reset(int trst, int srst)
{ {
LOG_DEBUG("trst: %i, srst: %i", trst, srst); LOG_DEBUG("trst: %i, srst: %i", trst, srst);
/* Signals are active low */ /* Signals are active low */
if (srst == 0) if (srst == 0)
{ {
@ -454,7 +454,7 @@ void jlink_reset(int trst, int srst)
{ {
jlink_simple_command(EMU_CMD_HW_RESET0); jlink_simple_command(EMU_CMD_HW_RESET0);
} }
if (trst == 0) if (trst == 0)
{ {
jlink_simple_command(EMU_CMD_HW_TRST1); jlink_simple_command(EMU_CMD_HW_TRST1);
@ -468,12 +468,12 @@ void jlink_reset(int trst, int srst)
void jlink_simple_command(u8 command) void jlink_simple_command(u8 command)
{ {
int result; int result;
DEBUG_JTAG_IO("0x%02x", command); DEBUG_JTAG_IO("0x%02x", command);
usb_out_buffer[0] = command; usb_out_buffer[0] = command;
result = jlink_usb_write(jlink_jtag_handle, 1); result = jlink_usb_write(jlink_jtag_handle, 1);
if (result != 1) if (result != 1)
{ {
LOG_ERROR("J-Link command 0x%02x failed (%d)", command, result); LOG_ERROR("J-Link command 0x%02x failed (%d)", command, result);
@ -483,10 +483,10 @@ void jlink_simple_command(u8 command)
int jlink_get_status(void) int jlink_get_status(void)
{ {
int result; int result;
jlink_simple_command(EMU_CMD_GET_STATE); jlink_simple_command(EMU_CMD_GET_STATE);
result = jlink_usb_read(jlink_jtag_handle); result = jlink_usb_read(jlink_jtag_handle);
if (result == 8) if (result == 8)
{ {
int vref = usb_in_buffer[0] + (usb_in_buffer[1] << 8); int vref = usb_in_buffer[0] + (usb_in_buffer[1] << 8);
@ -494,7 +494,7 @@ int jlink_get_status(void)
vref / 1000, vref % 1000, \ vref / 1000, vref % 1000, \
usb_in_buffer[2], usb_in_buffer[3], usb_in_buffer[4], \ usb_in_buffer[2], usb_in_buffer[3], usb_in_buffer[4], \
usb_in_buffer[5], usb_in_buffer[6], usb_in_buffer[7]); usb_in_buffer[5], usb_in_buffer[6], usb_in_buffer[7]);
if (vref < 1500) if (vref < 1500)
{ {
LOG_ERROR("Vref too low. Check Target Power\n"); LOG_ERROR("Vref too low. Check Target Power\n");
@ -504,7 +504,7 @@ int jlink_get_status(void)
{ {
LOG_ERROR("J-Link command EMU_CMD_GET_STATE failed (%d)\n", result); LOG_ERROR("J-Link command EMU_CMD_GET_STATE failed (%d)\n", result);
} }
return ERROR_OK; return ERROR_OK;
} }
@ -512,16 +512,16 @@ int jlink_get_version_info(void)
{ {
int result; int result;
int len = 0; int len = 0;
/* query hardware version */ /* query hardware version */
jlink_simple_command(EMU_CMD_VERSION); jlink_simple_command(EMU_CMD_VERSION);
result = jlink_usb_read(jlink_jtag_handle); result = jlink_usb_read(jlink_jtag_handle);
if (result == 2) if (result == 2)
{ {
len = buf_get_u32(usb_in_buffer, 0, 16); len = buf_get_u32(usb_in_buffer, 0, 16);
result = jlink_usb_read(jlink_jtag_handle); result = jlink_usb_read(jlink_jtag_handle);
if (result == len) if (result == len)
{ {
usb_in_buffer[result] = 0; usb_in_buffer[result] = 0;
@ -529,7 +529,7 @@ int jlink_get_version_info(void)
return ERROR_OK; return ERROR_OK;
} }
} }
LOG_ERROR("J-Link command EMU_CMD_VERSION failed (%d)\n", result); LOG_ERROR("J-Link command EMU_CMD_VERSION failed (%d)\n", result);
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
@ -541,7 +541,7 @@ int jlink_handle_jlink_info_command(struct command_context_s *cmd_ctx, char *cmd
/* attempt to get status */ /* attempt to get status */
jlink_get_status(); jlink_get_status();
} }
return ERROR_OK; return ERROR_OK;
} }
@ -581,7 +581,7 @@ void jlink_tap_ensure_space(int scans, int bits)
{ {
int available_scans = MAX_PENDING_SCAN_RESULTS - pending_scan_results_length; int available_scans = MAX_PENDING_SCAN_RESULTS - pending_scan_results_length;
int available_bits = JLINK_TAP_BUFFER_SIZE * 8 - tap_length; int available_bits = JLINK_TAP_BUFFER_SIZE * 8 - tap_length;
if (scans > available_scans || bits > available_bits) if (scans > available_scans || bits > available_bits)
{ {
jlink_tap_execute(); jlink_tap_execute();
@ -592,12 +592,12 @@ void jlink_tap_append_step(int tms, int tdi)
{ {
last_tms = tms; last_tms = tms;
int index = tap_length / 8; int index = tap_length / 8;
if (index < JLINK_TAP_BUFFER_SIZE) if (index < JLINK_TAP_BUFFER_SIZE)
{ {
int bit_index = tap_length % 8; int bit_index = tap_length % 8;
u8 bit = 1 << bit_index; u8 bit = 1 << bit_index;
if (tms) if (tms)
{ {
tms_buffer[index] |= bit; tms_buffer[index] |= bit;
@ -606,7 +606,7 @@ void jlink_tap_append_step(int tms, int tdi)
{ {
tms_buffer[index] &= ~bit; tms_buffer[index] &= ~bit;
} }
if (tdi) if (tdi)
{ {
tdi_buffer[index] |= bit; tdi_buffer[index] |= bit;
@ -615,7 +615,7 @@ void jlink_tap_append_step(int tms, int tdi)
{ {
tdi_buffer[index] &= ~bit; tdi_buffer[index] &= ~bit;
} }
tap_length++; tap_length++;
} }
else else
@ -628,12 +628,12 @@ void jlink_tap_append_scan(int length, u8 *buffer, scan_command_t *command)
{ {
pending_scan_result_t *pending_scan_result = &pending_scan_results_buffer[pending_scan_results_length]; pending_scan_result_t *pending_scan_result = &pending_scan_results_buffer[pending_scan_results_length];
int i; int i;
pending_scan_result->first = tap_length; pending_scan_result->first = tap_length;
pending_scan_result->length = length; pending_scan_result->length = length;
pending_scan_result->command = command; pending_scan_result->command = command;
pending_scan_result->buffer = buffer; pending_scan_result->buffer = buffer;
for (i = 0; i < length; i++) for (i = 0; i < length; i++)
{ {
jlink_tap_append_step((i < length-1 ? 0 : 1), (buffer[i/8] >> (i%8)) & 1); jlink_tap_append_step((i < length-1 ? 0 : 1), (buffer[i/8] >> (i%8)) & 1);
@ -650,7 +650,7 @@ int jlink_tap_execute(void)
int tdi_offset; int tdi_offset;
int i; int i;
int result; int result;
if (tap_length > 0) if (tap_length > 0)
{ {
/* Pad last byte so that tap_length is divisible by 8 */ /* Pad last byte so that tap_length is divisible by 8 */
@ -660,35 +660,35 @@ int jlink_tap_execute(void)
* analogous to free-running JTAG interfaces. */ * analogous to free-running JTAG interfaces. */
jlink_tap_append_step(last_tms, 0); jlink_tap_append_step(last_tms, 0);
} }
byte_length = tap_length / 8; byte_length = tap_length / 8;
usb_out_buffer[0] = EMU_CMD_HW_JTAG3; usb_out_buffer[0] = EMU_CMD_HW_JTAG3;
usb_out_buffer[1] = 0; usb_out_buffer[1] = 0;
usb_out_buffer[2] = (tap_length >> 0) & 0xff; usb_out_buffer[2] = (tap_length >> 0) & 0xff;
usb_out_buffer[3] = (tap_length >> 8) & 0xff; usb_out_buffer[3] = (tap_length >> 8) & 0xff;
tms_offset = 4; tms_offset = 4;
for (i = 0; i < byte_length; i++) for (i = 0; i < byte_length; i++)
{ {
usb_out_buffer[tms_offset + i] = tms_buffer[i]; usb_out_buffer[tms_offset + i] = tms_buffer[i];
} }
tdi_offset = tms_offset + byte_length; tdi_offset = tms_offset + byte_length;
for (i = 0; i < byte_length; i++) for (i = 0; i < byte_length; i++)
{ {
usb_out_buffer[tdi_offset + i] = tdi_buffer[i]; usb_out_buffer[tdi_offset + i] = tdi_buffer[i];
} }
result = jlink_usb_message(jlink_jtag_handle, 4 + 2 * byte_length, byte_length); result = jlink_usb_message(jlink_jtag_handle, 4 + 2 * byte_length, byte_length);
if (result == byte_length) if (result == byte_length)
{ {
for (i = 0; i < byte_length; i++) for (i = 0; i < byte_length; i++)
{ {
tdo_buffer[i] = usb_in_buffer[i]; tdo_buffer[i] = usb_in_buffer[i];
} }
for (i = 0; i < pending_scan_results_length; i++) for (i = 0; i < pending_scan_results_length; i++)
{ {
pending_scan_result_t *pending_scan_result = &pending_scan_results_buffer[i]; pending_scan_result_t *pending_scan_result = &pending_scan_results_buffer[i];
@ -696,22 +696,22 @@ int jlink_tap_execute(void)
int length = pending_scan_result->length; int length = pending_scan_result->length;
int first = pending_scan_result->first; int first = pending_scan_result->first;
scan_command_t *command = pending_scan_result->command; scan_command_t *command = pending_scan_result->command;
/* Copy to buffer */ /* Copy to buffer */
buf_set_buf(tdo_buffer, first, buffer, 0, length); buf_set_buf(tdo_buffer, first, buffer, 0, length);
DEBUG_JTAG_IO("pending scan result, length = %d", length); DEBUG_JTAG_IO("pending scan result, length = %d", length);
#ifdef _DEBUG_USB_COMMS_ #ifdef _DEBUG_USB_COMMS_
jlink_debug_buffer(buffer, byte_length); jlink_debug_buffer(buffer, byte_length);
#endif #endif
if (jtag_read_buffer(buffer, command) != ERROR_OK) if (jtag_read_buffer(buffer, command) != ERROR_OK)
{ {
jlink_tap_init(); jlink_tap_init();
return ERROR_JTAG_QUEUE_FAILED; return ERROR_JTAG_QUEUE_FAILED;
} }
if (pending_scan_result->buffer != NULL) if (pending_scan_result->buffer != NULL)
{ {
free(pending_scan_result->buffer); free(pending_scan_result->buffer);
@ -723,10 +723,10 @@ int jlink_tap_execute(void)
LOG_ERROR("jlink_tap_execute, wrong result %d, expected %d", result, byte_length); LOG_ERROR("jlink_tap_execute, wrong result %d, expected %d", result, byte_length);
return ERROR_JTAG_QUEUE_FAILED; return ERROR_JTAG_QUEUE_FAILED;
} }
jlink_tap_init(); jlink_tap_init();
} }
return ERROR_OK; return ERROR_OK;
} }
@ -738,19 +738,19 @@ jlink_jtag_t* jlink_usb_open()
struct usb_bus *busses; struct usb_bus *busses;
struct usb_bus *bus; struct usb_bus *bus;
struct usb_device *dev; struct usb_device *dev;
jlink_jtag_t *result; jlink_jtag_t *result;
result = (jlink_jtag_t*) malloc(sizeof(jlink_jtag_t)); result = (jlink_jtag_t*) malloc(sizeof(jlink_jtag_t));
usb_init(); usb_init();
usb_find_busses(); usb_find_busses();
usb_find_devices(); usb_find_devices();
busses = usb_get_busses(); busses = usb_get_busses();
/* find jlink_jtag device in usb bus */ /* find jlink_jtag device in usb bus */
for (bus = busses; bus; bus = bus->next) for (bus = busses; bus; bus = bus->next)
{ {
for (dev = bus->devices; dev; dev = dev->next) for (dev = bus->devices; dev; dev = dev->next)
@ -758,23 +758,23 @@ jlink_jtag_t* jlink_usb_open()
if ((dev->descriptor.idVendor == VID) && (dev->descriptor.idProduct == PID)) if ((dev->descriptor.idVendor == VID) && (dev->descriptor.idProduct == PID))
{ {
result->usb_handle = usb_open(dev); result->usb_handle = usb_open(dev);
/* usb_set_configuration required under win32 */ /* usb_set_configuration required under win32 */
usb_set_configuration(result->usb_handle, dev->config[0].bConfigurationValue); usb_set_configuration(result->usb_handle, dev->config[0].bConfigurationValue);
usb_claim_interface(result->usb_handle, 0); usb_claim_interface(result->usb_handle, 0);
#if 0 #if 0
/* /*
* This makes problems under Mac OS X. And is not needed * This makes problems under Mac OS X. And is not needed
* under Windows. Hopefully this will not break a linux build * under Windows. Hopefully this will not break a linux build
*/ */
usb_set_altinterface(result->usb_handle, 0); usb_set_altinterface(result->usb_handle, 0);
#endif #endif
return result; return result;
} }
} }
} }
free(result); free(result);
return NULL; return NULL;
} }
@ -790,7 +790,7 @@ int jlink_usb_message(jlink_jtag_t *jlink_jtag, int out_length, int in_length)
{ {
int result; int result;
int result2; int result2;
result = jlink_usb_write(jlink_jtag, out_length); result = jlink_usb_write(jlink_jtag, out_length);
if (result == out_length) if (result == out_length)
{ {
@ -811,7 +811,7 @@ int jlink_usb_message(jlink_jtag_t *jlink_jtag, int out_length, int in_length)
else else
{ {
LOG_ERROR("jlink_usb_read_emu_result (requested=0, result=%d)", usb_emu_result_buffer[0]); LOG_ERROR("jlink_usb_read_emu_result (requested=0, result=%d)", usb_emu_result_buffer[0]);
return -1; return -1;
} }
} }
else else
@ -830,7 +830,7 @@ int jlink_usb_message(jlink_jtag_t *jlink_jtag, int out_length, int in_length)
else else
{ {
LOG_ERROR("jlink_usb_read_emu_result (requested=0, result=%d)", usb_in_buffer[result]); LOG_ERROR("jlink_usb_read_emu_result (requested=0, result=%d)", usb_in_buffer[result]);
return -1; return -1;
} }
} }
} }
@ -851,18 +851,18 @@ int jlink_usb_message(jlink_jtag_t *jlink_jtag, int out_length, int in_length)
int jlink_usb_write(jlink_jtag_t *jlink_jtag, int out_length) int jlink_usb_write(jlink_jtag_t *jlink_jtag, int out_length)
{ {
int result; int result;
if (out_length > JLINK_OUT_BUFFER_SIZE) if (out_length > JLINK_OUT_BUFFER_SIZE)
{ {
LOG_ERROR("jlink_jtag_write illegal out_length=%d (max=%d)", out_length, JLINK_OUT_BUFFER_SIZE); LOG_ERROR("jlink_jtag_write illegal out_length=%d (max=%d)", out_length, JLINK_OUT_BUFFER_SIZE);
return -1; return -1;
} }
result = usb_bulk_write(jlink_jtag->usb_handle, JLINK_WRITE_ENDPOINT, \ result = usb_bulk_write(jlink_jtag->usb_handle, JLINK_WRITE_ENDPOINT, \
usb_out_buffer, out_length, JLINK_USB_TIMEOUT); usb_out_buffer, out_length, JLINK_USB_TIMEOUT);
DEBUG_JTAG_IO("jlink_usb_write, out_length = %d, result = %d", out_length, result); DEBUG_JTAG_IO("jlink_usb_write, out_length = %d, result = %d", out_length, result);
#ifdef _DEBUG_USB_COMMS_ #ifdef _DEBUG_USB_COMMS_
jlink_debug_buffer(usb_out_buffer, out_length); jlink_debug_buffer(usb_out_buffer, out_length);
#endif #endif
@ -876,7 +876,7 @@ int jlink_usb_read(jlink_jtag_t *jlink_jtag)
usb_in_buffer, JLINK_IN_BUFFER_SIZE, JLINK_USB_TIMEOUT); usb_in_buffer, JLINK_IN_BUFFER_SIZE, JLINK_USB_TIMEOUT);
DEBUG_JTAG_IO("jlink_usb_read, result = %d", result); DEBUG_JTAG_IO("jlink_usb_read, result = %d", result);
#ifdef _DEBUG_USB_COMMS_ #ifdef _DEBUG_USB_COMMS_
jlink_debug_buffer(usb_in_buffer, result); jlink_debug_buffer(usb_in_buffer, result);
#endif #endif
@ -890,7 +890,7 @@ int jlink_usb_read_emu_result(jlink_jtag_t *jlink_jtag)
usb_emu_result_buffer, JLINK_EMU_RESULT_BUFFER_SIZE, JLINK_USB_TIMEOUT); usb_emu_result_buffer, JLINK_EMU_RESULT_BUFFER_SIZE, JLINK_USB_TIMEOUT);
DEBUG_JTAG_IO("jlink_usb_read_result, result = %d", result); DEBUG_JTAG_IO("jlink_usb_read_result, result = %d", result);
#ifdef _DEBUG_USB_COMMS_ #ifdef _DEBUG_USB_COMMS_
jlink_debug_buffer(usb_emu_result_buffer, result); jlink_debug_buffer(usb_emu_result_buffer, result);
#endif #endif
@ -906,7 +906,7 @@ void jlink_debug_buffer(u8 *buffer, int length)
char s[4]; char s[4];
int i; int i;
int j; int j;
for (i = 0; i < length; i += BYTES_PER_LINE) for (i = 0; i < length; i += BYTES_PER_LINE)
{ {
snprintf(line, 5, "%04x", i); snprintf(line, 5, "%04x", i);

74
src/jtag/jtag.c
View File

@ -87,22 +87,22 @@ int tap_move_map[16] = {
tap_transition_t tap_transitions[16] = tap_transition_t tap_transitions[16] =
{ {
{TAP_TLR, TAP_RTI}, /* TLR */ {TAP_RESET, TAP_IDLE}, /* TLR */
{TAP_SIS, TAP_CD}, /* SDS */ {TAP_IRSELECT, TAP_DRCAPTURE}, /* SDS */
{TAP_E1D, TAP_SD}, /* CD */ {TAP_DREXIT1, TAP_DRSHIFT}, /* CD */
{TAP_E1D, TAP_SD}, /* SD */ {TAP_DREXIT1, TAP_DRSHIFT}, /* SD */
{TAP_UD, TAP_PD}, /* E1D */ {TAP_DRUPDATE, TAP_DRPAUSE}, /* E1D */
{TAP_E2D, TAP_PD}, /* PD */ {TAP_DREXIT2, TAP_DRPAUSE}, /* PD */
{TAP_UD, TAP_SD}, /* E2D */ {TAP_DRUPDATE, TAP_DRSHIFT}, /* E2D */
{TAP_SDS, TAP_RTI}, /* UD */ {TAP_DRSELECT, TAP_IDLE}, /* UD */
{TAP_SDS, TAP_RTI}, /* RTI */ {TAP_DRSELECT, TAP_IDLE}, /* RTI */
{TAP_TLR, TAP_CI}, /* SIS */ {TAP_RESET, TAP_IRCAPTURE}, /* SIS */
{TAP_E1I, TAP_SI}, /* CI */ {TAP_IREXIT1, TAP_IRSHIFT}, /* CI */
{TAP_E1I, TAP_SI}, /* SI */ {TAP_IREXIT1, TAP_IRSHIFT}, /* SI */
{TAP_UI, TAP_PI}, /* E1I */ {TAP_IRUPDATE, TAP_IRPAUSE}, /* E1I */
{TAP_E2I, TAP_PI}, /* PI */ {TAP_IREXIT2, TAP_IRPAUSE}, /* PI */
{TAP_UI, TAP_SI}, /* E2I */ {TAP_IRUPDATE, TAP_IRSHIFT}, /* E2I */
{TAP_SDS, TAP_RTI} /* UI */ {TAP_DRSELECT, TAP_IDLE} /* UI */
}; };
char* jtag_event_strings[] = char* jtag_event_strings[] =
@ -115,8 +115,8 @@ char* jtag_event_strings[] =
* inside the drivers, but we don't want to break * inside the drivers, but we don't want to break
* linking the drivers!!!! * linking the drivers!!!!
*/ */
enum tap_state end_state = TAP_TLR; enum tap_state end_state = TAP_RESET;
enum tap_state cur_state = TAP_TLR; enum tap_state cur_state = TAP_RESET;
int jtag_trst = 0; int jtag_trst = 0;
int jtag_srst = 0; int jtag_srst = 0;
@ -125,8 +125,8 @@ jtag_command_t **last_comand_pointer = &jtag_command_queue;
static jtag_tap_t *jtag_all_taps = NULL; static jtag_tap_t *jtag_all_taps = NULL;
enum reset_types jtag_reset_config = RESET_NONE; enum reset_types jtag_reset_config = RESET_NONE;
enum tap_state cmd_queue_end_state = TAP_TLR; enum tap_state cmd_queue_end_state = TAP_RESET;
enum tap_state cmd_queue_cur_state = TAP_TLR; enum tap_state cmd_queue_cur_state = TAP_RESET;
int jtag_verify_capture_ir = 1; int jtag_verify_capture_ir = 1;
@ -477,7 +477,7 @@ void* cmd_queue_alloc(size_t size)
* alignment. * alignment.
* *
* What I do not/have is a reasonable portable means * What I do not/have is a reasonable portable means
* to align by... * to align by...
* *
* The solution here, is based on these suggestions. * The solution here, is based on these suggestions.
* http://gcc.gnu.org/ml/gcc-help/2008-12/msg00041.html * http://gcc.gnu.org/ml/gcc-help/2008-12/msg00041.html
@ -493,8 +493,8 @@ void* cmd_queue_alloc(size_t size)
// The alignment process. // The alignment process.
size = (size + ALIGN_SIZE -1) & (~(ALIGN_SIZE-1)); size = (size + ALIGN_SIZE -1) & (~(ALIGN_SIZE-1));
// Done... // Done...
if (*p_page) if (*p_page)
{ {
@ -543,7 +543,7 @@ static void jtag_prelude1(void)
return; return;
} }
if (cmd_queue_end_state == TAP_TLR) if (cmd_queue_end_state == TAP_RESET)
jtag_call_event_callbacks(JTAG_TRST_ASSERTED); jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
} }
@ -959,7 +959,7 @@ int MINIDRIVER(interface_jtag_add_plain_dr_scan)(int num_fields, scan_field_t *f
void jtag_add_tlr(void) void jtag_add_tlr(void)
{ {
jtag_prelude(TAP_TLR); jtag_prelude(TAP_RESET);
int retval; int retval;
retval=interface_jtag_add_tlr(); retval=interface_jtag_add_tlr();
@ -969,7 +969,7 @@ void jtag_add_tlr(void)
int MINIDRIVER(interface_jtag_add_tlr)() int MINIDRIVER(interface_jtag_add_tlr)()
{ {
enum tap_state state = TAP_TLR; enum tap_state state = TAP_RESET;
jtag_command_t **last_cmd = jtag_get_last_command_p(); jtag_command_t **last_cmd = jtag_get_last_command_p();
/* allocate memory for a new list member */ /* allocate memory for a new list member */
@ -1000,9 +1000,9 @@ void jtag_add_pathmove(int num_states, enum tap_state *path)
for (i=0; i<num_states; i++) for (i=0; i<num_states; i++)
{ {
if (path[i] == TAP_TLR) if (path[i] == TAP_RESET)
{ {
LOG_ERROR("BUG: TAP_TLR is not a valid state for pathmove sequences"); LOG_ERROR("BUG: TAP_RESET is not a valid state for pathmove sequences");
exit(-1); exit(-1);
} }
if ((tap_transitions[cur_state].low != path[i])&& if ((tap_transitions[cur_state].low != path[i])&&
@ -1154,7 +1154,7 @@ void jtag_add_reset(int req_tlr_or_trst, int req_srst)
if (trst_with_tlr) if (trst_with_tlr)
{ {
LOG_DEBUG("JTAG reset with TLR instead of TRST"); LOG_DEBUG("JTAG reset with TLR instead of TRST");
jtag_add_end_state(TAP_TLR); jtag_add_end_state(TAP_RESET);
jtag_add_tlr(); jtag_add_tlr();
jtag_call_event_callbacks(JTAG_TRST_ASSERTED); jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
return; return;
@ -1166,7 +1166,7 @@ void jtag_add_reset(int req_tlr_or_trst, int req_srst)
* and inform possible listeners about this * and inform possible listeners about this
*/ */
LOG_DEBUG("TRST line asserted"); LOG_DEBUG("TRST line asserted");
cmd_queue_cur_state = TAP_TLR; cmd_queue_cur_state = TAP_RESET;
jtag_call_event_callbacks(JTAG_TRST_ASSERTED); jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
} }
else else
@ -1196,9 +1196,9 @@ int MINIDRIVER(interface_jtag_add_reset)(int req_trst, int req_srst)
void jtag_add_end_state(enum tap_state state) void jtag_add_end_state(enum tap_state state)
{ {
cmd_queue_end_state = state; cmd_queue_end_state = state;
if ((cmd_queue_end_state == TAP_SD)||(cmd_queue_end_state == TAP_SI)) if ((cmd_queue_end_state == TAP_DRSHIFT)||(cmd_queue_end_state == TAP_IRSHIFT))
{ {
LOG_ERROR("BUG: TAP_SD/SI can't be end state. Calling code should use a larger scan field"); LOG_ERROR("BUG: TAP_DRSHIFT/SI can't be end state. Calling code should use a larger scan field");
} }
} }
@ -1491,7 +1491,7 @@ int jtag_examine_chain(void)
buf_set_u32(idcode_buffer, i * 32, 32, 0x000000FF); buf_set_u32(idcode_buffer, i * 32, 32, 0x000000FF);
} }
jtag_add_plain_dr_scan(1, &field, TAP_TLR); jtag_add_plain_dr_scan(1, &field, TAP_RESET);
jtag_execute_queue(); jtag_execute_queue();
for (i = 0; i < JTAG_MAX_CHAIN_SIZE * 4; i++) for (i = 0; i < JTAG_MAX_CHAIN_SIZE * 4; i++)
@ -1583,7 +1583,7 @@ int jtag_examine_chain(void)
break; break;
} }
} }
/* If none of the expected ids matched, log an error */ /* If none of the expected ids matched, log an error */
if (ii == tap->expected_ids_cnt) { if (ii == tap->expected_ids_cnt) {
LOG_ERROR("JTAG tap: %s got: 0x%08x (mfg: 0x%3.3x, part: 0x%4.4x, ver: 0x%1.1x)", LOG_ERROR("JTAG tap: %s got: 0x%08x (mfg: 0x%3.3x, part: 0x%4.4x, ver: 0x%1.1x)",
@ -1662,7 +1662,7 @@ int jtag_validate_chain(void)
field.in_handler = NULL; field.in_handler = NULL;
field.in_handler_priv = NULL; field.in_handler_priv = NULL;
jtag_add_plain_ir_scan(1, &field, TAP_TLR); jtag_add_plain_ir_scan(1, &field, TAP_RESET);
jtag_execute_queue(); jtag_execute_queue();
tap = NULL; tap = NULL;
@ -1801,8 +1801,8 @@ jim_newtap_cmd( Jim_GetOptInfo *goi )
memcpy(new_expected_ids, pTap->expected_ids, sizeof(u32) * pTap->expected_ids_cnt); memcpy(new_expected_ids, pTap->expected_ids, sizeof(u32) * pTap->expected_ids_cnt);
new_expected_ids[pTap->expected_ids_cnt] = w; new_expected_ids[pTap->expected_ids_cnt] = w;
free(pTap->expected_ids); free(pTap->expected_ids);
pTap->expected_ids = new_expected_ids; pTap->expected_ids = new_expected_ids;
pTap->expected_ids_cnt++; pTap->expected_ids_cnt++;
break; break;

33
src/jtag/jtag.h
View File

@ -33,20 +33,15 @@
#define _DEBUG_JTAG_IO_ #define _DEBUG_JTAG_IO_
#endif #endif
/* Tap States /* 16 Tap States, from page 21 of ASSET InterTech, Inc.'s svf.pdf
* TLR - Test-Logic-Reset, RTI - Run-Test/Idle,
* SDS - Select-DR-Scan, CD - Capture-DR, SD - Shift-DR, E1D - Exit1-DR,
* PD - Pause-DR, E2D - Exit2-DR, UD - Update-DR,
* SIS - Select-IR-Scan, CI - Capture-IR, SI - Shift-IR, E1I - Exit1-IR,
* PI - Pause-IR, E2I - Exit2-IR, UI - Update-IR
*/ */
enum tap_state enum tap_state
{ {
TAP_TLR = 0x0, TAP_RTI = 0x8, TAP_RESET = 0x0, TAP_IDLE = 0x8,
TAP_SDS = 0x1, TAP_CD = 0x2, TAP_SD = 0x3, TAP_E1D = 0x4, TAP_DRSELECT = 0x1, TAP_DRCAPTURE = 0x2, TAP_DRSHIFT = 0x3, TAP_DREXIT1 = 0x4,
TAP_PD = 0x5, TAP_E2D = 0x6, TAP_UD = 0x7, TAP_DRPAUSE = 0x5, TAP_DREXIT2 = 0x6, TAP_DRUPDATE = 0x7,
TAP_SIS = 0x9, TAP_CI = 0xa, TAP_SI = 0xb, TAP_E1I = 0xc, TAP_IRSELECT = 0x9, TAP_IRCAPTURE = 0xa, TAP_IRSHIFT = 0xb, TAP_IREXIT1 = 0xc,
TAP_PI = 0xd, TAP_E2I = 0xe, TAP_UI = 0xf TAP_IRPAUSE = 0xd, TAP_IREXIT2 = 0xe, TAP_IRUPDATE = 0xf
}; };
typedef struct tap_transition_s typedef struct tap_transition_s
@ -325,7 +320,7 @@ extern int jtag_register_commands(struct command_context_s *cmd_ctx);
/* JTAG interface, can be implemented with a software or hardware fifo /* JTAG interface, can be implemented with a software or hardware fifo
* *
* TAP_SD and TAP_SI are illegal end states. TAP_SD/SI as end states * TAP_DRSHIFT and TAP_IRSHIFT are illegal end states. TAP_DRSHIFT/SI as end states
* can be emulated by using a larger scan. * can be emulated by using a larger scan.
* *
* Code that is relatively insensitive to the path(as long * Code that is relatively insensitive to the path(as long
@ -343,7 +338,7 @@ extern void jtag_add_plain_ir_scan(int num_fields, scan_field_t *fields, enum ta
extern int interface_jtag_add_plain_ir_scan(int num_fields, scan_field_t *fields, enum tap_state endstate); extern int interface_jtag_add_plain_ir_scan(int num_fields, scan_field_t *fields, enum tap_state endstate);
extern void jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum tap_state endstate); extern void jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum tap_state endstate);
extern int interface_jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum tap_state endstate); extern int interface_jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum tap_state endstate);
/* run a TAP_TLR reset. End state is TAP_TLR, regardless /* run a TAP_RESET reset. End state is TAP_RESET, regardless
* of start state. * of start state.
*/ */
extern void jtag_add_tlr(void); extern void jtag_add_tlr(void);
@ -364,7 +359,7 @@ extern int interface_jtag_add_tlr(void);
* all drivers can support this, but it is required for e.g. * all drivers can support this, but it is required for e.g.
* XScale and Xilinx support * XScale and Xilinx support
* *
* Note! TAP_TLR must not be used in the path! * Note! TAP_RESET must not be used in the path!
* *
* Note that the first on the list must be reachable * Note that the first on the list must be reachable
* via a single transition from the current state. * via a single transition from the current state.
@ -380,12 +375,12 @@ extern int interface_jtag_add_tlr(void);
*/ */
extern void jtag_add_pathmove(int num_states, enum tap_state *path); extern void jtag_add_pathmove(int num_states, enum tap_state *path);
extern int interface_jtag_add_pathmove(int num_states, enum tap_state *path); extern int interface_jtag_add_pathmove(int num_states, enum tap_state *path);
/* go to TAP_RTI, if we're not already there and cycle /* go to TAP_IDLE, if we're not already there and cycle
* precisely num_cycles in the TAP_RTI after which move * precisely num_cycles in the TAP_IDLE after which move
* to the end state, if it is != TAP_RTI * to the end state, if it is != TAP_IDLE
* *
* nb! num_cycles can be 0, in which case the fn will navigate * nb! num_cycles can be 0, in which case the fn will navigate
* to endstate via TAP_RTI * to endstate via TAP_IDLE
*/ */
extern void jtag_add_runtest(int num_cycles, enum tap_state endstate); extern void jtag_add_runtest(int num_cycles, enum tap_state endstate);
extern int interface_jtag_add_runtest(int num_cycles, enum tap_state endstate); extern int interface_jtag_add_runtest(int num_cycles, enum tap_state endstate);
@ -488,7 +483,7 @@ extern int jtag_verify_capture_ir;
#define MINIDRIVER(a) a #define MINIDRIVER(a) a
/* jtag_add_dr_out() is a faster version of jtag_add_dr_scan() /* jtag_add_dr_out() is a faster version of jtag_add_dr_scan()
* *
* Current or end_state can not be TAP_TLR. end_state can be -1 * Current or end_state can not be TAP_RESET. end_state can be -1
* *
* num_bits[i] is the number of bits to clock out from value[i] LSB first. * num_bits[i] is the number of bits to clock out from value[i] LSB first.
* *

14
src/jtag/usbprog.c
View File

@ -151,7 +151,7 @@ int usbprog_execute_queue(void)
#endif #endif
if (cmd->cmd.reset->trst == 1) if (cmd->cmd.reset->trst == 1)
{ {
cur_state = TAP_TLR; cur_state = TAP_RESET;
} }
usbprog_reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst); usbprog_reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
break; break;
@ -299,9 +299,9 @@ void usbprog_runtest(int num_cycles)
int i; int i;
/* only do a state_move when we're not already in RTI */ /* only do a state_move when we're not already in RTI */
if (cur_state != TAP_RTI) if (cur_state != TAP_IDLE)
{ {
usbprog_end_state(TAP_RTI); usbprog_end_state(TAP_IDLE);
usbprog_state_move(); usbprog_state_move();
} }
@ -336,9 +336,9 @@ void usbprog_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
enum tap_state saved_end_state = end_state; enum tap_state saved_end_state = end_state;
if (ir_scan) if (ir_scan)
usbprog_end_state(TAP_SI); usbprog_end_state(TAP_IRSHIFT);
else else
usbprog_end_state(TAP_SD); usbprog_end_state(TAP_DRSHIFT);
/* usbprog_jtag_tms_send(usbprog_jtag_handle); */ /* usbprog_jtag_tms_send(usbprog_jtag_handle); */
@ -361,9 +361,9 @@ void usbprog_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
} }
if (ir_scan) if (ir_scan)
cur_state = TAP_PI; cur_state = TAP_IRPAUSE;
else else
cur_state = TAP_PD; cur_state = TAP_DRPAUSE;
if (cur_state != end_state) if (cur_state != end_state)
usbprog_state_move(); usbprog_state_move();

38
src/jtag/zy1000.c
View File

@ -158,7 +158,7 @@ void zy1000_reset(int trst, int srst)
else else
{ {
/* Danger!!! if clk!=0 when in /* Danger!!! if clk!=0 when in
* idle in TAP_RTI, reset halt on str912 will fail. * idle in TAP_IDLE, reset halt on str912 will fail.
*/ */
ZY1000_POKE(ZY1000_JTAG_BASE+0x10, 0x00000001); ZY1000_POKE(ZY1000_JTAG_BASE+0x10, 0x00000001);
} }
@ -177,7 +177,7 @@ void zy1000_reset(int trst, int srst)
{ {
waitIdle(); waitIdle();
/* we're now in the TLR state until trst is deasserted */ /* we're now in the TLR state until trst is deasserted */
ZY1000_POKE(ZY1000_JTAG_BASE+0x20, TAP_TLR); ZY1000_POKE(ZY1000_JTAG_BASE+0x20, TAP_RESET);
} else } else
{ {
/* We'll get RCLK failure when we assert TRST, so clear any false positives here */ /* We'll get RCLK failure when we assert TRST, so clear any false positives here */
@ -303,7 +303,7 @@ int loadFile(const char *fileName, void **data, int *len)
if (fread(*data, 1, *len, pFile)!=*len) if (fread(*data, 1, *len, pFile)!=*len)
{ {
fclose(pFile); fclose(pFile);
free(*data); free(*data);
LOG_ERROR("Can't open %s\n", fileName); LOG_ERROR("Can't open %s\n", fileName);
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
@ -429,7 +429,7 @@ static __inline void scanFields(int num_fields, scan_field_t *fields, enum tap_s
enum tap_state pause_state; enum tap_state pause_state;
int l; int l;
k=num_bits-j; k=num_bits-j;
pause_state=(shiftState==TAP_SD)?TAP_SD:TAP_SI; pause_state=(shiftState==TAP_DRSHIFT)?TAP_DRSHIFT:TAP_IRSHIFT;
if (k>32) if (k>32)
{ {
k=32; k=32;
@ -437,7 +437,7 @@ static __inline void scanFields(int num_fields, scan_field_t *fields, enum tap_s
} else if (pause&&(i == num_fields-1)) } else if (pause&&(i == num_fields-1))
{ {
/* this was the last to shift out this time */ /* this was the last to shift out this time */
pause_state=(shiftState==TAP_SD)?TAP_PD:TAP_PI; pause_state=(shiftState==TAP_DRSHIFT)?TAP_DRPAUSE:TAP_IRPAUSE;
} }
// we have (num_bits+7)/8 bytes of bits to toggle out. // we have (num_bits+7)/8 bytes of bits to toggle out.
@ -520,7 +520,7 @@ int interface_jtag_add_ir_scan(int num_fields, scan_field_t *fields, enum tap_st
fields[j].in_check_mask = tap->expected_mask; fields[j].in_check_mask = tap->expected_mask;
} }
scanFields(1, fields+j, TAP_SI, pause); scanFields(1, fields+j, TAP_IRSHIFT, pause);
/* update device information */ /* update device information */
buf_cpy(fields[j].out_value, tap->cur_instr, scan_size); buf_cpy(fields[j].out_value, tap->cur_instr, scan_size);
@ -538,7 +538,7 @@ int interface_jtag_add_ir_scan(int num_fields, scan_field_t *fields, enum tap_st
memset(&tmp, 0, sizeof(tmp)); memset(&tmp, 0, sizeof(tmp));
tmp.out_value = ones; tmp.out_value = ones;
tmp.num_bits = scan_size; tmp.num_bits = scan_size;
scanFields(1, &tmp, TAP_SI, pause); scanFields(1, &tmp, TAP_IRSHIFT, pause);
/* update device information */ /* update device information */
buf_cpy(tmp.out_value, tap->cur_instr, scan_size); buf_cpy(tmp.out_value, tap->cur_instr, scan_size);
tap->bypass = 1; tap->bypass = 1;
@ -555,7 +555,7 @@ int interface_jtag_add_ir_scan(int num_fields, scan_field_t *fields, enum tap_st
int interface_jtag_add_plain_ir_scan(int num_fields, scan_field_t *fields, enum tap_state state) int interface_jtag_add_plain_ir_scan(int num_fields, scan_field_t *fields, enum tap_state state)
{ {
scanFields(num_fields, fields, TAP_SI, 1); scanFields(num_fields, fields, TAP_IRSHIFT, 1);
gotoEndState(); gotoEndState();
return ERROR_OK; return ERROR_OK;
@ -580,7 +580,7 @@ int interface_jtag_add_dr_scan(int num_fields, scan_field_t *fields, enum tap_st
{ {
found = 1; found = 1;
scanFields(1, fields+j, TAP_SD, pause); scanFields(1, fields+j, TAP_DRSHIFT, pause);
} }
} }
if (!found) if (!found)
@ -596,7 +596,7 @@ int interface_jtag_add_dr_scan(int num_fields, scan_field_t *fields, enum tap_st
tmp.in_handler = NULL; tmp.in_handler = NULL;
tmp.in_handler_priv = NULL; tmp.in_handler_priv = NULL;
scanFields(1, &tmp, TAP_SD, pause); scanFields(1, &tmp, TAP_DRSHIFT, pause);
} }
else else
{ {
@ -608,7 +608,7 @@ int interface_jtag_add_dr_scan(int num_fields, scan_field_t *fields, enum tap_st
int interface_jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum tap_state state) int interface_jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum tap_state state)
{ {
scanFields(num_fields, fields, TAP_SD, 1); scanFields(num_fields, fields, TAP_DRSHIFT, 1);
gotoEndState(); gotoEndState();
return ERROR_OK; return ERROR_OK;
} }
@ -616,7 +616,7 @@ int interface_jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum
int interface_jtag_add_tlr() int interface_jtag_add_tlr()
{ {
setCurrentState(TAP_TLR); setCurrentState(TAP_RESET);
return ERROR_OK; return ERROR_OK;
} }
@ -635,7 +635,7 @@ int interface_jtag_add_reset(int req_trst, int req_srst)
int interface_jtag_add_runtest(int num_cycles, enum tap_state state) int interface_jtag_add_runtest(int num_cycles, enum tap_state state)
{ {
/* num_cycles can be 0 */ /* num_cycles can be 0 */
setCurrentState(TAP_RTI); setCurrentState(TAP_IDLE);
/* execute num_cycles, 32 at the time. */ /* execute num_cycles, 32 at the time. */
int i; int i;
@ -647,14 +647,14 @@ int interface_jtag_add_runtest(int num_cycles, enum tap_state state)
{ {
num=num_cycles-i; num=num_cycles-i;
} }
shiftValueInner(TAP_RTI, TAP_RTI, num, 0); shiftValueInner(TAP_IDLE, TAP_IDLE, num, 0);
} }
#if !TEST_MANUAL() #if !TEST_MANUAL()
/* finish in end_state */ /* finish in end_state */
setCurrentState(state); setCurrentState(state);
#else #else
enum tap_state t=TAP_RTI; enum tap_state t=TAP_IDLE;
/* test manual drive code on any target */ /* test manual drive code on any target */
int tms; int tms;
u8 tms_scan = TAP_MOVE(t, state); u8 tms_scan = TAP_MOVE(t, state);
@ -734,8 +734,8 @@ void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little
int i; int i;
for (i = 0; i < count; i++) for (i = 0; i < count; i++)
{ {
shiftValueInner(TAP_SD, TAP_SD, 32, fast_target_buffer_get_u32(buffer, 1)); shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, fast_target_buffer_get_u32(buffer, 1));
shiftValueInner(TAP_SD, end_state, 6, reg_addr|(1<<5)); shiftValueInner(TAP_DRSHIFT, end_state, 6, reg_addr|(1<<5));
buffer+=4; buffer+=4;
} }
} else } else
@ -743,8 +743,8 @@ void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little
int i; int i;
for (i = 0; i < count; i++) for (i = 0; i < count; i++)
{ {
shiftValueInner(TAP_SD, TAP_SD, 32, fast_target_buffer_get_u32(buffer, 0)); shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, fast_target_buffer_get_u32(buffer, 0));
shiftValueInner(TAP_SD, end_state, 6, reg_addr|(1<<5)); shiftValueInner(TAP_DRSHIFT, end_state, 6, reg_addr|(1<<5));
buffer+=4; buffer+=4;
} }
} }

16
src/pld/virtex2.c
View File

@ -63,7 +63,7 @@ int virtex2_set_instr(jtag_tap_t *tap, u32 new_instr)
field.in_handler = NULL; field.in_handler = NULL;
field.in_handler_priv = NULL; field.in_handler_priv = NULL;
jtag_add_ir_scan(1, &field, TAP_RTI); jtag_add_ir_scan(1, &field, TAP_IDLE);
free(field.out_value); free(field.out_value);
} }
@ -95,7 +95,7 @@ int virtex2_send_32(struct pld_device_s *pld_device, int num_words, u32 *words)
virtex2_set_instr(virtex2_info->tap, 0x5); /* CFG_IN */ virtex2_set_instr(virtex2_info->tap, 0x5); /* CFG_IN */
jtag_add_dr_scan(1, &scan_field, TAP_PD); jtag_add_dr_scan(1, &scan_field, TAP_DRPAUSE);
free(values); free(values);
@ -128,7 +128,7 @@ int virtex2_receive_32(struct pld_device_s *pld_device, int num_words, u32 *word
while (num_words--) while (num_words--)
{ {
scan_field.in_handler_priv = words++; scan_field.in_handler_priv = words++;
jtag_add_dr_scan(1, &scan_field, TAP_PD); jtag_add_dr_scan(1, &scan_field, TAP_DRPAUSE);
} }
return ERROR_OK; return ERROR_OK;
@ -176,7 +176,7 @@ int virtex2_load(struct pld_device_s *pld_device, char *filename)
if ((retval = xilinx_read_bit_file(&bit_file, filename)) != ERROR_OK) if ((retval = xilinx_read_bit_file(&bit_file, filename)) != ERROR_OK)
return retval; return retval;
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
virtex2_set_instr(virtex2_info->tap, 0xb); /* JPROG_B */ virtex2_set_instr(virtex2_info->tap, 0xb); /* JPROG_B */
jtag_execute_queue(); jtag_execute_queue();
jtag_add_sleep(1000); jtag_add_sleep(1000);
@ -190,18 +190,18 @@ int virtex2_load(struct pld_device_s *pld_device, char *filename)
field.num_bits = bit_file.length * 8; field.num_bits = bit_file.length * 8;
field.out_value = bit_file.data; field.out_value = bit_file.data;
jtag_add_dr_scan(1, &field, TAP_PD); jtag_add_dr_scan(1, &field, TAP_DRPAUSE);
jtag_execute_queue(); jtag_execute_queue();
jtag_add_tlr(); jtag_add_tlr();
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
virtex2_set_instr(virtex2_info->tap, 0xc); /* JSTART */ virtex2_set_instr(virtex2_info->tap, 0xc); /* JSTART */
jtag_add_runtest(13, TAP_RTI); jtag_add_runtest(13, TAP_IDLE);
virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */ virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */
virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */ virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */
virtex2_set_instr(virtex2_info->tap, 0xc); /* JSTART */ virtex2_set_instr(virtex2_info->tap, 0xc); /* JSTART */
jtag_add_runtest(13, TAP_RTI); jtag_add_runtest(13, TAP_IDLE);
virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */ virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */
jtag_execute_queue(); jtag_execute_queue();

16
src/target/arm11.c
View File

@ -393,7 +393,7 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1); arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2); arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD); arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
} }
else else
{ {
@ -627,7 +627,7 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1); arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2); arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD); arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
} }
arm11_record_register_history(arm11); arm11_record_register_history(arm11);
@ -735,7 +735,7 @@ int arm11_halt(struct target_s *target)
return ERROR_OK; return ERROR_OK;
} }
arm11_add_IR(arm11, ARM11_HALT, TAP_RTI); arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
if((retval = jtag_execute_queue()) != ERROR_OK) if((retval = jtag_execute_queue()) != ERROR_OK)
{ {
@ -841,7 +841,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
arm11_leave_debug_state(arm11); arm11_leave_debug_state(arm11);
arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI); arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
if((retval = jtag_execute_queue()) != ERROR_OK) if((retval = jtag_execute_queue()) != ERROR_OK)
{ {
@ -956,7 +956,7 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
arm11_leave_debug_state(arm11); arm11_leave_debug_state(arm11);
arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI); arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
if((retval = jtag_execute_queue()) != ERROR_OK) if((retval = jtag_execute_queue()) != ERROR_OK)
{ {
@ -1571,7 +1571,7 @@ int arm11_examine(struct target_s *target)
arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field); arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD); arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
/* check DIDR */ /* check DIDR */
@ -1584,7 +1584,7 @@ int arm11_examine(struct target_s *target)
arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0); arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1); arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI); arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
if ((retval=jtag_execute_queue())!=ERROR_OK) if ((retval=jtag_execute_queue())!=ERROR_OK)
return retval; return retval;
@ -1832,7 +1832,7 @@ arm11_common_t * arm11_find_target(const char * arg)
{ {
jtag_tap_t *tap; jtag_tap_t *tap;
target_t * t; target_t * t;
tap = jtag_TapByString( arg ); tap = jtag_TapByString( arg );
if( !tap ){ if( !tap ){
return NULL; return NULL;

60
src/target/arm11_dbgtap.c
View File

@ -38,13 +38,13 @@
enum tap_state arm11_move_pi_to_si_via_ci[] = enum tap_state arm11_move_pi_to_si_via_ci[] =
{ {
TAP_E2I, TAP_UI, TAP_SDS, TAP_SIS, TAP_CI, TAP_SI TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT
}; };
int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state) int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state)
{ {
if (cmd_queue_cur_state == TAP_PI) if (cmd_queue_cur_state == TAP_IRPAUSE)
jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci); jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci);
jtag_add_ir_scan(num_fields, fields, state); jtag_add_ir_scan(num_fields, fields, state);
@ -53,12 +53,12 @@ int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state st
enum tap_state arm11_move_pd_to_sd_via_cd[] = enum tap_state arm11_move_pd_to_sd_via_cd[] =
{ {
TAP_E2D, TAP_UD, TAP_SDS, TAP_CD, TAP_SD TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
}; };
int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state) int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state)
{ {
if (cmd_queue_cur_state == TAP_PD) if (cmd_queue_cur_state == TAP_DRPAUSE)
jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd); jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd);
jtag_add_dr_scan(num_fields, fields, state); jtag_add_dr_scan(num_fields, fields, state);
@ -104,7 +104,7 @@ void arm11_add_IR(arm11_common_t * arm11, u8 instr, enum tap_state state)
jtag_tap_t *tap; jtag_tap_t *tap;
tap = arm11->jtag_info.tap; tap = arm11->jtag_info.tap;
if( tap == NULL ){ if( tap == NULL ){
/* FIX!!!! error is logged, but not propagated back up the call stack... */ /* FIX!!!! error is logged, but not propagated back up the call stack... */
LOG_ERROR( "tap is null here! This is bad!"); LOG_ERROR( "tap is null here! This is bad!");
return; return;
} }
@ -120,7 +120,7 @@ void arm11_add_IR(arm11_common_t * arm11, u8 instr, enum tap_state state)
arm11_setup_field(arm11, 5, &instr, NULL, &field); arm11_setup_field(arm11, 5, &instr, NULL, &field);
arm11_add_ir_scan_vc(1, &field, state == -1 ? TAP_PI : state); arm11_add_ir_scan_vc(1, &field, state == -1 ? TAP_IRPAUSE : state);
} }
/** Verify shifted out data from Scan Chain Register (SCREG) /** Verify shifted out data from Scan Chain Register (SCREG)
@ -135,8 +135,8 @@ static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s
if (v != 0x10) if (v != 0x10)
{ {
LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v); LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v);
return ERROR_FAIL; return ERROR_FAIL;
} }
JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v); JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v);
@ -179,7 +179,7 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, enum tap_state sta
field.in_handler = arm11_in_handler_SCAN_N; field.in_handler = arm11_in_handler_SCAN_N;
arm11_add_dr_scan_vc(1, &field, state == -1 ? TAP_PD : state); arm11_add_dr_scan_vc(1, &field, state == -1 ? TAP_DRPAUSE : state);
} }
/** Write an instruction into the ITR register /** Write an instruction into the ITR register
@ -194,7 +194,7 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, enum tap_state sta
* \remarks By default this ends with Run-Test/Idle state * \remarks By default this ends with Run-Test/Idle state
* and causes the instruction to be executed. If * and causes the instruction to be executed. If
* a subsequent write to DTR is needed before * a subsequent write to DTR is needed before
* executing the instruction then TAP_PD should be * executing the instruction then TAP_DRPAUSE should be
* passed to \p state. * passed to \p state.
* *
* \remarks This adds to the JTAG command queue but does \em not execute it. * \remarks This adds to the JTAG command queue but does \em not execute it.
@ -208,7 +208,7 @@ void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, enum tap_
arm11_setup_field(arm11, 32, &inst, NULL, itr + 0); arm11_setup_field(arm11, 32, &inst, NULL, itr + 0);
arm11_setup_field(arm11, 1, NULL, flag, itr + 1); arm11_setup_field(arm11, 1, NULL, flag, itr + 1);
arm11_add_dr_scan_vc(asizeof(itr), itr, state == -1 ? TAP_RTI : state); arm11_add_dr_scan_vc(asizeof(itr), itr, state == -1 ? TAP_IDLE : state);
} }
/** Read the Debug Status and Control Register (DSCR) /** Read the Debug Status and Control Register (DSCR)
@ -231,12 +231,12 @@ u32 arm11_read_DSCR(arm11_common_t * arm11)
arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field); arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field);
arm11_add_dr_scan_vc(1, &chain1_field, TAP_PD); arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
jtag_execute_queue(); jtag_execute_queue();
if (arm11->last_dscr != dscr) if (arm11->last_dscr != dscr)
JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr); JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
arm11->last_dscr = dscr; arm11->last_dscr = dscr;
@ -262,7 +262,7 @@ void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field); arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field);
arm11_add_dr_scan_vc(1, &chain1_field, TAP_PD); arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
jtag_execute_queue(); jtag_execute_queue();
@ -369,13 +369,13 @@ void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
while (count--) while (count--)
{ {
arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_RTI); arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_IDLE);
while (1) while (1)
{ {
u8 flag; u8 flag;
arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_RTI : TAP_PD); arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
jtag_execute_queue(); jtag_execute_queue();
@ -416,7 +416,7 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data
{ {
arm11_add_IR(arm11, ARM11_ITRSEL, -1); arm11_add_IR(arm11, ARM11_ITRSEL, -1);
arm11_add_debug_INST(arm11, opcode, NULL, TAP_PD); arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
arm11_add_IR(arm11, ARM11_EXTEST, -1); arm11_add_IR(arm11, ARM11_EXTEST, -1);
@ -436,7 +436,7 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data
{ {
Data = *data; Data = *data;
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_RTI); arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
jtag_execute_queue(); jtag_execute_queue();
JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry); JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
@ -452,7 +452,7 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data
{ {
Data = 0; Data = 0;
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD); arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
jtag_execute_queue(); jtag_execute_queue();
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry); JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
@ -462,18 +462,18 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data
/** JTAG path for arm11_run_instr_data_to_core_noack /** JTAG path for arm11_run_instr_data_to_core_noack
* *
* The repeated TAP_RTI's do not cause a repeated execution * The repeated TAP_IDLE's do not cause a repeated execution
* if passed without leaving the state. * if passed without leaving the state.
* *
* Since this is more than 7 bits (adjustable via adding more * Since this is more than 7 bits (adjustable via adding more
* TAP_RTI's) it produces an artificial delay in the lower * TAP_IDLE's) it produces an artificial delay in the lower
* layer (FT2232) that is long enough to finish execution on * layer (FT2232) that is long enough to finish execution on
* the core but still shorter than any manually inducible delays. * the core but still shorter than any manually inducible delays.
* *
*/ */
enum tap_state arm11_MOVE_PD_RTI_PD_with_delay[] = enum tap_state arm11_MOVE_PD_RTI_PD_with_delay[] =
{ {
TAP_E2D, TAP_UD, TAP_RTI, TAP_RTI, TAP_RTI, TAP_SDS, TAP_CD, TAP_SD TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
}; };
@ -497,7 +497,7 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32
{ {
arm11_add_IR(arm11, ARM11_ITRSEL, -1); arm11_add_IR(arm11, ARM11_ITRSEL, -1);
arm11_add_debug_INST(arm11, opcode, NULL, TAP_PD); arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
arm11_add_IR(arm11, ARM11_EXTEST, -1); arm11_add_IR(arm11, ARM11_EXTEST, -1);
@ -517,13 +517,13 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32
if (count) if (count)
{ {
jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_PD); jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
jtag_add_pathmove(asizeof(arm11_MOVE_PD_RTI_PD_with_delay), jtag_add_pathmove(asizeof(arm11_MOVE_PD_RTI_PD_with_delay),
arm11_MOVE_PD_RTI_PD_with_delay); arm11_MOVE_PD_RTI_PD_with_delay);
} }
else else
{ {
jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_RTI); jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
} }
} }
@ -532,7 +532,7 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32
chain5_fields[0].out_value = 0; chain5_fields[0].out_value = 0;
chain5_fields[1].in_value = ReadyPos++; chain5_fields[1].in_value = ReadyPos++;
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD); arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
jtag_execute_queue(); jtag_execute_queue();
@ -586,7 +586,7 @@ void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * da
{ {
arm11_add_IR(arm11, ARM11_ITRSEL, -1); arm11_add_IR(arm11, ARM11_ITRSEL, -1);
arm11_add_debug_INST(arm11, opcode, NULL, TAP_RTI); arm11_add_debug_INST(arm11, opcode, NULL, TAP_IDLE);
arm11_add_IR(arm11, ARM11_INTEST, -1); arm11_add_IR(arm11, ARM11_INTEST, -1);
@ -604,7 +604,7 @@ void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * da
{ {
do do
{ {
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_RTI : TAP_PD); arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
jtag_execute_queue(); jtag_execute_queue();
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry); JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
@ -699,11 +699,11 @@ void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t
AddressOut = 0; AddressOut = 0;
} }
do do
{ {
JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW); JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_PD); arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE);
jtag_execute_queue(); jtag_execute_queue();
JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready); JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);

136
src/target/arm720t.c
View File

@ -64,7 +64,7 @@ target_type_t arm720t_target =
.assert_reset = arm7_9_assert_reset, .assert_reset = arm7_9_assert_reset,
.deassert_reset = arm7_9_deassert_reset, .deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm720t_soft_reset_halt, .soft_reset_halt = arm720t_soft_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list, .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.read_memory = arm720t_read_memory, .read_memory = arm720t_read_memory,
@ -72,7 +72,7 @@ target_type_t arm720t_target =
.bulk_write_memory = arm7_9_bulk_write_memory, .bulk_write_memory = arm7_9_bulk_write_memory,
.checksum_memory = arm7_9_checksum_memory, .checksum_memory = arm7_9_checksum_memory,
.blank_check_memory = arm7_9_blank_check_memory, .blank_check_memory = arm7_9_blank_check_memory,
.run_algorithm = armv4_5_run_algorithm, .run_algorithm = armv4_5_run_algorithm,
.add_breakpoint = arm7_9_add_breakpoint, .add_breakpoint = arm7_9_add_breakpoint,
@ -96,10 +96,10 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
scan_field_t fields[2]; scan_field_t fields[2];
u8 out_buf[4]; u8 out_buf[4];
u8 instruction_buf = instruction; u8 instruction_buf = instruction;
buf_set_u32(out_buf, 0, 32, flip_u32(out, 32)); buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
jtag_add_end_state(TAP_PD); jtag_add_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
{ {
return retval; return retval;
@ -108,7 +108,7 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
{ {
return retval; return retval;
} }
fields[0].tap = jtag_info->tap; fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1; fields[0].num_bits = 1;
fields[0].out_value = &instruction_buf; fields[0].out_value = &instruction_buf;
@ -135,7 +135,7 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
} }
fields[1].in_check_value = NULL; fields[1].in_check_value = NULL;
fields[1].in_check_mask = NULL; fields[1].in_check_mask = NULL;
jtag_add_dr_scan(2, fields, -1); jtag_add_dr_scan(2, fields, -1);
if (clock) if (clock)
@ -171,7 +171,7 @@ int arm720t_read_cp15(target_t *target, u32 opcode, u32 *value)
arm720t_scan_cp15(target, 0x0, NULL, 0, 1); arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
/* "EXECUTE" stage (3), CDATA is read */ /* "EXECUTE" stage (3), CDATA is read */
arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1); arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
return ERROR_OK; return ERROR_OK;
} }
@ -197,9 +197,9 @@ u32 arm720t_get_ttb(target_t *target)
arm720t_read_cp15(target, 0xee120f10, &ttb); arm720t_read_cp15(target, 0xee120f10, &ttb);
jtag_execute_queue(); jtag_execute_queue();
ttb &= 0xffffc000; ttb &= 0xffffc000;
return ttb; return ttb;
} }
@ -210,10 +210,10 @@ void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_
/* read cp15 control register */ /* read cp15 control register */
arm720t_read_cp15(target, 0xee110f10, &cp15_control); arm720t_read_cp15(target, 0xee110f10, &cp15_control);
jtag_execute_queue(); jtag_execute_queue();
if (mmu) if (mmu)
cp15_control &= ~0x1U; cp15_control &= ~0x1U;
if (d_u_cache || i_cache) if (d_u_cache || i_cache)
cp15_control &= ~0x4U; cp15_control &= ~0x4U;
@ -227,13 +227,13 @@ void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_c
/* read cp15 control register */ /* read cp15 control register */
arm720t_read_cp15(target, 0xee110f10, &cp15_control); arm720t_read_cp15(target, 0xee110f10, &cp15_control);
jtag_execute_queue(); jtag_execute_queue();
if (mmu) if (mmu)
cp15_control |= 0x1U; cp15_control |= 0x1U;
if (d_u_cache || i_cache) if (d_u_cache || i_cache)
cp15_control |= 0x4U; cp15_control |= 0x4U;
arm720t_write_cp15(target, 0xee010f10, cp15_control); arm720t_write_cp15(target, 0xee010f10, cp15_control);
} }
@ -243,7 +243,7 @@ void arm720t_post_debug_entry(target_t *target)
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
arm720t_common_t *arm720t = arm7tdmi->arch_info; arm720t_common_t *arm720t = arm7tdmi->arch_info;
/* examine cp15 control reg */ /* examine cp15 control reg */
arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg); arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
jtag_execute_queue(); jtag_execute_queue();
@ -265,7 +265,7 @@ void arm720t_pre_restore_context(target_t *target)
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
arm720t_common_t *arm720t = arm7tdmi->arch_info; arm720t_common_t *arm720t = arm7tdmi->arch_info;
/* restore i/d fault status and address register */ /* restore i/d fault status and address register */
arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg); arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg); arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
@ -277,35 +277,35 @@ int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, ar
arm7_9_common_t *arm7_9; arm7_9_common_t *arm7_9;
arm7tdmi_common_t *arm7tdmi; arm7tdmi_common_t *arm7tdmi;
arm720t_common_t *arm720t; arm720t_common_t *arm720t;
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{ {
return -1; return -1;
} }
arm7_9 = armv4_5->arch_info; arm7_9 = armv4_5->arch_info;
if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC) if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
{ {
return -1; return -1;
} }
arm7tdmi = arm7_9->arch_info; arm7tdmi = arm7_9->arch_info;
if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC) if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC)
{ {
return -1; return -1;
} }
arm720t = arm7tdmi->arch_info; arm720t = arm7tdmi->arch_info;
if (arm720t->common_magic != ARM720T_COMMON_MAGIC) if (arm720t->common_magic != ARM720T_COMMON_MAGIC)
{ {
return -1; return -1;
} }
*armv4_5_p = armv4_5; *armv4_5_p = armv4_5;
*arm7_9_p = arm7_9; *arm7_9_p = arm7_9;
*arm7tdmi_p = arm7tdmi; *arm7tdmi_p = arm7tdmi;
*arm720t_p = arm720t; *arm720t_p = arm720t;
return ERROR_OK; return ERROR_OK;
} }
@ -315,18 +315,18 @@ int arm720t_arch_state(struct target_s *target)
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
arm720t_common_t *arm720t = arm7tdmi->arch_info; arm720t_common_t *arm720t = arm7tdmi->arch_info;
char *state[] = char *state[] =
{ {
"disabled", "enabled" "disabled", "enabled"
}; };
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{ {
LOG_ERROR("BUG: called for a non-ARMv4/5 target"); LOG_ERROR("BUG: called for a non-ARMv4/5 target");
exit(-1); exit(-1);
} }
LOG_USER("target halted in %s state due to %s, current mode: %s\n" LOG_USER("target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8x pc: 0x%8.8x\n" "cpsr: 0x%8.8x pc: 0x%8.8x\n"
"MMU: %s, Cache: %s", "MMU: %s, Cache: %s",
@ -337,7 +337,7 @@ int arm720t_arch_state(struct target_s *target)
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
state[arm720t->armv4_5_mmu.mmu_enabled], state[arm720t->armv4_5_mmu.mmu_enabled],
state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]); state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
return ERROR_OK; return ERROR_OK;
} }
@ -348,23 +348,23 @@ int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 coun
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
arm720t_common_t *arm720t = arm7tdmi->arch_info; arm720t_common_t *arm720t = arm7tdmi->arch_info;
/* disable cache, but leave MMU enabled */ /* disable cache, but leave MMU enabled */
if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
arm720t_disable_mmu_caches(target, 0, 1, 0); arm720t_disable_mmu_caches(target, 0, 1, 0);
retval = arm7_9_read_memory(target, address, size, count, buffer); retval = arm7_9_read_memory(target, address, size, count, buffer);
if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
arm720t_enable_mmu_caches(target, 0, 1, 0); arm720t_enable_mmu_caches(target, 0, 1, 0);
return retval; return retval;
} }
int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
{ {
int retval; int retval;
if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK) if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
return retval; return retval;
@ -379,12 +379,12 @@ int arm720t_soft_reset_halt(struct target_s *target)
arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
arm720t_common_t *arm720t = arm7tdmi->arch_info; arm720t_common_t *arm720t = arm7tdmi->arch_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
if ((retval = target_halt(target)) != ERROR_OK) if ((retval = target_halt(target)) != ERROR_OK)
{ {
return retval; return retval;
} }
long long then=timeval_ms(); long long then=timeval_ms();
int timeout; int timeout;
while (!(timeout=((timeval_ms()-then)>1000))) while (!(timeout=((timeval_ms()-then)>1000)))
@ -413,22 +413,22 @@ int arm720t_soft_reset_halt(struct target_s *target)
LOG_ERROR("Failed to halt CPU after 1 sec"); LOG_ERROR("Failed to halt CPU after 1 sec");
return ERROR_TARGET_TIMEOUT; return ERROR_TARGET_TIMEOUT;
} }
target->state = TARGET_HALTED; target->state = TARGET_HALTED;
/* SVC, ARM state, IRQ and FIQ disabled */ /* SVC, ARM state, IRQ and FIQ disabled */
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3); buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
/* start fetching from 0x0 */ /* start fetching from 0x0 */
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].dirty = 1;
armv4_5->core_cache->reg_list[15].valid = 1; armv4_5->core_cache->reg_list[15].valid = 1;
armv4_5->core_mode = ARMV4_5_MODE_SVC; armv4_5->core_mode = ARMV4_5_MODE_SVC;
armv4_5->core_state = ARMV4_5_STATE_ARM; armv4_5->core_state = ARMV4_5_STATE_ARM;
arm720t_disable_mmu_caches(target, 1, 1, 1); arm720t_disable_mmu_caches(target, 1, 1, 1);
arm720t->armv4_5_mmu.mmu_enabled = 0; arm720t->armv4_5_mmu.mmu_enabled = 0;
arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
@ -438,21 +438,21 @@ int arm720t_soft_reset_halt(struct target_s *target)
{ {
return retval; return retval;
} }
return ERROR_OK; return ERROR_OK;
} }
int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target) int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
{ {
arm7tdmi_init_target(cmd_ctx, target); arm7tdmi_init_target(cmd_ctx, target);
return ERROR_OK; return ERROR_OK;
} }
int arm720t_quit(void) int arm720t_quit(void)
{ {
return ERROR_OK; return ERROR_OK;
} }
@ -460,15 +460,15 @@ int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap
{ {
arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common; arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common; arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
arm7tdmi_init_arch_info(target, arm7tdmi, tap, variant); arm7tdmi_init_arch_info(target, arm7tdmi, tap, variant);
arm7tdmi->arch_info = arm720t; arm7tdmi->arch_info = arm720t;
arm720t->common_magic = ARM720T_COMMON_MAGIC; arm720t->common_magic = ARM720T_COMMON_MAGIC;
arm7_9->post_debug_entry = arm720t_post_debug_entry; arm7_9->post_debug_entry = arm720t_post_debug_entry;
arm7_9->pre_restore_context = arm720t_pre_restore_context; arm7_9->pre_restore_context = arm720t_pre_restore_context;
arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1; arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb; arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory; arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
@ -477,14 +477,14 @@ int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap
arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches; arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
arm720t->armv4_5_mmu.has_tiny_pages = 0; arm720t->armv4_5_mmu.has_tiny_pages = 0;
arm720t->armv4_5_mmu.mmu_enabled = 0; arm720t->armv4_5_mmu.mmu_enabled = 0;
return ERROR_OK; return ERROR_OK;
} }
int arm720t_target_create(struct target_s *target, Jim_Interp *interp) int arm720t_target_create(struct target_s *target, Jim_Interp *interp)
{ {
arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t)); arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t));
arm720t_init_arch_info(target, arm720t, target->tap, target->variant); arm720t_init_arch_info(target, arm720t, target->tap, target->variant);
return ERROR_OK; return ERROR_OK;
@ -494,10 +494,10 @@ int arm720t_register_commands(struct command_context_s *cmd_ctx)
{ {
int retval; int retval;
command_t *arm720t_cmd; command_t *arm720t_cmd;
retval = arm7tdmi_register_commands(cmd_ctx); retval = arm7tdmi_register_commands(cmd_ctx);
arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands"); arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands");
register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]"); register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]");
@ -510,7 +510,7 @@ int arm720t_register_commands(struct command_context_s *cmd_ctx)
register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>"); register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>"); register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>"); register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
return ERROR_OK; return ERROR_OK;
} }
@ -529,9 +529,9 @@ int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
command_print(cmd_ctx, "current target isn't an ARM720t target"); command_print(cmd_ctx, "current target isn't an ARM720t target");
return ERROR_OK; return ERROR_OK;
} }
jtag_info = &arm7_9->jtag_info; jtag_info = &arm7_9->jtag_info;
if (target->state != TARGET_HALTED) if (target->state != TARGET_HALTED)
{ {
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
@ -556,7 +556,7 @@ int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
{ {
return retval; return retval;
} }
command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value); command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
} }
else if (argc == 2) else if (argc == 2)
@ -575,7 +575,7 @@ int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
} }
int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
{ {
target_t *target = get_current_target(cmd_ctx); target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5; armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9; arm7_9_common_t *arm7_9;
@ -588,20 +588,20 @@ int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char
command_print(cmd_ctx, "current target isn't an ARM720t target"); command_print(cmd_ctx, "current target isn't an ARM720t target");
return ERROR_OK; return ERROR_OK;
} }
jtag_info = &arm7_9->jtag_info; jtag_info = &arm7_9->jtag_info;
if (target->state != TARGET_HALTED) if (target->state != TARGET_HALTED)
{ {
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
return ERROR_OK; return ERROR_OK;
} }
return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu); return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
} }
int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
{ {
target_t *target = get_current_target(cmd_ctx); target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5; armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9; arm7_9_common_t *arm7_9;
@ -614,20 +614,20 @@ int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char *
command_print(cmd_ctx, "current target isn't an ARM720t target"); command_print(cmd_ctx, "current target isn't an ARM720t target");
return ERROR_OK; return ERROR_OK;
} }
jtag_info = &arm7_9->jtag_info; jtag_info = &arm7_9->jtag_info;
if (target->state != TARGET_HALTED) if (target->state != TARGET_HALTED)
{ {
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
return ERROR_OK; return ERROR_OK;
} }
return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu); return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
} }
int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
{ {
target_t *target = get_current_target(cmd_ctx); target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5; armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9; arm7_9_common_t *arm7_9;
@ -640,14 +640,14 @@ int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char *
command_print(cmd_ctx, "current target isn't an ARM720t target"); command_print(cmd_ctx, "current target isn't an ARM720t target");
return ERROR_OK; return ERROR_OK;
} }
jtag_info = &arm7_9->jtag_info; jtag_info = &arm7_9->jtag_info;
if (target->state != TARGET_HALTED) if (target->state != TARGET_HALTED)
{ {
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
return ERROR_OK; return ERROR_OK;
} }
return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu); return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
} }

8
src/target/arm7_9_common.c
View File

@ -584,7 +584,7 @@ int arm7_9_execute_sys_speed(struct target_s *target)
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* set RESTART instruction */ /* set RESTART instruction */
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
if (arm7_9->need_bypass_before_restart) { if (arm7_9->need_bypass_before_restart) {
arm7_9->need_bypass_before_restart = 0; arm7_9->need_bypass_before_restart = 0;
arm_jtag_set_instr(jtag_info, 0xf, NULL); arm_jtag_set_instr(jtag_info, 0xf, NULL);
@ -630,7 +630,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* set RESTART instruction */ /* set RESTART instruction */
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
if (arm7_9->need_bypass_before_restart) { if (arm7_9->need_bypass_before_restart) {
arm7_9->need_bypass_before_restart = 0; arm7_9->need_bypass_before_restart = 0;
arm_jtag_set_instr(jtag_info, 0xf, NULL); arm_jtag_set_instr(jtag_info, 0xf, NULL);
@ -1492,14 +1492,14 @@ int arm7_9_restart_core(struct target_s *target)
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* set RESTART instruction */ /* set RESTART instruction */
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
if (arm7_9->need_bypass_before_restart) { if (arm7_9->need_bypass_before_restart) {
arm7_9->need_bypass_before_restart = 0; arm7_9->need_bypass_before_restart = 0;
arm_jtag_set_instr(jtag_info, 0xf, NULL); arm_jtag_set_instr(jtag_info, 0xf, NULL);
} }
arm_jtag_set_instr(jtag_info, 0x4, NULL); arm_jtag_set_instr(jtag_info, 0x4, NULL);
jtag_add_runtest(1, TAP_RTI); jtag_add_runtest(1, TAP_IDLE);
return jtag_execute_queue(); return jtag_execute_queue();
} }

172
src/target/arm7tdmi.c
View File

@ -55,7 +55,7 @@ int arm7tdmi_quit(void);
/* target function declarations */ /* target function declarations */
int arm7tdmi_poll(struct target_s *target); int arm7tdmi_poll(struct target_s *target);
int arm7tdmi_halt(target_t *target); int arm7tdmi_halt(target_t *target);
target_type_t arm7tdmi_target = target_type_t arm7tdmi_target =
{ {
.name = "arm7tdmi", .name = "arm7tdmi",
@ -74,15 +74,15 @@ target_type_t arm7tdmi_target =
.soft_reset_halt = arm7_9_soft_reset_halt, .soft_reset_halt = arm7_9_soft_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list, .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.read_memory = arm7_9_read_memory, .read_memory = arm7_9_read_memory,
.write_memory = arm7_9_write_memory, .write_memory = arm7_9_write_memory,
.bulk_write_memory = arm7_9_bulk_write_memory, .bulk_write_memory = arm7_9_bulk_write_memory,
.checksum_memory = arm7_9_checksum_memory, .checksum_memory = arm7_9_checksum_memory,
.blank_check_memory = arm7_9_blank_check_memory, .blank_check_memory = arm7_9_blank_check_memory,
.run_algorithm = armv4_5_run_algorithm, .run_algorithm = armv4_5_run_algorithm,
.add_breakpoint = arm7_9_add_breakpoint, .add_breakpoint = arm7_9_add_breakpoint,
.remove_breakpoint = arm7_9_remove_breakpoint, .remove_breakpoint = arm7_9_remove_breakpoint,
.add_watchpoint = arm7_9_add_watchpoint, .add_watchpoint = arm7_9_add_watchpoint,
@ -101,7 +101,7 @@ int arm7tdmi_examine_debug_reason(target_t *target)
/* get pointers to arch-specific information */ /* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
/* only check the debug reason if we don't know it already */ /* only check the debug reason if we don't know it already */
if ((target->debug_reason != DBG_REASON_DBGRQ) if ((target->debug_reason != DBG_REASON_DBGRQ)
&& (target->debug_reason != DBG_REASON_SINGLESTEP)) && (target->debug_reason != DBG_REASON_SINGLESTEP))
@ -109,8 +109,8 @@ int arm7tdmi_examine_debug_reason(target_t *target)
scan_field_t fields[2]; scan_field_t fields[2];
u8 databus[4]; u8 databus[4];
u8 breakpoint; u8 breakpoint;
jtag_add_end_state(TAP_PD); jtag_add_end_state(TAP_DRPAUSE);
fields[0].tap = arm7_9->jtag_info.tap; fields[0].tap = arm7_9->jtag_info.tap;
fields[0].num_bits = 1; fields[0].num_bits = 1;
@ -121,7 +121,7 @@ int arm7tdmi_examine_debug_reason(target_t *target)
fields[0].in_check_mask = NULL; fields[0].in_check_mask = NULL;
fields[0].in_handler = NULL; fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL; fields[0].in_handler_priv = NULL;
fields[1].tap = arm7_9->jtag_info.tap; fields[1].tap = arm7_9->jtag_info.tap;
fields[1].num_bits = 32; fields[1].num_bits = 32;
fields[1].out_value = NULL; fields[1].out_value = NULL;
@ -131,30 +131,30 @@ int arm7tdmi_examine_debug_reason(target_t *target)
fields[1].in_check_mask = NULL; fields[1].in_check_mask = NULL;
fields[1].in_handler = NULL; fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL; fields[1].in_handler_priv = NULL;
if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK) if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
{ {
return retval; return retval;
} }
arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL); arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
jtag_add_dr_scan(2, fields, TAP_PD); jtag_add_dr_scan(2, fields, TAP_DRPAUSE);
if((retval = jtag_execute_queue()) != ERROR_OK) if((retval = jtag_execute_queue()) != ERROR_OK)
{ {
return retval; return retval;
} }
fields[0].in_value = NULL; fields[0].in_value = NULL;
fields[0].out_value = &breakpoint; fields[0].out_value = &breakpoint;
fields[1].in_value = NULL; fields[1].in_value = NULL;
fields[1].out_value = databus; fields[1].out_value = databus;
jtag_add_dr_scan(2, fields, TAP_PD); jtag_add_dr_scan(2, fields, TAP_DRPAUSE);
if (breakpoint & 1) if (breakpoint & 1)
target->debug_reason = DBG_REASON_WATCHPOINT; target->debug_reason = DBG_REASON_WATCHPOINT;
else else
target->debug_reason = DBG_REASON_BREAKPOINT; target->debug_reason = DBG_REASON_BREAKPOINT;
} }
return ERROR_OK; return ERROR_OK;
@ -164,13 +164,13 @@ static int arm7tdmi_num_bits[]={1, 32};
static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int breakpoint) static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int breakpoint)
{ {
u32 values[2]={breakpoint, flip_u32(out, 32)}; u32 values[2]={breakpoint, flip_u32(out, 32)};
jtag_add_dr_out(jtag_info->tap, jtag_add_dr_out(jtag_info->tap,
2, 2,
arm7tdmi_num_bits, arm7tdmi_num_bits,
values, values,
-1); -1);
jtag_add_runtest(0, -1); jtag_add_runtest(0, -1);
return ERROR_OK; return ERROR_OK;
@ -179,10 +179,10 @@ static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int
/* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */ /* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */
static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *deprecated, int breakpoint) static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *deprecated, int breakpoint)
{ {
jtag_add_end_state(TAP_PD); jtag_add_end_state(TAP_DRPAUSE);
arm_jtag_scann(jtag_info, 0x1); arm_jtag_scann(jtag_info, 0x1);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
return arm7tdmi_clock_out_inner(jtag_info, out, breakpoint); return arm7tdmi_clock_out_inner(jtag_info, out, breakpoint);
} }
@ -192,13 +192,13 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
int retval = ERROR_OK; int retval = ERROR_OK;
scan_field_t fields[2]; scan_field_t fields[2];
jtag_add_end_state(TAP_PD); jtag_add_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
{ {
return retval; return retval;
} }
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].tap = jtag_info->tap; fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1; fields[0].num_bits = 1;
fields[0].out_value = NULL; fields[0].out_value = NULL;
@ -208,7 +208,7 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
fields[0].in_check_mask = NULL; fields[0].in_check_mask = NULL;
fields[0].in_handler = NULL; fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL; fields[0].in_handler_priv = NULL;
fields[1].tap = jtag_info->tap; fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32; fields[1].num_bits = 32;
fields[1].out_value = NULL; fields[1].out_value = NULL;
@ -222,14 +222,14 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
jtag_add_dr_scan(2, fields, -1); jtag_add_dr_scan(2, fields, -1);
jtag_add_runtest(0, -1); jtag_add_runtest(0, -1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_ #ifdef _DEBUG_INSTRUCTION_EXECUTION_
{ {
if((retval = jtag_execute_queue()) != ERROR_OK) if((retval = jtag_execute_queue()) != ERROR_OK)
{ {
return retval; return retval;
} }
if (in) if (in)
{ {
LOG_DEBUG("in: 0x%8.8x", *in); LOG_DEBUG("in: 0x%8.8x", *in);
@ -247,19 +247,19 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
/* clock the target, and read the databus /* clock the target, and read the databus
* the *in pointer points to a buffer where elements of 'size' bytes * the *in pointer points to a buffer where elements of 'size' bytes
* are stored in big (be==1) or little (be==0) endianness * are stored in big (be==1) or little (be==0) endianness
*/ */
int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be) int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
{ {
int retval = ERROR_OK; int retval = ERROR_OK;
scan_field_t fields[2]; scan_field_t fields[2];
jtag_add_end_state(TAP_PD); jtag_add_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
{ {
return retval; return retval;
} }
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].tap = jtag_info->tap; fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1; fields[0].num_bits = 1;
fields[0].out_value = NULL; fields[0].out_value = NULL;
@ -269,7 +269,7 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
fields[0].in_check_mask = NULL; fields[0].in_check_mask = NULL;
fields[0].in_handler = NULL; fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL; fields[0].in_handler_priv = NULL;
fields[1].tap = jtag_info->tap; fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32; fields[1].num_bits = 32;
fields[1].out_value = NULL; fields[1].out_value = NULL;
@ -294,14 +294,14 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
jtag_add_dr_scan(2, fields, -1); jtag_add_dr_scan(2, fields, -1);
jtag_add_runtest(0, -1); jtag_add_runtest(0, -1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_ #ifdef _DEBUG_INSTRUCTION_EXECUTION_
{ {
if((retval = jtag_execute_queue()) != ERROR_OK) if((retval = jtag_execute_queue()) != ERROR_OK)
{ {
return retval; return retval;
} }
if (in) if (in)
{ {
LOG_DEBUG("in: 0x%8.8x", *(u32*)in); LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
@ -322,10 +322,10 @@ void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* save r0 before using it and put system in ARM state /* save r0 before using it and put system in ARM state
* to allow common handling of ARM and THUMB debugging */ * to allow common handling of ARM and THUMB debugging */
/* fetch STR r0, [r0] */ /* fetch STR r0, [r0] */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
@ -333,7 +333,7 @@ void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
/* nothing fetched, STR r0, [r0] in Execute (2) */ /* nothing fetched, STR r0, [r0] in Execute (2) */
arm7tdmi_clock_data_in(jtag_info, r0); arm7tdmi_clock_data_in(jtag_info, r0);
/* MOV r0, r15 fetched, STR in Decode */ /* MOV r0, r15 fetched, STR in Decode */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
@ -349,22 +349,22 @@ void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
arm7tdmi_clock_out(jtag_info, 0x0, NULL, 0); arm7tdmi_clock_out(jtag_info, 0x0, NULL, 0);
/* nothing fetched, data from previous cycle is written to register */ /* nothing fetched, data from previous cycle is written to register */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
/* fetch BX */ /* fetch BX */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), NULL, 0);
/* NOP fetched, BX in Decode, MOV in Execute */ /* NOP fetched, BX in Decode, MOV in Execute */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
/* NOP fetched, BX in Execute (1) */ /* NOP fetched, BX in Execute (1) */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
jtag_execute_queue(); jtag_execute_queue();
/* fix program counter: /* fix program counter:
* MOV r0, r15 was the 4th instruction (+6) * MOV r0, r15 was the 4th instruction (+6)
* reading PC in Thumb state gives address of instruction + 4 * reading PC in Thumb state gives address of instruction + 4
*/ */
*pc -= 0xa; *pc -= 0xa;
} }
void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16]) void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
@ -374,7 +374,7 @@ void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* STMIA r0-15, [r0] at debug speed /* STMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK * register values will start to appear on 4th DCLK
*/ */
@ -405,7 +405,7 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf
u32 *buf_u32 = buffer; u32 *buf_u32 = buffer;
u16 *buf_u16 = buffer; u16 *buf_u16 = buffer;
u8 *buf_u8 = buffer; u8 *buf_u8 = buffer;
/* STMIA r0-15, [r0] at debug speed /* STMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK * register values will start to appear on 4th DCLK
*/ */
@ -435,7 +435,7 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf
} }
} }
} }
} }
void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr) void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
@ -444,10 +444,10 @@ void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* MRS r0, cpsr */ /* MRS r0, cpsr */
arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), NULL, 0);
/* STR r0, [r15] */ /* STR r0, [r15] */
arm7tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), NULL, 0);
/* fetch NOP, STR in DECODE stage */ /* fetch NOP, STR in DECODE stage */
@ -465,7 +465,7 @@ void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr); LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
/* MSR1 fetched */ /* MSR1 fetched */
@ -496,9 +496,9 @@ void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr); LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
/* MSR fetched */ /* MSR fetched */
arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), NULL, 0);
/* NOP fetched, MSR in DECODE */ /* NOP fetched, MSR in DECODE */
@ -507,7 +507,7 @@ void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
/* nothing fetched, MSR in EXECUTE (2) */ /* nothing fetched, MSR in EXECUTE (2) */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
} }
void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16]) void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
@ -517,7 +517,7 @@ void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed /* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK * register values will start to appear on 4th DCLK
*/ */
@ -535,7 +535,7 @@ void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0); arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0);
} }
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0); arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
} }
void arm7tdmi_load_word_regs(target_t *target, u32 mask) void arm7tdmi_load_word_regs(target_t *target, u32 mask)
@ -558,7 +558,7 @@ void arm7tdmi_load_hword_reg(target_t *target, int num)
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load half-word into the pipeline */ /* put system-speed load half-word into the pipeline */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1); arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
@ -591,7 +591,7 @@ void arm7tdmi_store_word_regs(target_t *target, u32 mask)
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1); arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), NULL, 0);
} }
void arm7tdmi_store_hword_reg(target_t *target, int num) void arm7tdmi_store_hword_reg(target_t *target, int num)
@ -628,7 +628,7 @@ void arm7tdmi_write_pc(target_t *target, u32 pc)
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed /* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK * register values will start to appear on 4th DCLK
*/ */
@ -655,7 +655,7 @@ void arm7tdmi_branch_resume(target_t *target)
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1); arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0); arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0);
@ -664,7 +664,7 @@ void arm7tdmi_branch_resume(target_t *target)
void arm7tdmi_branch_resume_thumb(target_t *target) void arm7tdmi_branch_resume_thumb(target_t *target)
{ {
LOG_DEBUG("-"); LOG_DEBUG("-");
/* get pointers to arch-specific information */ /* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@ -687,15 +687,15 @@ void arm7tdmi_branch_resume_thumb(target_t *target)
/* Branch and eXchange */ /* Branch and eXchange */
arm7tdmi_clock_out(jtag_info, ARMV4_5_BX(0), NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_BX(0), NULL, 0);
embeddedice_read_reg(dbg_stat); embeddedice_read_reg(dbg_stat);
/* fetch NOP, BX in DECODE stage */ /* fetch NOP, BX in DECODE stage */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
/* target is now in Thumb state */ /* target is now in Thumb state */
embeddedice_read_reg(dbg_stat); embeddedice_read_reg(dbg_stat);
/* fetch NOP, BX in EXECUTE stage (1st cycle) */ /* fetch NOP, BX in EXECUTE stage (1st cycle) */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
@ -712,17 +712,17 @@ void arm7tdmi_branch_resume_thumb(target_t *target)
arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0); arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
/* nothing fetched, LDR in EXECUTE stage (3rd cycle) */ /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
embeddedice_read_reg(dbg_stat); embeddedice_read_reg(dbg_stat);
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 1); arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 1);
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0);
} }
void arm7tdmi_build_reg_cache(target_t *target) void arm7tdmi_build_reg_cache(target_t *target)
{ {
reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
@ -745,10 +745,10 @@ int arm7tdmi_examine(struct target_s *target)
reg_cache_t *t=embeddedice_build_reg_cache(target, arm7_9); reg_cache_t *t=embeddedice_build_reg_cache(target, arm7_9);
if (t==NULL) if (t==NULL)
return ERROR_FAIL; return ERROR_FAIL;
(*cache_p) = t; (*cache_p) = t;
arm7_9->eice_cache = (*cache_p); arm7_9->eice_cache = (*cache_p);
if (arm7_9->etm_ctx) if (arm7_9->etm_ctx)
{ {
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
@ -771,16 +771,16 @@ int arm7tdmi_examine(struct target_s *target)
int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target) int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
{ {
arm7tdmi_build_reg_cache(target); arm7tdmi_build_reg_cache(target);
return ERROR_OK; return ERROR_OK;
} }
int arm7tdmi_quit(void) int arm7tdmi_quit(void)
{ {
return ERROR_OK; return ERROR_OK;
} }
@ -788,56 +788,56 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_
{ {
armv4_5_common_t *armv4_5; armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9; arm7_9_common_t *arm7_9;
arm7_9 = &arm7tdmi->arm7_9_common; arm7_9 = &arm7tdmi->arm7_9_common;
armv4_5 = &arm7_9->armv4_5_common; armv4_5 = &arm7_9->armv4_5_common;
/* prepare JTAG information for the new target */ /* prepare JTAG information for the new target */
arm7_9->jtag_info.tap = tap; arm7_9->jtag_info.tap = tap;
arm7_9->jtag_info.scann_size = 4; arm7_9->jtag_info.scann_size = 4;
/* register arch-specific functions */ /* register arch-specific functions */
arm7_9->examine_debug_reason = arm7tdmi_examine_debug_reason; arm7_9->examine_debug_reason = arm7tdmi_examine_debug_reason;
arm7_9->change_to_arm = arm7tdmi_change_to_arm; arm7_9->change_to_arm = arm7tdmi_change_to_arm;
arm7_9->read_core_regs = arm7tdmi_read_core_regs; arm7_9->read_core_regs = arm7tdmi_read_core_regs;
arm7_9->read_core_regs_target_buffer = arm7tdmi_read_core_regs_target_buffer; arm7_9->read_core_regs_target_buffer = arm7tdmi_read_core_regs_target_buffer;
arm7_9->read_xpsr = arm7tdmi_read_xpsr; arm7_9->read_xpsr = arm7tdmi_read_xpsr;
arm7_9->write_xpsr = arm7tdmi_write_xpsr; arm7_9->write_xpsr = arm7tdmi_write_xpsr;
arm7_9->write_xpsr_im8 = arm7tdmi_write_xpsr_im8; arm7_9->write_xpsr_im8 = arm7tdmi_write_xpsr_im8;
arm7_9->write_core_regs = arm7tdmi_write_core_regs; arm7_9->write_core_regs = arm7tdmi_write_core_regs;
arm7_9->load_word_regs = arm7tdmi_load_word_regs; arm7_9->load_word_regs = arm7tdmi_load_word_regs;
arm7_9->load_hword_reg = arm7tdmi_load_hword_reg; arm7_9->load_hword_reg = arm7tdmi_load_hword_reg;
arm7_9->load_byte_reg = arm7tdmi_load_byte_reg; arm7_9->load_byte_reg = arm7tdmi_load_byte_reg;
arm7_9->store_word_regs = arm7tdmi_store_word_regs; arm7_9->store_word_regs = arm7tdmi_store_word_regs;
arm7_9->store_hword_reg = arm7tdmi_store_hword_reg; arm7_9->store_hword_reg = arm7tdmi_store_hword_reg;
arm7_9->store_byte_reg = arm7tdmi_store_byte_reg; arm7_9->store_byte_reg = arm7tdmi_store_byte_reg;
arm7_9->write_pc = arm7tdmi_write_pc; arm7_9->write_pc = arm7tdmi_write_pc;
arm7_9->branch_resume = arm7tdmi_branch_resume; arm7_9->branch_resume = arm7tdmi_branch_resume;
arm7_9->branch_resume_thumb = arm7tdmi_branch_resume_thumb; arm7_9->branch_resume_thumb = arm7tdmi_branch_resume_thumb;
arm7_9->enable_single_step = arm7_9_enable_eice_step; arm7_9->enable_single_step = arm7_9_enable_eice_step;
arm7_9->disable_single_step = arm7_9_disable_eice_step; arm7_9->disable_single_step = arm7_9_disable_eice_step;
arm7_9->pre_debug_entry = NULL; arm7_9->pre_debug_entry = NULL;
arm7_9->post_debug_entry = NULL; arm7_9->post_debug_entry = NULL;
arm7_9->pre_restore_context = NULL; arm7_9->pre_restore_context = NULL;
arm7_9->post_restore_context = NULL; arm7_9->post_restore_context = NULL;
/* initialize arch-specific breakpoint handling */ /* initialize arch-specific breakpoint handling */
arm7_9->arm_bkpt = 0xdeeedeee; arm7_9->arm_bkpt = 0xdeeedeee;
arm7_9->thumb_bkpt = 0xdeee; arm7_9->thumb_bkpt = 0xdeee;
arm7_9->dbgreq_adjust_pc = 2; arm7_9->dbgreq_adjust_pc = 2;
arm7_9->arch_info = arm7tdmi; arm7_9->arch_info = arm7tdmi;
arm7tdmi->arch_info = NULL; arm7tdmi->arch_info = NULL;
arm7tdmi->common_magic = ARM7TDMI_COMMON_MAGIC; arm7tdmi->common_magic = ARM7TDMI_COMMON_MAGIC;
if (variant) if (variant)
{ {
arm7tdmi->variant = strdup(variant); arm7tdmi->variant = strdup(variant);
@ -846,7 +846,7 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_
{ {
arm7tdmi->variant = strdup(""); arm7tdmi->variant = strdup("");
} }
arm7_9_init_arch_info(target, arm7_9); arm7_9_init_arch_info(target, arm7_9);
return ERROR_OK; return ERROR_OK;
@ -857,11 +857,11 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_
int arm7tdmi_target_create( struct target_s *target, Jim_Interp *interp ) int arm7tdmi_target_create( struct target_s *target, Jim_Interp *interp )
{ {
arm7tdmi_common_t *arm7tdmi; arm7tdmi_common_t *arm7tdmi;
arm7tdmi = calloc(1,sizeof(arm7tdmi_common_t)); arm7tdmi = calloc(1,sizeof(arm7tdmi_common_t));
arm7tdmi_init_arch_info(target, arm7tdmi, target->tap, target->variant); arm7tdmi_init_arch_info(target, arm7tdmi, target->tap, target->variant);
return ERROR_OK; return ERROR_OK;
} }
@ -869,9 +869,9 @@ int arm7tdmi_target_create( struct target_s *target, Jim_Interp *interp )
int arm7tdmi_register_commands(struct command_context_s *cmd_ctx) int arm7tdmi_register_commands(struct command_context_s *cmd_ctx)
{ {
int retval; int retval;
retval = arm7_9_register_commands(cmd_ctx); retval = arm7_9_register_commands(cmd_ctx);
return retval; return retval;
} }

402
src/target/arm920t.c
View File

File diff suppressed because it is too large Load Diff

6
src/target/arm926ejs.c
View File

@ -132,7 +132,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
buf_set_u32(address_buf, 0, 14, address); buf_set_u32(address_buf, 0, 14, address);
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
{ {
return retval; return retval;
@ -222,7 +222,7 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
buf_set_u32(address_buf, 0, 14, address); buf_set_u32(address_buf, 0, 14, address);
buf_set_u32(value_buf, 0, 32, value); buf_set_u32(value_buf, 0, 32, value);
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
{ {
return retval; return retval;
@ -366,7 +366,7 @@ int arm926ejs_examine_debug_reason(target_t *target)
default: default:
LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason); LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
target->debug_reason = DBG_REASON_DBGRQ; target->debug_reason = DBG_REASON_DBGRQ;
/* if we fail here, we won't talk to the target and it will /* if we fail here, we won't talk to the target and it will
* be reported to be in the halted state */ * be reported to be in the halted state */
retval = ERROR_TARGET_FAILURE; retval = ERROR_TARGET_FAILURE;
break; break;

52
src/target/arm966e.c
View File

@ -74,9 +74,9 @@ target_type_t arm966e_target =
.bulk_write_memory = arm7_9_bulk_write_memory, .bulk_write_memory = arm7_9_bulk_write_memory,
.checksum_memory = arm7_9_checksum_memory, .checksum_memory = arm7_9_checksum_memory,
.blank_check_memory = arm7_9_blank_check_memory, .blank_check_memory = arm7_9_blank_check_memory,
.run_algorithm = armv4_5_run_algorithm, .run_algorithm = armv4_5_run_algorithm,
.add_breakpoint = arm7_9_add_breakpoint, .add_breakpoint = arm7_9_add_breakpoint,
.remove_breakpoint = arm7_9_remove_breakpoint, .remove_breakpoint = arm7_9_remove_breakpoint,
.add_watchpoint = arm7_9_add_watchpoint, .add_watchpoint = arm7_9_add_watchpoint,
@ -92,13 +92,13 @@ target_type_t arm966e_target =
int arm966e_init_target(struct command_context_s *cmd_ctx, struct target_s *target) int arm966e_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
{ {
arm9tdmi_init_target(cmd_ctx, target); arm9tdmi_init_target(cmd_ctx, target);
return ERROR_OK; return ERROR_OK;
} }
int arm966e_quit(void) int arm966e_quit(void)
{ {
return ERROR_OK; return ERROR_OK;
} }
@ -106,25 +106,25 @@ int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, jtag_tap
{ {
arm9tdmi_common_t *arm9tdmi = &arm966e->arm9tdmi_common; arm9tdmi_common_t *arm9tdmi = &arm966e->arm9tdmi_common;
arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common; arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant); arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant);
arm9tdmi->arch_info = arm966e; arm9tdmi->arch_info = arm966e;
arm966e->common_magic = ARM966E_COMMON_MAGIC; arm966e->common_magic = ARM966E_COMMON_MAGIC;
/* The ARM966E-S implements the ARMv5TE architecture which /* The ARM966E-S implements the ARMv5TE architecture which
* has the BKPT instruction, so we don't have to use a watchpoint comparator * has the BKPT instruction, so we don't have to use a watchpoint comparator
*/ */
arm7_9->arm_bkpt = ARMV5_BKPT(0x0); arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff; arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
return ERROR_OK; return ERROR_OK;
} }
int arm966e_target_create( struct target_s *target, Jim_Interp *interp ) int arm966e_target_create( struct target_s *target, Jim_Interp *interp )
{ {
arm966e_common_t *arm966e = calloc(1,sizeof(arm966e_common_t)); arm966e_common_t *arm966e = calloc(1,sizeof(arm966e_common_t));
arm966e_init_arch_info(target, arm966e, target->tap, target->variant); arm966e_init_arch_info(target, arm966e, target->tap, target->variant);
return ERROR_OK; return ERROR_OK;
@ -136,35 +136,35 @@ int arm966e_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, ar
arm7_9_common_t *arm7_9; arm7_9_common_t *arm7_9;
arm9tdmi_common_t *arm9tdmi; arm9tdmi_common_t *arm9tdmi;
arm966e_common_t *arm966e; arm966e_common_t *arm966e;
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{ {
return -1; return -1;
} }
arm7_9 = armv4_5->arch_info; arm7_9 = armv4_5->arch_info;
if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC) if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
{ {
return -1; return -1;
} }
arm9tdmi = arm7_9->arch_info; arm9tdmi = arm7_9->arch_info;
if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC) if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
{ {
return -1; return -1;
} }
arm966e = arm9tdmi->arch_info; arm966e = arm9tdmi->arch_info;
if (arm966e->common_magic != ARM966E_COMMON_MAGIC) if (arm966e->common_magic != ARM966E_COMMON_MAGIC)
{ {
return -1; return -1;
} }
*armv4_5_p = armv4_5; *armv4_5_p = armv4_5;
*arm7_9_p = arm7_9; *arm7_9_p = arm7_9;
*arm9tdmi_p = arm9tdmi; *arm9tdmi_p = arm9tdmi;
*arm966e_p = arm966e; *arm966e_p = arm966e;
return ERROR_OK; return ERROR_OK;
} }
@ -177,8 +177,8 @@ int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value)
scan_field_t fields[3]; scan_field_t fields[3];
u8 reg_addr_buf = reg_addr & 0x3f; u8 reg_addr_buf = reg_addr & 0x3f;
u8 nr_w_buf = 0; u8 nr_w_buf = 0;
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
{ {
return retval; return retval;
@ -214,7 +214,7 @@ int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value)
fields[2].in_check_mask = NULL; fields[2].in_check_mask = NULL;
fields[2].in_handler = NULL; fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL; fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1); jtag_add_dr_scan(3, fields, -1);
fields[0].in_handler_priv = value; fields[0].in_handler_priv = value;
@ -243,10 +243,10 @@ int arm966e_write_cp15(target_t *target, int reg_addr, u32 value)
u8 reg_addr_buf = reg_addr & 0x3f; u8 reg_addr_buf = reg_addr & 0x3f;
u8 nr_w_buf = 1; u8 nr_w_buf = 1;
u8 value_buf[4]; u8 value_buf[4];
buf_set_u32(value_buf, 0, 32, value); buf_set_u32(value_buf, 0, 32, value);
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
{ {
return retval; return retval;
@ -282,7 +282,7 @@ int arm966e_write_cp15(target_t *target, int reg_addr, u32 value)
fields[2].in_check_mask = NULL; fields[2].in_check_mask = NULL;
fields[2].in_handler = NULL; fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL; fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1); jtag_add_dr_scan(3, fields, -1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_ #ifdef _DEBUG_INSTRUCTION_EXECUTION_
@ -307,9 +307,9 @@ int arm966e_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
command_print(cmd_ctx, "current target isn't an ARM966e target"); command_print(cmd_ctx, "current target isn't an ARM966e target");
return ERROR_OK; return ERROR_OK;
} }
jtag_info = &arm7_9->jtag_info; jtag_info = &arm7_9->jtag_info;
if (target->state != TARGET_HALTED) if (target->state != TARGET_HALTED)
{ {
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
@ -333,7 +333,7 @@ int arm966e_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
{ {
return retval; return retval;
} }
command_print(cmd_ctx, "%i: %8.8x", address, value); command_print(cmd_ctx, "%i: %8.8x", address, value);
} }
else if (argc == 2) else if (argc == 2)
@ -355,10 +355,10 @@ int arm966e_register_commands(struct command_context_s *cmd_ctx)
{ {
int retval; int retval;
command_t *arm966e_cmd; command_t *arm966e_cmd;
retval = arm9tdmi_register_commands(cmd_ctx); retval = arm9tdmi_register_commands(cmd_ctx);
arm966e_cmd = register_command(cmd_ctx, NULL, "arm966e", NULL, COMMAND_ANY, "arm966e specific commands"); arm966e_cmd = register_command(cmd_ctx, NULL, "arm966e", NULL, COMMAND_ANY, "arm966e specific commands");
register_command(cmd_ctx, arm966e_cmd, "cp15", arm966e_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]"); register_command(cmd_ctx, arm966e_cmd, "cp15", arm966e_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
return retval; return retval;
} }

212
src/target/arm9tdmi.c
View File

@ -56,7 +56,7 @@ int arm9tdmi_target_create( struct target_s *target, Jim_Interp *interp );
int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target); int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm9tdmi_quit(void); int arm9tdmi_quit(void);
target_type_t arm9tdmi_target = target_type_t arm9tdmi_target =
{ {
.name = "arm9tdmi", .name = "arm9tdmi",
@ -81,9 +81,9 @@ target_type_t arm9tdmi_target =
.bulk_write_memory = arm7_9_bulk_write_memory, .bulk_write_memory = arm7_9_bulk_write_memory,
.checksum_memory = arm7_9_checksum_memory, .checksum_memory = arm7_9_checksum_memory,
.blank_check_memory = arm7_9_blank_check_memory, .blank_check_memory = arm7_9_blank_check_memory,
.run_algorithm = armv4_5_run_algorithm, .run_algorithm = armv4_5_run_algorithm,
.add_breakpoint = arm7_9_add_breakpoint, .add_breakpoint = arm7_9_add_breakpoint,
.remove_breakpoint = arm7_9_remove_breakpoint, .remove_breakpoint = arm7_9_remove_breakpoint,
.add_watchpoint = arm7_9_add_watchpoint, .add_watchpoint = arm7_9_add_watchpoint,
@ -115,7 +115,7 @@ int arm9tdmi_examine_debug_reason(target_t *target)
/* get pointers to arch-specific information */ /* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
/* only check the debug reason if we don't know it already */ /* only check the debug reason if we don't know it already */
if ((target->debug_reason != DBG_REASON_DBGRQ) if ((target->debug_reason != DBG_REASON_DBGRQ)
&& (target->debug_reason != DBG_REASON_SINGLESTEP)) && (target->debug_reason != DBG_REASON_SINGLESTEP))
@ -125,7 +125,7 @@ int arm9tdmi_examine_debug_reason(target_t *target)
u8 instructionbus[4]; u8 instructionbus[4];
u8 debug_reason; u8 debug_reason;
jtag_add_end_state(TAP_PD); jtag_add_end_state(TAP_DRPAUSE);
fields[0].tap = arm7_9->jtag_info.tap; fields[0].tap = arm7_9->jtag_info.tap;
fields[0].num_bits = 32; fields[0].num_bits = 32;
@ -136,7 +136,7 @@ int arm9tdmi_examine_debug_reason(target_t *target)
fields[0].in_check_mask = NULL; fields[0].in_check_mask = NULL;
fields[0].in_handler = NULL; fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL; fields[0].in_handler_priv = NULL;
fields[1].tap = arm7_9->jtag_info.tap; fields[1].tap = arm7_9->jtag_info.tap;
fields[1].num_bits = 3; fields[1].num_bits = 3;
fields[1].out_value = NULL; fields[1].out_value = NULL;
@ -146,7 +146,7 @@ int arm9tdmi_examine_debug_reason(target_t *target)
fields[1].in_check_mask = NULL; fields[1].in_check_mask = NULL;
fields[1].in_handler = NULL; fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL; fields[1].in_handler_priv = NULL;
fields[2].tap = arm7_9->jtag_info.tap; fields[2].tap = arm7_9->jtag_info.tap;
fields[2].num_bits = 32; fields[2].num_bits = 32;
fields[2].out_value = NULL; fields[2].out_value = NULL;
@ -156,27 +156,27 @@ int arm9tdmi_examine_debug_reason(target_t *target)
fields[2].in_check_mask = NULL; fields[2].in_check_mask = NULL;
fields[2].in_handler = NULL; fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL; fields[2].in_handler_priv = NULL;
if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK) if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
{ {
return retval; return retval;
} }
arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL); arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
jtag_add_dr_scan(3, fields, TAP_PD); jtag_add_dr_scan(3, fields, TAP_DRPAUSE);
if((retval = jtag_execute_queue()) != ERROR_OK) if((retval = jtag_execute_queue()) != ERROR_OK)
{ {
return retval; return retval;
} }
fields[0].in_value = NULL; fields[0].in_value = NULL;
fields[0].out_value = databus; fields[0].out_value = databus;
fields[1].in_value = NULL; fields[1].in_value = NULL;
fields[1].out_value = &debug_reason; fields[1].out_value = &debug_reason;
fields[2].in_value = NULL; fields[2].in_value = NULL;
fields[2].out_value = instructionbus; fields[2].out_value = instructionbus;
jtag_add_dr_scan(3, fields, TAP_PD); jtag_add_dr_scan(3, fields, TAP_DRPAUSE);
if (debug_reason & 0x4) if (debug_reason & 0x4)
if (debug_reason & 0x2) if (debug_reason & 0x2)
@ -198,23 +198,23 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
u8 out_buf[4]; u8 out_buf[4];
u8 instr_buf[4]; u8 instr_buf[4];
u8 sysspeed_buf = 0x0; u8 sysspeed_buf = 0x0;
/* prepare buffer */ /* prepare buffer */
buf_set_u32(out_buf, 0, 32, out); buf_set_u32(out_buf, 0, 32, out);
buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32)); buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
if (sysspeed) if (sysspeed)
buf_set_u32(&sysspeed_buf, 2, 1, 1); buf_set_u32(&sysspeed_buf, 2, 1, 1);
jtag_add_end_state(TAP_PD); jtag_add_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
{ {
return retval; return retval;
} }
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].tap = jtag_info->tap; fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32; fields[0].num_bits = 32;
fields[0].out_value = out_buf; fields[0].out_value = out_buf;
@ -232,7 +232,7 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
} }
fields[0].in_check_value = NULL; fields[0].in_check_value = NULL;
fields[0].in_check_mask = NULL; fields[0].in_check_mask = NULL;
fields[1].tap = jtag_info->tap; fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3; fields[1].num_bits = 3;
fields[1].out_value = &sysspeed_buf; fields[1].out_value = &sysspeed_buf;
@ -242,7 +242,7 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
fields[1].in_check_mask = NULL; fields[1].in_check_mask = NULL;
fields[1].in_handler = NULL; fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL; fields[1].in_handler_priv = NULL;
fields[2].tap = jtag_info->tap; fields[2].tap = jtag_info->tap;
fields[2].num_bits = 32; fields[2].num_bits = 32;
fields[2].out_value = instr_buf; fields[2].out_value = instr_buf;
@ -256,14 +256,14 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
jtag_add_dr_scan(3, fields, -1); jtag_add_dr_scan(3, fields, -1);
jtag_add_runtest(0, -1); jtag_add_runtest(0, -1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_ #ifdef _DEBUG_INSTRUCTION_EXECUTION_
{ {
if((retval = jtag_execute_queue()) != ERROR_OK) if((retval = jtag_execute_queue()) != ERROR_OK)
{ {
return retval; return retval;
} }
if (in) if (in)
{ {
LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in); LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
@ -282,14 +282,14 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
int retval = ERROR_OK;; int retval = ERROR_OK;;
scan_field_t fields[3]; scan_field_t fields[3];
jtag_add_end_state(TAP_PD); jtag_add_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
{ {
return retval; return retval;
} }
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].tap = jtag_info->tap; fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32; fields[0].num_bits = 32;
fields[0].out_value = NULL; fields[0].out_value = NULL;
@ -299,7 +299,7 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
fields[0].in_handler_priv = in; fields[0].in_handler_priv = in;
fields[0].in_check_value = NULL; fields[0].in_check_value = NULL;
fields[0].in_check_mask = NULL; fields[0].in_check_mask = NULL;
fields[1].tap = jtag_info->tap; fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3; fields[1].num_bits = 3;
fields[1].out_value = NULL; fields[1].out_value = NULL;
@ -319,18 +319,18 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
fields[2].in_check_mask = NULL; fields[2].in_check_mask = NULL;
fields[2].in_handler = NULL; fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL; fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1); jtag_add_dr_scan(3, fields, -1);
jtag_add_runtest(0, -1); jtag_add_runtest(0, -1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_ #ifdef _DEBUG_INSTRUCTION_EXECUTION_
{ {
if((retval = jtag_execute_queue()) != ERROR_OK) if((retval = jtag_execute_queue()) != ERROR_OK)
{ {
return retval; return retval;
} }
if (in) if (in)
{ {
LOG_DEBUG("in: 0x%8.8x", *in); LOG_DEBUG("in: 0x%8.8x", *in);
@ -353,15 +353,15 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
{ {
int retval = ERROR_OK; int retval = ERROR_OK;
scan_field_t fields[3]; scan_field_t fields[3];
jtag_add_end_state(TAP_PD); jtag_add_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
{ {
return retval; return retval;
} }
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].tap = jtag_info->tap; fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32; fields[0].num_bits = 32;
fields[0].out_value = NULL; fields[0].out_value = NULL;
@ -382,7 +382,7 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
fields[0].in_handler_priv = in; fields[0].in_handler_priv = in;
fields[0].in_check_value = NULL; fields[0].in_check_value = NULL;
fields[0].in_check_mask = NULL; fields[0].in_check_mask = NULL;
fields[1].tap = jtag_info->tap; fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3; fields[1].num_bits = 3;
fields[1].out_value = NULL; fields[1].out_value = NULL;
@ -402,18 +402,18 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
fields[2].in_check_mask = NULL; fields[2].in_check_mask = NULL;
fields[2].in_handler = NULL; fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL; fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1); jtag_add_dr_scan(3, fields, -1);
jtag_add_runtest(0, -1); jtag_add_runtest(0, -1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_ #ifdef _DEBUG_INSTRUCTION_EXECUTION_
{ {
if((retval = jtag_execute_queue()) != ERROR_OK) if((retval = jtag_execute_queue()) != ERROR_OK)
{ {
return retval; return retval;
} }
if (in) if (in)
{ {
LOG_DEBUG("in: 0x%8.8x", *(u32*)in); LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
@ -435,10 +435,10 @@ void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* save r0 before using it and put system in ARM state /* save r0 before using it and put system in ARM state
* to allow common handling of ARM and THUMB debugging */ * to allow common handling of ARM and THUMB debugging */
/* fetch STR r0, [r0] */ /* fetch STR r0, [r0] */
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
@ -446,7 +446,7 @@ void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
/* STR r0, [r0] in Memory */ /* STR r0, [r0] in Memory */
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
/* MOV r0, r15 fetched, STR in Decode */ /* MOV r0, r15 fetched, STR in Decode */
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
@ -470,12 +470,12 @@ void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
/* NOP fetched, BX in Execute (1) */ /* NOP fetched, BX in Execute (1) */
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
if((retval = jtag_execute_queue()) != ERROR_OK) if((retval = jtag_execute_queue()) != ERROR_OK)
{ {
return; return;
} }
/* fix program counter: /* fix program counter:
* MOV r0, r15 was the 5th instruction (+8) * MOV r0, r15 was the 5th instruction (+8)
* reading PC in Thumb state gives address of instruction + 4 * reading PC in Thumb state gives address of instruction + 4
@ -490,7 +490,7 @@ void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* STMIA r0-15, [r0] at debug speed /* STMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK * register values will start to appear on 4th DCLK
*/ */
@ -521,7 +521,7 @@ void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf
u32 *buf_u32 = buffer; u32 *buf_u32 = buffer;
u16 *buf_u16 = buffer; u16 *buf_u16 = buffer;
u8 *buf_u8 = buffer; u8 *buf_u8 = buffer;
/* STMIA r0-15, [r0] at debug speed /* STMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK * register values will start to appear on 4th DCLK
*/ */
@ -558,7 +558,7 @@ void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* MRS r0, cpsr */ /* MRS r0, cpsr */
arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@ -583,7 +583,7 @@ void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr); LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
/* MSR1 fetched */ /* MSR1 fetched */
@ -619,16 +619,16 @@ void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr); LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
/* MSR fetched */ /* MSR fetched */
arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
/* NOP fetched, MSR in DECODE */ /* NOP fetched, MSR in DECODE */
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
/* NOP fetched, MSR in EXECUTE (1) */ /* NOP fetched, MSR in EXECUTE (1) */
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
/* rot == 4 writes flags, which takes only one cycle */ /* rot == 4 writes flags, which takes only one cycle */
if (rot != 4) if (rot != 4)
{ {
@ -646,7 +646,7 @@ void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed /* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK * register values will start to appear on 4th DCLK
*/ */
@ -664,7 +664,7 @@ void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
} }
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
} }
void arm9tdmi_load_word_regs(target_t *target, u32 mask) void arm9tdmi_load_word_regs(target_t *target, u32 mask)
@ -686,7 +686,7 @@ void arm9tdmi_load_hword_reg(target_t *target, int num)
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load half-word into the pipeline */ /* put system-speed load half-word into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
@ -750,7 +750,7 @@ void arm9tdmi_write_pc(target_t *target, u32 pc)
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed /* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK * register values will start to appear on 4th DCLK
*/ */
@ -777,7 +777,7 @@ void arm9tdmi_branch_resume(target_t *target)
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
@ -786,7 +786,7 @@ void arm9tdmi_branch_resume(target_t *target)
void arm9tdmi_branch_resume_thumb(target_t *target) void arm9tdmi_branch_resume_thumb(target_t *target)
{ {
LOG_DEBUG("-"); LOG_DEBUG("-");
/* get pointers to arch-specific information */ /* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@ -809,14 +809,14 @@ void arm9tdmi_branch_resume_thumb(target_t *target)
/* Branch and eXchange */ /* Branch and eXchange */
arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
embeddedice_read_reg(dbg_stat); embeddedice_read_reg(dbg_stat);
/* fetch NOP, BX in DECODE stage */ /* fetch NOP, BX in DECODE stage */
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
embeddedice_read_reg(dbg_stat); embeddedice_read_reg(dbg_stat);
/* fetch NOP, BX in EXECUTE stage (1st cycle) */ /* fetch NOP, BX in EXECUTE stage (1st cycle) */
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@ -833,12 +833,12 @@ void arm9tdmi_branch_resume_thumb(target_t *target)
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
/* nothing fetched, LDR in EXECUTE stage (3rd cycle) */ /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
embeddedice_read_reg(dbg_stat); embeddedice_read_reg(dbg_stat);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
@ -849,7 +849,7 @@ void arm9tdmi_enable_single_step(target_t *target, u32 next_pc)
/* get pointers to arch-specific information */ /* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
if (arm7_9->has_single_step) if (arm7_9->has_single_step)
{ {
buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1); buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
@ -866,7 +866,7 @@ void arm9tdmi_disable_single_step(target_t *target)
/* get pointers to arch-specific information */ /* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
if (arm7_9->has_single_step) if (arm7_9->has_single_step)
{ {
buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0); buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
@ -905,7 +905,7 @@ int arm9tdmi_examine(struct target_s *target)
return ERROR_FAIL; return ERROR_FAIL;
(*cache_p) = t; (*cache_p) = t;
arm7_9->eice_cache = (*cache_p); arm7_9->eice_cache = (*cache_p);
if (arm7_9->etm_ctx) if (arm7_9->etm_ctx)
{ {
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
@ -928,16 +928,16 @@ int arm9tdmi_examine(struct target_s *target)
int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target) int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
{ {
arm9tdmi_build_reg_cache(target); arm9tdmi_build_reg_cache(target);
return ERROR_OK; return ERROR_OK;
} }
int arm9tdmi_quit(void) int arm9tdmi_quit(void)
{ {
return ERROR_OK; return ERROR_OK;
} }
@ -945,53 +945,53 @@ int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_
{ {
armv4_5_common_t *armv4_5; armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9; arm7_9_common_t *arm7_9;
arm7_9 = &arm9tdmi->arm7_9_common; arm7_9 = &arm9tdmi->arm7_9_common;
armv4_5 = &arm7_9->armv4_5_common; armv4_5 = &arm7_9->armv4_5_common;
/* prepare JTAG information for the new target */ /* prepare JTAG information for the new target */
arm7_9->jtag_info.tap = tap; arm7_9->jtag_info.tap = tap;
arm7_9->jtag_info.scann_size = 5; arm7_9->jtag_info.scann_size = 5;
/* register arch-specific functions */ /* register arch-specific functions */
arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason; arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
arm7_9->change_to_arm = arm9tdmi_change_to_arm; arm7_9->change_to_arm = arm9tdmi_change_to_arm;
arm7_9->read_core_regs = arm9tdmi_read_core_regs; arm7_9->read_core_regs = arm9tdmi_read_core_regs;
arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer; arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
arm7_9->read_xpsr = arm9tdmi_read_xpsr; arm7_9->read_xpsr = arm9tdmi_read_xpsr;
arm7_9->write_xpsr = arm9tdmi_write_xpsr; arm7_9->write_xpsr = arm9tdmi_write_xpsr;
arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8; arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
arm7_9->write_core_regs = arm9tdmi_write_core_regs; arm7_9->write_core_regs = arm9tdmi_write_core_regs;
arm7_9->load_word_regs = arm9tdmi_load_word_regs; arm7_9->load_word_regs = arm9tdmi_load_word_regs;
arm7_9->load_hword_reg = arm9tdmi_load_hword_reg; arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
arm7_9->load_byte_reg = arm9tdmi_load_byte_reg; arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
arm7_9->store_word_regs = arm9tdmi_store_word_regs; arm7_9->store_word_regs = arm9tdmi_store_word_regs;
arm7_9->store_hword_reg = arm9tdmi_store_hword_reg; arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
arm7_9->store_byte_reg = arm9tdmi_store_byte_reg; arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
arm7_9->write_pc = arm9tdmi_write_pc; arm7_9->write_pc = arm9tdmi_write_pc;
arm7_9->branch_resume = arm9tdmi_branch_resume; arm7_9->branch_resume = arm9tdmi_branch_resume;
arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb; arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
arm7_9->enable_single_step = arm9tdmi_enable_single_step; arm7_9->enable_single_step = arm9tdmi_enable_single_step;
arm7_9->disable_single_step = arm9tdmi_disable_single_step; arm7_9->disable_single_step = arm9tdmi_disable_single_step;
arm7_9->pre_debug_entry = NULL; arm7_9->pre_debug_entry = NULL;
arm7_9->post_debug_entry = NULL; arm7_9->post_debug_entry = NULL;
arm7_9->pre_restore_context = NULL; arm7_9->pre_restore_context = NULL;
arm7_9->post_restore_context = NULL; arm7_9->post_restore_context = NULL;
/* initialize arch-specific breakpoint handling */ /* initialize arch-specific breakpoint handling */
arm7_9->arm_bkpt = 0xdeeedeee; arm7_9->arm_bkpt = 0xdeeedeee;
arm7_9->thumb_bkpt = 0xdeee; arm7_9->thumb_bkpt = 0xdeee;
arm7_9->dbgreq_adjust_pc = 3; arm7_9->dbgreq_adjust_pc = 3;
arm7_9->arch_info = arm9tdmi; arm7_9->arch_info = arm9tdmi;
arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC; arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
arm9tdmi->arch_info = NULL; arm9tdmi->arch_info = NULL;
@ -1003,7 +1003,7 @@ int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_
{ {
arm9tdmi->variant = strdup(""); arm9tdmi->variant = strdup("");
} }
arm7_9_init_arch_info(target, arm7_9); arm7_9_init_arch_info(target, arm7_9);
/* override use of DBGRQ, this is safe on ARM9TDMI */ /* override use of DBGRQ, this is safe on ARM9TDMI */
@ -1011,7 +1011,7 @@ int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_
/* all ARM9s have the vector catch register */ /* all ARM9s have the vector catch register */
arm7_9->has_vector_catch = 1; arm7_9->has_vector_catch = 1;
return ERROR_OK; return ERROR_OK;
} }
@ -1020,28 +1020,28 @@ int arm9tdmi_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, a
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9; arm7_9_common_t *arm7_9;
arm9tdmi_common_t *arm9tdmi; arm9tdmi_common_t *arm9tdmi;
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{ {
return -1; return -1;
} }
arm7_9 = armv4_5->arch_info; arm7_9 = armv4_5->arch_info;
if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC) if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
{ {
return -1; return -1;
} }
arm9tdmi = arm7_9->arch_info; arm9tdmi = arm7_9->arch_info;
if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC) if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
{ {
return -1; return -1;
} }
*armv4_5_p = armv4_5; *armv4_5_p = armv4_5;
*arm7_9_p = arm7_9; *arm7_9_p = arm7_9;
*arm9tdmi_p = arm9tdmi; *arm9tdmi_p = arm9tdmi;
return ERROR_OK; return ERROR_OK;
} }
@ -1052,24 +1052,24 @@ int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp)
arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t)); arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t));
arm9tdmi_init_arch_info(target, arm9tdmi, target->tap, target->variant); arm9tdmi_init_arch_info(target, arm9tdmi, target->tap, target->variant);
return ERROR_OK; return ERROR_OK;
} }
int arm9tdmi_register_commands(struct command_context_s *cmd_ctx) int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
{ {
int retval; int retval;
command_t *arm9tdmi_cmd; command_t *arm9tdmi_cmd;
retval = arm7_9_register_commands(cmd_ctx); retval = arm7_9_register_commands(cmd_ctx);
arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands"); arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']"); register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
return retval; return retval;
} }
@ -1083,22 +1083,22 @@ int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, cha
reg_t *vector_catch; reg_t *vector_catch;
u32 vector_catch_value; u32 vector_catch_value;
int i, j; int i, j;
if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK) if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
{ {
command_print(cmd_ctx, "current target isn't an ARM9TDMI based target"); command_print(cmd_ctx, "current target isn't an ARM9TDMI based target");
return ERROR_OK; return ERROR_OK;
} }
vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]; vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
/* read the vector catch register if necessary */ /* read the vector catch register if necessary */
if (!vector_catch->valid) if (!vector_catch->valid)
embeddedice_read_reg(vector_catch); embeddedice_read_reg(vector_catch);
/* get the current setting */ /* get the current setting */
vector_catch_value = buf_get_u32(vector_catch->value, 0, 32); vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
if (argc > 0) if (argc > 0)
{ {
vector_catch_value = 0x0; vector_catch_value = 0x0;
@ -1123,25 +1123,25 @@ int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, cha
break; break;
} }
} }
/* complain if vector wasn't found */ /* complain if vector wasn't found */
if (!arm9tdmi_vectors[j].name) if (!arm9tdmi_vectors[j].name)
{ {
command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]); command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
/* reread current setting */ /* reread current setting */
vector_catch_value = buf_get_u32(vector_catch->value, 0, 32); vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
break; break;
} }
} }
} }
/* store new settings */ /* store new settings */
buf_set_u32(vector_catch->value, 0, 32, vector_catch_value); buf_set_u32(vector_catch->value, 0, 32, vector_catch_value);
embeddedice_store_reg(vector_catch); embeddedice_store_reg(vector_catch);
} }
/* output current settings (skip RESERVED vector) */ /* output current settings (skip RESERVED vector) */
for (i = 0; i < 8; i++) for (i = 0; i < 8; i++)
{ {
@ -1149,7 +1149,7 @@ int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, cha
{ {
command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name, command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name,
(vector_catch_value & (1 << i)) ? "catch" : "don't catch"); (vector_catch_value & (1 << i)) ? "catch" : "don't catch");
} }
} }
return ERROR_OK; return ERROR_OK;

248
src/target/cortex_swjdp.c
View File

@ -44,7 +44,7 @@
/* /*
* Transaction Mode: * Transaction Mode:
* swjdp->trans_mode = TRANS_MODE_COMPOSITE; * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
* Uses Overrun checking mode and does not do actual JTAG send/receive or transaction * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
* result checking until swjdp_end_transaction() * result checking until swjdp_end_transaction()
* This must be done before using or deallocating any return variables. * This must be done before using or deallocating any return variables.
* swjdp->trans_mode == TRANS_MODE_ATOMIC * swjdp->trans_mode == TRANS_MODE_ATOMIC
@ -63,8 +63,8 @@ int swjdp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalu
{ {
scan_field_t fields[2]; scan_field_t fields[2];
u8 out_addr_buf; u8 out_addr_buf;
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
arm_jtag_set_instr(jtag_info, instr, NULL); arm_jtag_set_instr(jtag_info, instr, NULL);
fields[0].tap = jtag_info->tap; fields[0].tap = jtag_info->tap;
@ -99,8 +99,8 @@ int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 out
scan_field_t fields[2]; scan_field_t fields[2];
u8 out_value_buf[4]; u8 out_value_buf[4];
u8 out_addr_buf; u8 out_addr_buf;
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
arm_jtag_set_instr(jtag_info, instr, NULL); arm_jtag_set_instr(jtag_info, instr, NULL);
fields[0].tap = jtag_info->tap; fields[0].tap = jtag_info->tap;
@ -138,7 +138,7 @@ int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 out
return ERROR_OK; return ERROR_OK;
} }
/* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */ /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue) int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue)
{ {
swjdp_scan(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL); swjdp_scan(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
@ -146,7 +146,7 @@ int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *o
{ {
swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
} }
/* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */ /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */
if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
{ {
@ -163,7 +163,7 @@ int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u
{ {
swjdp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); swjdp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
} }
/* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */ /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */
if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
{ {
@ -179,10 +179,10 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
u32 ctrlstat; u32 ctrlstat;
keep_alive(); keep_alive();
/* Danger!!!! BROKEN!!!! */ /* Danger!!!! BROKEN!!!! */
scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
/* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here???? /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
R956 introduced the check on return value here and now Michael Schwingen reports R956 introduced the check on return value here and now Michael Schwingen reports
that this code no longer works.... that this code no longer works....
@ -196,9 +196,9 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
if ((retval=jtag_execute_queue())!=ERROR_OK) if ((retval=jtag_execute_queue())!=ERROR_OK)
return retval; return retval;
swjdp->ack = swjdp->ack & 0x7; swjdp->ack = swjdp->ack & 0x7;
long long then=timeval_ms(); long long then=timeval_ms();
while (swjdp->ack != 2) while (swjdp->ack != 2)
{ {
@ -234,13 +234,13 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
else else
{ {
u32 dcb_dhcsr,nvic_shcsr, nvic_bfar, nvic_cfsr; u32 dcb_dhcsr,nvic_shcsr, nvic_bfar, nvic_cfsr;
if (ctrlstat & SSTICKYORUN) if (ctrlstat & SSTICKYORUN)
LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed"); LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
if (ctrlstat & SSTICKYERR) if (ctrlstat & SSTICKYERR)
LOG_ERROR("SWJ-DP STICKY ERROR"); LOG_ERROR("SWJ-DP STICKY ERROR");
/* Clear Sticky Error Bits */ /* Clear Sticky Error Bits */
scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL); scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
@ -248,8 +248,8 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
return retval; return retval;
LOG_DEBUG("swjdp: status 0x%x", ctrlstat); LOG_DEBUG("swjdp: status 0x%x", ctrlstat);
/* Can we find out the reason for the error ?? */ /* Can we find out the reason for the error ?? */
ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr); ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
ahbap_read_system_atomic_u32(swjdp, NVIC_SHCSR, &nvic_shcsr); ahbap_read_system_atomic_u32(swjdp, NVIC_SHCSR, &nvic_shcsr);
ahbap_read_system_atomic_u32(swjdp, NVIC_CFSR, &nvic_cfsr); ahbap_read_system_atomic_u32(swjdp, NVIC_CFSR, &nvic_cfsr);
@ -312,7 +312,7 @@ int ahbap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf)
int ahbap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value) int ahbap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value)
{ {
u8 out_value_buf[4]; u8 out_value_buf[4];
buf_set_u32(out_value_buf, 0, 32, value); buf_set_u32(out_value_buf, 0, 32, value);
swjdp_bankselect_apacc(swjdp, reg_addr); swjdp_bankselect_apacc(swjdp, reg_addr);
scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL); scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
@ -350,7 +350,7 @@ int ahbap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar)
swjdp->ap_tar_value = tar; swjdp->ap_tar_value = tar;
} }
if (csw & CSW_ADDRINC_MASK) if (csw & CSW_ADDRINC_MASK)
{ {
/* Do not cache TAR value when autoincrementing */ /* Do not cache TAR value when autoincrementing */
swjdp->ap_tar_value = -1; swjdp->ap_tar_value = -1;
} }
@ -371,14 +371,14 @@ int ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0); ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (address & 0xC), value ); ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (address & 0xC), value );
return ERROR_OK; return ERROR_OK;
} }
int ahbap_read_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value) int ahbap_read_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
{ {
ahbap_read_system_u32(swjdp, address, value); ahbap_read_system_u32(swjdp, address, value);
return swjdp_transaction_endcheck(swjdp); return swjdp_transaction_endcheck(swjdp);
} }
@ -402,7 +402,7 @@ int ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value)
int ahbap_write_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value) int ahbap_write_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value)
{ {
ahbap_write_system_u32(swjdp, address, value); ahbap_write_system_u32(swjdp, address, value);
return swjdp_transaction_endcheck(swjdp); return swjdp_transaction_endcheck(swjdp);
} }
@ -419,12 +419,12 @@ int ahbap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres
int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK; int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
u32 adr = address; u32 adr = address;
u8* pBuffer = buffer; u8* pBuffer = buffer;
swjdp->trans_mode = TRANS_MODE_COMPOSITE; swjdp->trans_mode = TRANS_MODE_COMPOSITE;
count >>= 2; count >>= 2;
wcount = count; wcount = count;
/* if we have an unaligned access - reorder data */ /* if we have an unaligned access - reorder data */
if (adr & 0x3u) if (adr & 0x3u)
{ {
@ -432,7 +432,7 @@ int ahbap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres
{ {
int i; int i;
outvalue = *((u32*)pBuffer); outvalue = *((u32*)pBuffer);
for (i = 0; i < 4; i++ ) for (i = 0; i < 4; i++ )
{ {
*((u8*)pBuffer + (adr & 0x3)) = outvalue; *((u8*)pBuffer + (adr & 0x3)) = outvalue;
@ -442,25 +442,25 @@ int ahbap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres
pBuffer += 4; pBuffer += 4;
} }
} }
while (wcount > 0) while (wcount > 0)
{ {
/* Adjust to write blocks within 4K aligned boundaries */ /* Adjust to write blocks within 4K aligned boundaries */
blocksize = (0x1000 - (0xFFF & address)) >> 2; blocksize = (0x1000 - (0xFFF & address)) >> 2;
if (wcount < blocksize) if (wcount < blocksize)
blocksize = wcount; blocksize = wcount;
/* handle unaligned data at 4k boundary */ /* handle unaligned data at 4k boundary */
if (blocksize == 0) if (blocksize == 0)
blocksize = 1; blocksize = 1;
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address); ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
for (writecount = 0; writecount < blocksize; writecount++) for (writecount = 0; writecount < blocksize; writecount++)
{ {
ahbap_write_reg(swjdp, AHBAP_DRW, buffer + 4 * writecount ); ahbap_write_reg(swjdp, AHBAP_DRW, buffer + 4 * writecount );
} }
if (swjdp_transaction_endcheck(swjdp) == ERROR_OK) if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
{ {
wcount = wcount - blocksize; wcount = wcount - blocksize;
@ -471,14 +471,14 @@ int ahbap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres
{ {
errorcount++; errorcount++;
} }
if (errorcount > 1) if (errorcount > 1)
{ {
LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount); LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount);
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
} }
return retval; return retval;
} }
@ -487,32 +487,32 @@ int ahbap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32
u32 outvalue; u32 outvalue;
int retval = ERROR_OK; int retval = ERROR_OK;
int wcount, blocksize, writecount, i; int wcount, blocksize, writecount, i;
swjdp->trans_mode = TRANS_MODE_COMPOSITE; swjdp->trans_mode = TRANS_MODE_COMPOSITE;
wcount = count >> 1; wcount = count >> 1;
while (wcount > 0) while (wcount > 0)
{ {
int nbytes; int nbytes;
/* Adjust to read within 4K block boundaries */ /* Adjust to read within 4K block boundaries */
blocksize = (0x1000 - (0xFFF & address)) >> 1; blocksize = (0x1000 - (0xFFF & address)) >> 1;
if (wcount < blocksize) if (wcount < blocksize)
blocksize = wcount; blocksize = wcount;
/* handle unaligned data at 4k boundary */ /* handle unaligned data at 4k boundary */
if (blocksize == 0) if (blocksize == 0)
blocksize = 1; blocksize = 1;
ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address); ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
writecount = blocksize; writecount = blocksize;
do do
{ {
nbytes = MIN((writecount << 1), 4); nbytes = MIN((writecount << 1), 4);
if (nbytes < 4 ) if (nbytes < 4 )
{ {
if (ahbap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK) if (ahbap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
@ -520,20 +520,20 @@ int ahbap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32
LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
address += nbytes >> 1; address += nbytes >> 1;
} }
else else
{ {
outvalue = *((u32*)buffer); outvalue = *((u32*)buffer);
for (i = 0; i < nbytes; i++ ) for (i = 0; i < nbytes; i++ )
{ {
*((u8*)buffer + (address & 0x3)) = outvalue; *((u8*)buffer + (address & 0x3)) = outvalue;
outvalue >>= 8; outvalue >>= 8;
address++; address++;
} }
outvalue = *((u32*)buffer); outvalue = *((u32*)buffer);
ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue); ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue);
if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
@ -542,14 +542,14 @@ int ahbap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
} }
buffer += nbytes >> 1; buffer += nbytes >> 1;
writecount -= nbytes >> 1; writecount -= nbytes >> 1;
} while (writecount); } while (writecount);
wcount -= blocksize; wcount -= blocksize;
} }
return retval; return retval;
} }
@ -557,12 +557,12 @@ int ahbap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres
{ {
u32 outvalue; u32 outvalue;
int retval = ERROR_OK; int retval = ERROR_OK;
if (count >= 4) if (count >= 4)
return ahbap_write_buf_packed_u16(swjdp, buffer, count, address); return ahbap_write_buf_packed_u16(swjdp, buffer, count, address);
swjdp->trans_mode = TRANS_MODE_COMPOSITE; swjdp->trans_mode = TRANS_MODE_COMPOSITE;
while (count > 0) while (count > 0)
{ {
ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address); ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
@ -582,28 +582,28 @@ int ahbap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32
u32 outvalue; u32 outvalue;
int retval = ERROR_OK; int retval = ERROR_OK;
int wcount, blocksize, writecount, i; int wcount, blocksize, writecount, i;
swjdp->trans_mode = TRANS_MODE_COMPOSITE; swjdp->trans_mode = TRANS_MODE_COMPOSITE;
wcount = count; wcount = count;
while (wcount > 0) while (wcount > 0)
{ {
int nbytes; int nbytes;
/* Adjust to read within 4K block boundaries */ /* Adjust to read within 4K block boundaries */
blocksize = (0x1000 - (0xFFF & address)); blocksize = (0x1000 - (0xFFF & address));
if (wcount < blocksize) if (wcount < blocksize)
blocksize = wcount; blocksize = wcount;
ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address); ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
writecount = blocksize; writecount = blocksize;
do do
{ {
nbytes = MIN(writecount, 4); nbytes = MIN(writecount, 4);
if (nbytes < 4 ) if (nbytes < 4 )
{ {
if (ahbap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK) if (ahbap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
@ -611,20 +611,20 @@ int ahbap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32
LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
address += nbytes; address += nbytes;
} }
else else
{ {
outvalue = *((u32*)buffer); outvalue = *((u32*)buffer);
for (i = 0; i < nbytes; i++ ) for (i = 0; i < nbytes; i++ )
{ {
*((u8*)buffer + (address & 0x3)) = outvalue; *((u8*)buffer + (address & 0x3)) = outvalue;
outvalue >>= 8; outvalue >>= 8;
address++; address++;
} }
outvalue = *((u32*)buffer); outvalue = *((u32*)buffer);
ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue); ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue);
if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
@ -633,14 +633,14 @@ int ahbap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
} }
buffer += nbytes; buffer += nbytes;
writecount -= nbytes; writecount -= nbytes;
} while (writecount); } while (writecount);
wcount -= blocksize; wcount -= blocksize;
} }
return retval; return retval;
} }
@ -648,12 +648,12 @@ int ahbap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address
{ {
u32 outvalue; u32 outvalue;
int retval = ERROR_OK; int retval = ERROR_OK;
if (count >= 4) if (count >= 4)
return ahbap_write_buf_packed_u8(swjdp, buffer, count, address); return ahbap_write_buf_packed_u8(swjdp, buffer, count, address);
swjdp->trans_mode = TRANS_MODE_COMPOSITE; swjdp->trans_mode = TRANS_MODE_COMPOSITE;
while (count > 0) while (count > 0)
{ {
ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
@ -664,7 +664,7 @@ int ahbap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address
address++; address++;
buffer++; buffer++;
} }
return retval; return retval;
} }
@ -680,25 +680,25 @@ int ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address
int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK; int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
u32 adr = address; u32 adr = address;
u8* pBuffer = buffer; u8* pBuffer = buffer;
swjdp->trans_mode = TRANS_MODE_COMPOSITE; swjdp->trans_mode = TRANS_MODE_COMPOSITE;
count >>= 2; count >>= 2;
wcount = count; wcount = count;
while (wcount > 0) while (wcount > 0)
{ {
/* Adjust to read within 4K block boundaries */ /* Adjust to read within 4K block boundaries */
blocksize = (0x1000 - (0xFFF & address)) >> 2; blocksize = (0x1000 - (0xFFF & address)) >> 2;
if (wcount < blocksize) if (wcount < blocksize)
blocksize = wcount; blocksize = wcount;
/* handle unaligned data at 4k boundary */ /* handle unaligned data at 4k boundary */
if (blocksize == 0) if (blocksize == 0)
blocksize = 1; blocksize = 1;
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address); ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
/* Scan out first read */ /* Scan out first read */
swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, NULL, NULL); swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, NULL, NULL);
for (readcount = 0; readcount < blocksize - 1; readcount++) for (readcount = 0; readcount < blocksize - 1; readcount++)
@ -706,27 +706,27 @@ int ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address
/* Scan out read instruction and scan in previous value */ /* Scan out read instruction and scan in previous value */
swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack); swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
} }
/* Scan in last value */ /* Scan in last value */
swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack); swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
if (swjdp_transaction_endcheck(swjdp) == ERROR_OK) if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
{ {
wcount = wcount - blocksize; wcount = wcount - blocksize;
address += 4 * blocksize; address += 4 * blocksize;
buffer += 4 * blocksize; buffer += 4 * blocksize;
} }
else else
{ {
errorcount++; errorcount++;
} }
if (errorcount > 1) if (errorcount > 1)
{ {
LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
} }
/* if we have an unaligned access - reorder data */ /* if we have an unaligned access - reorder data */
if (adr & 0x3u) if (adr & 0x3u)
{ {
@ -734,7 +734,7 @@ int ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address
{ {
int i; int i;
u32 data = *((u32*)pBuffer); u32 data = *((u32*)pBuffer);
for (i = 0; i < 4; i++ ) for (i = 0; i < 4; i++ )
{ {
*((u8*)pBuffer) = (data >> 8 * (adr & 0x3)); *((u8*)pBuffer) = (data >> 8 * (adr & 0x3));
@ -743,7 +743,7 @@ int ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address
} }
} }
} }
return retval; return retval;
} }
@ -752,27 +752,27 @@ int ahbap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32
u32 invalue; u32 invalue;
int retval = ERROR_OK; int retval = ERROR_OK;
int wcount, blocksize, readcount, i; int wcount, blocksize, readcount, i;
swjdp->trans_mode = TRANS_MODE_COMPOSITE; swjdp->trans_mode = TRANS_MODE_COMPOSITE;
wcount = count >> 1; wcount = count >> 1;
while (wcount > 0) while (wcount > 0)
{ {
int nbytes; int nbytes;
/* Adjust to read within 4K block boundaries */ /* Adjust to read within 4K block boundaries */
blocksize = (0x1000 - (0xFFF & address)) >> 1; blocksize = (0x1000 - (0xFFF & address)) >> 1;
if (wcount < blocksize) if (wcount < blocksize)
blocksize = wcount; blocksize = wcount;
ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address); ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
/* handle unaligned data at 4k boundary */ /* handle unaligned data at 4k boundary */
if (blocksize == 0) if (blocksize == 0)
blocksize = 1; blocksize = 1;
readcount = blocksize; readcount = blocksize;
do do
{ {
ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue ); ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
@ -781,21 +781,21 @@ int ahbap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32
LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
nbytes = MIN((readcount << 1), 4); nbytes = MIN((readcount << 1), 4);
for (i = 0; i < nbytes; i++ ) for (i = 0; i < nbytes; i++ )
{ {
*((u8*)buffer) = (invalue >> 8 * (address & 0x3)); *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
buffer++; buffer++;
address++; address++;
} }
readcount -= (nbytes >> 1); readcount -= (nbytes >> 1);
} while (readcount); } while (readcount);
wcount -= blocksize; wcount -= blocksize;
} }
return retval; return retval;
} }
@ -803,12 +803,12 @@ int ahbap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address
{ {
u32 invalue, i; u32 invalue, i;
int retval = ERROR_OK; int retval = ERROR_OK;
if (count >= 4) if (count >= 4)
return ahbap_read_buf_packed_u16(swjdp, buffer, count, address); return ahbap_read_buf_packed_u16(swjdp, buffer, count, address);
swjdp->trans_mode = TRANS_MODE_COMPOSITE; swjdp->trans_mode = TRANS_MODE_COMPOSITE;
while (count > 0) while (count > 0)
{ {
ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address); ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
@ -840,24 +840,24 @@ int ahbap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 a
u32 invalue; u32 invalue;
int retval = ERROR_OK; int retval = ERROR_OK;
int wcount, blocksize, readcount, i; int wcount, blocksize, readcount, i;
swjdp->trans_mode = TRANS_MODE_COMPOSITE; swjdp->trans_mode = TRANS_MODE_COMPOSITE;
wcount = count; wcount = count;
while (wcount > 0) while (wcount > 0)
{ {
int nbytes; int nbytes;
/* Adjust to read within 4K block boundaries */ /* Adjust to read within 4K block boundaries */
blocksize = (0x1000 - (0xFFF & address)); blocksize = (0x1000 - (0xFFF & address));
if (wcount < blocksize) if (wcount < blocksize)
blocksize = wcount; blocksize = wcount;
ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address); ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
readcount = blocksize; readcount = blocksize;
do do
{ {
ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue ); ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
@ -866,21 +866,21 @@ int ahbap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 a
LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
nbytes = MIN(readcount, 4); nbytes = MIN(readcount, 4);
for (i = 0; i < nbytes; i++ ) for (i = 0; i < nbytes; i++ )
{ {
*((u8*)buffer) = (invalue >> 8 * (address & 0x3)); *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
buffer++; buffer++;
address++; address++;
} }
readcount -= nbytes; readcount -= nbytes;
} while (readcount); } while (readcount);
wcount -= blocksize; wcount -= blocksize;
} }
return retval; return retval;
} }
@ -888,12 +888,12 @@ int ahbap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
{ {
u32 invalue; u32 invalue;
int retval = ERROR_OK; int retval = ERROR_OK;
if (count >= 4) if (count >= 4)
return ahbap_read_buf_packed_u8(swjdp, buffer, count, address); return ahbap_read_buf_packed_u8(swjdp, buffer, count, address);
swjdp->trans_mode = TRANS_MODE_COMPOSITE; swjdp->trans_mode = TRANS_MODE_COMPOSITE;
while (count > 0) while (count > 0)
{ {
ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
@ -912,12 +912,12 @@ int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum)
{ {
int retval; int retval;
u32 dcrdr; u32 dcrdr;
/* because the DCB_DCRDR is used for the emulated dcc channel /* because the DCB_DCRDR is used for the emulated dcc channel
* we gave to save/restore the DCB_DCRDR when used */ * we gave to save/restore the DCB_DCRDR when used */
ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr); ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr);
swjdp->trans_mode = TRANS_MODE_COMPOSITE; swjdp->trans_mode = TRANS_MODE_COMPOSITE;
/* ahbap_write_system_u32(swjdp, DCB_DCRSR, regnum); */ /* ahbap_write_system_u32(swjdp, DCB_DCRSR, regnum); */
@ -927,7 +927,7 @@ int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum)
/* ahbap_read_system_u32(swjdp, DCB_DCRDR, value); */ /* ahbap_read_system_u32(swjdp, DCB_DCRDR, value); */
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value ); ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
retval = swjdp_transaction_endcheck(swjdp); retval = swjdp_transaction_endcheck(swjdp);
ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr); ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
return retval; return retval;
@ -937,14 +937,14 @@ int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum)
{ {
int retval; int retval;
u32 dcrdr; u32 dcrdr;
/* because the DCB_DCRDR is used for the emulated dcc channel /* because the DCB_DCRDR is used for the emulated dcc channel
* we gave to save/restore the DCB_DCRDR when used */ * we gave to save/restore the DCB_DCRDR when used */
ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr); ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr);
swjdp->trans_mode = TRANS_MODE_COMPOSITE; swjdp->trans_mode = TRANS_MODE_COMPOSITE;
/* ahbap_write_system_u32(swjdp, DCB_DCRDR, core_regs[i]); */ /* ahbap_write_system_u32(swjdp, DCB_DCRDR, core_regs[i]); */
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value ); ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
@ -952,7 +952,7 @@ int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum)
/* ahbap_write_system_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */ /* ahbap_write_system_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR ); ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR );
retval = swjdp_transaction_endcheck(swjdp); retval = swjdp_transaction_endcheck(swjdp);
ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr); ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
return retval; return retval;
@ -964,16 +964,16 @@ int ahbap_debugport_init(swjdp_common_t *swjdp)
u32 ctrlstat; u32 ctrlstat;
int cnt = 0; int cnt = 0;
int retval; int retval;
LOG_DEBUG(" "); LOG_DEBUG(" ");
swjdp->ap_csw_value = -1; swjdp->ap_csw_value = -1;
swjdp->ap_tar_value = -1; swjdp->ap_tar_value = -1;
swjdp->trans_mode = TRANS_MODE_ATOMIC; swjdp->trans_mode = TRANS_MODE_ATOMIC;
swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT); swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
swjdp_write_dpacc(swjdp, SSTICKYERR, DP_CTRL_STAT); swjdp_write_dpacc(swjdp, SSTICKYERR, DP_CTRL_STAT);
swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT); swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ; swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT); swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
@ -1005,11 +1005,11 @@ int ahbap_debugport_init(swjdp_common_t *swjdp)
swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT; swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT); swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT); swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
ahbap_read_reg_u32(swjdp, 0xFC, &idreg); ahbap_read_reg_u32(swjdp, 0xFC, &idreg);
ahbap_read_reg_u32(swjdp, 0xF8, &romaddr); ahbap_read_reg_u32(swjdp, 0xF8, &romaddr);
LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr); LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr);
return ERROR_OK; return ERROR_OK;
} }

10
src/target/embeddedice.c
View File

@ -246,7 +246,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
u8 field1_out[1]; u8 field1_out[1];
u8 field2_out[1]; u8 field2_out[1];
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(ice_reg->jtag_info, 0x2); arm_jtag_scann(ice_reg->jtag_info, 0x2);
arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL); arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
@ -309,7 +309,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
u8 field1_out[1]; u8 field1_out[1];
u8 field2_out[1]; u8 field2_out[1];
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(jtag_info, 0x2); arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
@ -400,7 +400,7 @@ void embeddedice_write_reg(reg_t *reg, u32 value)
LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value); LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(ice_reg->jtag_info, 0x2); arm_jtag_scann(ice_reg->jtag_info, 0x2);
arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL); arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
@ -426,7 +426,7 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
u8 field1_out[1]; u8 field1_out[1];
u8 field2_out[1]; u8 field2_out[1];
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(jtag_info, 0x2); arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
@ -495,7 +495,7 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
else else
return ERROR_INVALID_ARGUMENTS; return ERROR_INVALID_ARGUMENTS;
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(jtag_info, 0x2); arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);

6
src/target/etb.c
View File

@ -184,7 +184,7 @@ int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
scan_field_t fields[3]; scan_field_t fields[3];
int i; int i;
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
etb_scann(etb, 0x0); etb_scann(etb, 0x0);
etb_set_instr(etb, 0xc); etb_set_instr(etb, 0xc);
@ -255,7 +255,7 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
LOG_DEBUG("%i", etb_reg->addr); LOG_DEBUG("%i", etb_reg->addr);
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
etb_scann(etb_reg->etb, 0x0); etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc); etb_set_instr(etb_reg->etb, 0xc);
@ -351,7 +351,7 @@ int etb_write_reg(reg_t *reg, u32 value)
LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value); LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
etb_scann(etb_reg->etb, 0x0); etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc); etb_set_instr(etb_reg->etb, 0xc);

4
src/target/etm.c
View File

@ -335,7 +335,7 @@ int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
LOG_DEBUG("%i", etm_reg->addr); LOG_DEBUG("%i", etm_reg->addr);
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(etm_reg->jtag_info, 0x6); arm_jtag_scann(etm_reg->jtag_info, 0x6);
arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL); arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
@ -426,7 +426,7 @@ int etm_write_reg(reg_t *reg, u32 value)
LOG_DEBUG("%i: 0x%8.8x", etm_reg->addr, value); LOG_DEBUG("%i: 0x%8.8x", etm_reg->addr, value);
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(etm_reg->jtag_info, 0x6); arm_jtag_scann(etm_reg->jtag_info, 0x6);
arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL); arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);

74
src/target/feroceon.c
View File

@ -91,7 +91,7 @@ target_type_t feroceon_target =
.assert_reset = feroceon_assert_reset, .assert_reset = feroceon_assert_reset,
.deassert_reset = arm7_9_deassert_reset, .deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm926ejs_soft_reset_halt, .soft_reset_halt = arm926ejs_soft_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list, .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.read_memory = arm7_9_read_memory, .read_memory = arm7_9_read_memory,
@ -99,7 +99,7 @@ target_type_t feroceon_target =
.bulk_write_memory = feroceon_bulk_write_memory, .bulk_write_memory = feroceon_bulk_write_memory,
.checksum_memory = arm7_9_checksum_memory, .checksum_memory = arm7_9_checksum_memory,
.blank_check_memory = arm7_9_blank_check_memory, .blank_check_memory = arm7_9_blank_check_memory,
.run_algorithm = armv4_5_run_algorithm, .run_algorithm = armv4_5_run_algorithm,
.add_breakpoint = arm7_9_add_breakpoint, .add_breakpoint = arm7_9_add_breakpoint,
@ -121,17 +121,17 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr)
u8 out_buf[4]; u8 out_buf[4];
u8 instr_buf[4]; u8 instr_buf[4];
u8 sysspeed_buf = 0x0; u8 sysspeed_buf = 0x0;
/* prepare buffer */ /* prepare buffer */
buf_set_u32(out_buf, 0, 32, 0); buf_set_u32(out_buf, 0, 32, 0);
buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32)); buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
jtag_add_end_state(TAP_PD); jtag_add_end_state(TAP_DRPAUSE);
arm_jtag_scann(jtag_info, 0x1); arm_jtag_scann(jtag_info, 0x1);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].tap = jtag_info->tap; fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32; fields[0].num_bits = 32;
fields[0].out_value = out_buf; fields[0].out_value = out_buf;
@ -141,7 +141,7 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr)
fields[0].in_handler_priv = NULL; fields[0].in_handler_priv = NULL;
fields[0].in_check_value = NULL; fields[0].in_check_value = NULL;
fields[0].in_check_mask = NULL; fields[0].in_check_mask = NULL;
fields[1].tap = jtag_info->tap; fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3; fields[1].num_bits = 3;
fields[1].out_value = &sysspeed_buf; fields[1].out_value = &sysspeed_buf;
@ -151,7 +151,7 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr)
fields[1].in_check_mask = NULL; fields[1].in_check_mask = NULL;
fields[1].in_handler = NULL; fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL; fields[1].in_handler_priv = NULL;
fields[2].tap = jtag_info->tap; fields[2].tap = jtag_info->tap;
fields[2].num_bits = 32; fields[2].num_bits = 32;
fields[2].out_value = instr_buf; fields[2].out_value = instr_buf;
@ -165,7 +165,7 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr)
jtag_add_dr_scan(3, fields, -1); jtag_add_dr_scan(3, fields, -1);
/* no jtag_add_runtest(0, -1) here */ /* no jtag_add_runtest(0, -1) here */
return ERROR_OK; return ERROR_OK;
} }
@ -174,9 +174,9 @@ void feroceon_change_to_arm(target_t *target, u32 *r0, u32 *pc)
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* /*
* save r0 before using it and put system in ARM state * save r0 before using it and put system in ARM state
* to allow common handling of ARM and THUMB debugging * to allow common handling of ARM and THUMB debugging
*/ */
@ -221,7 +221,7 @@ void feroceon_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@ -276,7 +276,7 @@ void feroceon_read_xpsr(target_t *target, u32 *xpsr, int spsr)
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@ -299,7 +299,7 @@ void feroceon_write_xpsr(target_t *target, u32 xpsr, int spsr)
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr); LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
@ -358,7 +358,7 @@ void feroceon_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@ -390,13 +390,13 @@ void feroceon_branch_resume(target_t *target)
void feroceon_branch_resume_thumb(target_t *target) void feroceon_branch_resume_thumb(target_t *target)
{ {
LOG_DEBUG("-"); LOG_DEBUG("-");
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info;
u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
(void)(r0); // use R0... (void)(r0); // use R0...
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@ -411,7 +411,7 @@ void feroceon_branch_resume_thumb(target_t *target)
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDMIA(0, 0x1), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDMIA(0, 0x1), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, pc, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, pc, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
@ -523,7 +523,7 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf
* We can't use the dcc flow control bits, so let's transfer data * We can't use the dcc flow control bits, so let's transfer data
* with 31 bits and flip the MSB each time a new data word is sent. * with 31 bits and flip the MSB each time a new data word is sent.
*/ */
static u32 dcc_code[] = static u32 dcc_code[] =
{ {
0xee115e10, /* 3: mrc p14, 0, r5, c1, c0, 0 */ 0xee115e10, /* 3: mrc p14, 0, r5, c1, c0, 0 */
0xe3a0301e, /* 1: mov r3, #30 */ 0xe3a0301e, /* 1: mov r3, #30 */
@ -586,7 +586,7 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf
armv4_5->core_cache->reg_list[0].dirty = 1; armv4_5->core_cache->reg_list[0].dirty = 1;
armv4_5->core_state = ARMV4_5_STATE_ARM; armv4_5->core_state = ARMV4_5_STATE_ARM;
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0);
arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1); arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
/* send data over */ /* send data over */
@ -597,12 +597,12 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf
{ {
u32 y = target_buffer_get_u32(target, buffer); u32 y = target_buffer_get_u32(target, buffer);
u32 z = (x >> 1) | (y >> shift) | (flip ^= 0x80000000); u32 z = (x >> 1) | (y >> shift) | (flip ^= 0x80000000);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z);
x = y << (32 - shift); x = y << (32 - shift);
if (++shift >= 32 || i + 1 >= count) if (++shift >= 32 || i + 1 >= count)
{ {
z = (x >> 1) | (flip ^= 0x80000000); z = (x >> 1) | (flip ^= 0x80000000);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z);
x = 0; x = 0;
shift = 1; shift = 1;
} }
@ -644,7 +644,7 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp)
armv4_5_common_t *armv4_5; armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9; arm7_9_common_t *arm7_9;
arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t)); arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
arm926ejs_init_arch_info(target, arm926ejs, target->tap, target->variant); arm926ejs_init_arch_info(target, arm926ejs, target->tap, target->variant);
armv4_5 = target->arch_info; armv4_5 = target->arch_info;
@ -678,8 +678,8 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp)
arm7_9->set_special_dbgrq = feroceon_set_dbgrq; arm7_9->set_special_dbgrq = feroceon_set_dbgrq;
/* only one working comparator */ /* only one working comparator */
arm7_9->wp_available_max = 1; arm7_9->wp_available_max = 1;
arm7_9->wp1_used_default = -1; arm7_9->wp1_used_default = -1;
return ERROR_OK; return ERROR_OK;
} }
@ -694,27 +694,27 @@ int feroceon_examine(struct target_s *target)
retval = arm9tdmi_examine(target); retval = arm9tdmi_examine(target);
if (retval!=ERROR_OK) if (retval!=ERROR_OK)
return retval; return retval;
armv4_5 = target->arch_info; armv4_5 = target->arch_info;
arm7_9 = armv4_5->arch_info; arm7_9 = armv4_5->arch_info;
/* the COMMS_CTRL bits are all contiguous */ /* the COMMS_CTRL bits are all contiguous */
if (buf_get_u32(arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL].value, 2, 4) != 6) if (buf_get_u32(arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL].value, 2, 4) != 6)
LOG_ERROR("unexpected Feroceon EICE version signature"); LOG_ERROR("unexpected Feroceon EICE version signature");
arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].size = 6; arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].size = 6;
arm7_9->eice_cache->reg_list[EICE_DBG_STAT].size = 5; arm7_9->eice_cache->reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_monitor_mode = 1; arm7_9->has_monitor_mode = 1;
/* vector catch reg is not initialized on reset */ /* vector catch reg is not initialized on reset */
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0);
/* clear monitor mode, enable comparators */ /* clear monitor mode, enable comparators */
embeddedice_read_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]); embeddedice_read_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
jtag_execute_queue(); jtag_execute_queue();
buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 4, 1, 0); buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 4, 1, 0);
buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 5, 1, 0); buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 5, 1, 0);
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]); embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
return ERROR_OK; return ERROR_OK;
} }

6
src/target/mips_ejtag.c
View File

@ -65,7 +65,7 @@ int mips_ejtag_get_idcode(mips_ejtag_t *ejtag_info, u32 *idcode, in_handler_t ha
{ {
scan_field_t field; scan_field_t field;
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE, NULL);
@ -92,7 +92,7 @@ int mips_ejtag_get_impcode(mips_ejtag_t *ejtag_info, u32 *impcode, in_handler_t
{ {
scan_field_t field; scan_field_t field;
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE, NULL);
@ -202,7 +202,7 @@ int mips_ejtag_config_step(mips_ejtag_t *ejtag_info, int enable_step)
int mips_ejtag_enter_debug(mips_ejtag_t *ejtag_info) int mips_ejtag_enter_debug(mips_ejtag_t *ejtag_info)
{ {
u32 ejtag_ctrl; u32 ejtag_ctrl;
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
/* set debug break bit */ /* set debug break bit */

218
src/target/mips_m4k.c
View File

@ -67,7 +67,7 @@ target_type_t mips_m4k_target =
.assert_reset = mips_m4k_assert_reset, .assert_reset = mips_m4k_assert_reset,
.deassert_reset = mips_m4k_deassert_reset, .deassert_reset = mips_m4k_deassert_reset,
.soft_reset_halt = mips_m4k_soft_reset_halt, .soft_reset_halt = mips_m4k_soft_reset_halt,
.get_gdb_reg_list = mips32_get_gdb_reg_list, .get_gdb_reg_list = mips32_get_gdb_reg_list,
.read_memory = mips_m4k_read_memory, .read_memory = mips_m4k_read_memory,
@ -75,7 +75,7 @@ target_type_t mips_m4k_target =
.bulk_write_memory = mips_m4k_bulk_write_memory, .bulk_write_memory = mips_m4k_bulk_write_memory,
.checksum_memory = NULL, .checksum_memory = NULL,
.blank_check_memory = NULL, .blank_check_memory = NULL,
.run_algorithm = mips32_run_algorithm, .run_algorithm = mips32_run_algorithm,
.add_breakpoint = mips_m4k_add_breakpoint, .add_breakpoint = mips_m4k_add_breakpoint,
@ -91,10 +91,10 @@ target_type_t mips_m4k_target =
}; };
int mips_m4k_examine_debug_reason(target_t *target) int mips_m4k_examine_debug_reason(target_t *target)
{ {
int break_status; int break_status;
int retval; int retval;
if ((target->debug_reason != DBG_REASON_DBGRQ) if ((target->debug_reason != DBG_REASON_DBGRQ)
&& (target->debug_reason != DBG_REASON_SINGLESTEP)) && (target->debug_reason != DBG_REASON_SINGLESTEP))
{ {
@ -108,7 +108,7 @@ int mips_m4k_examine_debug_reason(target_t *target)
return retval; return retval;
target->debug_reason = DBG_REASON_BREAKPOINT; target->debug_reason = DBG_REASON_BREAKPOINT;
} }
/* get info about data breakpoint support */ /* get info about data breakpoint support */
if ((retval = target_read_u32(target, 0xFF302000, &break_status)) != ERROR_OK) if ((retval = target_read_u32(target, 0xFF302000, &break_status)) != ERROR_OK)
return retval; return retval;
@ -120,7 +120,7 @@ int mips_m4k_examine_debug_reason(target_t *target)
target->debug_reason = DBG_REASON_WATCHPOINT; target->debug_reason = DBG_REASON_WATCHPOINT;
} }
} }
return ERROR_OK; return ERROR_OK;
} }
@ -129,29 +129,29 @@ int mips_m4k_debug_entry(target_t *target)
mips32_common_t *mips32 = target->arch_info; mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
u32 debug_reg; u32 debug_reg;
/* read debug register */ /* read debug register */
mips_ejtag_read_debug(ejtag_info, &debug_reg); mips_ejtag_read_debug(ejtag_info, &debug_reg);
/* make sure break uit configured */ /* make sure break uit configured */
mips32_configure_break_unit(target); mips32_configure_break_unit(target);
/* attempt to find halt reason */ /* attempt to find halt reason */
mips_m4k_examine_debug_reason(target); mips_m4k_examine_debug_reason(target);
/* clear single step if active */ /* clear single step if active */
if (debug_reg & EJTAG_DEBUG_DSS) if (debug_reg & EJTAG_DEBUG_DSS)
{ {
/* stopped due to single step - clear step bit */ /* stopped due to single step - clear step bit */
mips_ejtag_config_step(ejtag_info, 0); mips_ejtag_config_step(ejtag_info, 0);
} }
mips32_save_context(target); mips32_save_context(target);
LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s", LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s",
*(u32*)(mips32->core_cache->reg_list[MIPS32_PC].value), *(u32*)(mips32->core_cache->reg_list[MIPS32_PC].value),
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
return ERROR_OK; return ERROR_OK;
} }
@ -161,48 +161,48 @@ int mips_m4k_poll(target_t *target)
mips32_common_t *mips32 = target->arch_info; mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
u32 ejtag_ctrl = ejtag_info->ejtag_ctrl; u32 ejtag_ctrl = ejtag_info->ejtag_ctrl;
/* read ejtag control reg */ /* read ejtag control reg */
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
/* clear this bit before handling polling /* clear this bit before handling polling
* as after reset registers will read zero */ * as after reset registers will read zero */
if (ejtag_ctrl & EJTAG_CTRL_ROCC) if (ejtag_ctrl & EJTAG_CTRL_ROCC)
{ {
/* we have detected a reset, clear flag /* we have detected a reset, clear flag
* otherwise ejtag will not work */ * otherwise ejtag will not work */
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC; ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
LOG_DEBUG("Reset Detected"); LOG_DEBUG("Reset Detected");
} }
/* check for processor halted */ /* check for processor halted */
if (ejtag_ctrl & EJTAG_CTRL_BRKST) if (ejtag_ctrl & EJTAG_CTRL_BRKST)
{ {
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
{ {
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
target->state = TARGET_HALTED; target->state = TARGET_HALTED;
if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK) if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
return retval; return retval;
target_call_event_callbacks(target, TARGET_EVENT_HALTED); target_call_event_callbacks(target, TARGET_EVENT_HALTED);
} }
else if (target->state == TARGET_DEBUG_RUNNING) else if (target->state == TARGET_DEBUG_RUNNING)
{ {
target->state = TARGET_HALTED; target->state = TARGET_HALTED;
if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK) if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
return retval; return retval;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
} }
} }
@ -210,9 +210,9 @@ int mips_m4k_poll(target_t *target)
{ {
target->state = TARGET_RUNNING; target->state = TARGET_RUNNING;
} }
// LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl); // LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
return ERROR_OK; return ERROR_OK;
} }
@ -220,22 +220,22 @@ int mips_m4k_halt(struct target_s *target)
{ {
mips32_common_t *mips32 = target->arch_info; mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("target->state: %s", LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
if (target->state == TARGET_HALTED) if (target->state == TARGET_HALTED)
{ {
LOG_DEBUG("target was already halted"); LOG_DEBUG("target was already halted");
return ERROR_OK; return ERROR_OK;
} }
if (target->state == TARGET_UNKNOWN) if (target->state == TARGET_UNKNOWN)
{ {
LOG_WARNING("target was in unknown state when halt was requested"); LOG_WARNING("target was in unknown state when halt was requested");
} }
if (target->state == TARGET_RESET) if (target->state == TARGET_RESET)
{ {
if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst) if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
{ {
@ -248,16 +248,16 @@ int mips_m4k_halt(struct target_s *target)
* debug entry was already prepared in mips32_prepare_reset_halt() * debug entry was already prepared in mips32_prepare_reset_halt()
*/ */
target->debug_reason = DBG_REASON_DBGRQ; target->debug_reason = DBG_REASON_DBGRQ;
return ERROR_OK; return ERROR_OK;
} }
} }
/* break processor */ /* break processor */
mips_ejtag_enter_debug(ejtag_info); mips_ejtag_enter_debug(ejtag_info);
target->debug_reason = DBG_REASON_DBGRQ; target->debug_reason = DBG_REASON_DBGRQ;
return ERROR_OK; return ERROR_OK;
} }
@ -266,28 +266,28 @@ int mips_m4k_assert_reset(target_t *target)
mips32_common_t *mips32 = target->arch_info; mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
mips_m4k_common_t *mips_m4k = mips32->arch_info; mips_m4k_common_t *mips_m4k = mips32->arch_info;
LOG_DEBUG("target->state: %s", LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
if (!(jtag_reset_config & RESET_HAS_SRST)) if (!(jtag_reset_config & RESET_HAS_SRST))
{ {
LOG_ERROR("Can't assert SRST"); LOG_ERROR("Can't assert SRST");
return ERROR_FAIL; return ERROR_FAIL;
} }
if (target->reset_halt) if (target->reset_halt)
{ {
/* use hardware to catch reset */ /* use hardware to catch reset */
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
} }
else else
{ {
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
} }
if (strcmp(mips_m4k->variant, "ejtag_srst") == 0) if (strcmp(mips_m4k->variant, "ejtag_srst") == 0)
{ {
u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST; u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
@ -307,7 +307,7 @@ int mips_m4k_assert_reset(target_t *target)
jtag_add_reset(0, 1); jtag_add_reset(0, 1);
} }
} }
target->state = TARGET_RESET; target->state = TARGET_RESET;
jtag_add_sleep(50000); jtag_add_sleep(50000);
@ -319,18 +319,18 @@ int mips_m4k_assert_reset(target_t *target)
if ((retval = target_halt(target))!=ERROR_OK) if ((retval = target_halt(target))!=ERROR_OK)
return retval; return retval;
} }
return ERROR_OK; return ERROR_OK;
} }
int mips_m4k_deassert_reset(target_t *target) int mips_m4k_deassert_reset(target_t *target)
{ {
LOG_DEBUG("target->state: %s", LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
/* deassert reset lines */ /* deassert reset lines */
jtag_add_reset(0, 0); jtag_add_reset(0, 0);
return ERROR_OK; return ERROR_OK;
} }
@ -344,15 +344,15 @@ int mips_m4k_single_step_core(target_t *target)
{ {
mips32_common_t *mips32 = target->arch_info; mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
/* configure single step mode */ /* configure single step mode */
mips_ejtag_config_step(ejtag_info, 1); mips_ejtag_config_step(ejtag_info, 1);
/* exit debug mode */ /* exit debug mode */
mips_ejtag_exit_debug(ejtag_info, 1); mips_ejtag_exit_debug(ejtag_info, 1);
mips_m4k_debug_entry(target); mips_m4k_debug_entry(target);
return ERROR_OK; return ERROR_OK;
} }
@ -362,20 +362,20 @@ int mips_m4k_resume(struct target_s *target, int current, u32 address, int handl
mips_ejtag_t *ejtag_info = &mips32->ejtag_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
breakpoint_t *breakpoint = NULL; breakpoint_t *breakpoint = NULL;
u32 resume_pc; u32 resume_pc;
if (target->state != TARGET_HALTED) if (target->state != TARGET_HALTED)
{ {
LOG_WARNING("target not halted"); LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED; return ERROR_TARGET_NOT_HALTED;
} }
if (!debug_execution) if (!debug_execution)
{ {
target_free_all_working_areas(target); target_free_all_working_areas(target);
mips_m4k_enable_breakpoints(target); mips_m4k_enable_breakpoints(target);
mips_m4k_enable_watchpoints(target); mips_m4k_enable_watchpoints(target);
} }
/* current = 1: continue on current pc, otherwise continue at <address> */ /* current = 1: continue on current pc, otherwise continue at <address> */
if (!current) if (!current)
{ {
@ -383,11 +383,11 @@ int mips_m4k_resume(struct target_s *target, int current, u32 address, int handl
mips32->core_cache->reg_list[MIPS32_PC].dirty = 1; mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
mips32->core_cache->reg_list[MIPS32_PC].valid = 1; mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
} }
resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32); resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
mips32_restore_context(target); mips32_restore_context(target);
/* the front-end may request us not to handle breakpoints */ /* the front-end may request us not to handle breakpoints */
if (handle_breakpoints) if (handle_breakpoints)
{ {
@ -400,14 +400,14 @@ int mips_m4k_resume(struct target_s *target, int current, u32 address, int handl
mips_m4k_set_breakpoint(target, breakpoint); mips_m4k_set_breakpoint(target, breakpoint);
} }
} }
/* exit debug mode - enable interrupts if required */ /* exit debug mode - enable interrupts if required */
mips_ejtag_exit_debug(ejtag_info, !debug_execution); mips_ejtag_exit_debug(ejtag_info, !debug_execution);
target->debug_reason = DBG_REASON_NOTHALTED; target->debug_reason = DBG_REASON_NOTHALTED;
/* registers are now invalid */ /* registers are now invalid */
mips32_invalidate_core_regs(target); mips32_invalidate_core_regs(target);
if (!debug_execution) if (!debug_execution)
{ {
target->state = TARGET_RUNNING; target->state = TARGET_RUNNING;
@ -420,7 +420,7 @@ int mips_m4k_resume(struct target_s *target, int current, u32 address, int handl
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
LOG_DEBUG("target debug resumed at 0x%x", resume_pc); LOG_DEBUG("target debug resumed at 0x%x", resume_pc);
} }
return ERROR_OK; return ERROR_OK;
} }
@ -440,43 +440,43 @@ int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_
/* current = 1: continue on current pc, otherwise continue at <address> */ /* current = 1: continue on current pc, otherwise continue at <address> */
if (!current) if (!current)
buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address); buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
/* the front-end may request us not to handle breakpoints */ /* the front-end may request us not to handle breakpoints */
if (handle_breakpoints) if (handle_breakpoints)
if ((breakpoint = breakpoint_find(target, buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32)))) if ((breakpoint = breakpoint_find(target, buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32))))
mips_m4k_unset_breakpoint(target, breakpoint); mips_m4k_unset_breakpoint(target, breakpoint);
/* restore context */ /* restore context */
mips32_restore_context(target); mips32_restore_context(target);
/* configure single step mode */ /* configure single step mode */
mips_ejtag_config_step(ejtag_info, 1); mips_ejtag_config_step(ejtag_info, 1);
target->debug_reason = DBG_REASON_SINGLESTEP; target->debug_reason = DBG_REASON_SINGLESTEP;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED); target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
/* exit debug mode */ /* exit debug mode */
mips_ejtag_exit_debug(ejtag_info, 1); mips_ejtag_exit_debug(ejtag_info, 1);
/* registers are now invalid */ /* registers are now invalid */
mips32_invalidate_core_regs(target); mips32_invalidate_core_regs(target);
if (breakpoint) if (breakpoint)
mips_m4k_set_breakpoint(target, breakpoint); mips_m4k_set_breakpoint(target, breakpoint);
LOG_DEBUG("target stepped "); LOG_DEBUG("target stepped ");
mips_m4k_debug_entry(target); mips_m4k_debug_entry(target);
target_call_event_callbacks(target, TARGET_EVENT_HALTED); target_call_event_callbacks(target, TARGET_EVENT_HALTED);
return ERROR_OK; return ERROR_OK;
} }
void mips_m4k_enable_breakpoints(struct target_s *target) void mips_m4k_enable_breakpoints(struct target_s *target)
{ {
breakpoint_t *breakpoint = target->breakpoints; breakpoint_t *breakpoint = target->breakpoints;
/* set any pending breakpoints */ /* set any pending breakpoints */
while (breakpoint) while (breakpoint)
{ {
@ -490,17 +490,17 @@ int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{ {
mips32_common_t *mips32 = target->arch_info; mips32_common_t *mips32 = target->arch_info;
mips32_comparator_t * comparator_list = mips32->inst_break_list; mips32_comparator_t * comparator_list = mips32->inst_break_list;
if (breakpoint->set) if (breakpoint->set)
{ {
LOG_WARNING("breakpoint already set"); LOG_WARNING("breakpoint already set");
return ERROR_OK; return ERROR_OK;
} }
if (breakpoint->type == BKPT_HARD) if (breakpoint->type == BKPT_HARD)
{ {
int bp_num = 0; int bp_num = 0;
while(comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints)) while(comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
bp_num++; bp_num++;
if (bp_num >= mips32->num_inst_bpoints) if (bp_num >= mips32->num_inst_bpoints)
@ -521,7 +521,7 @@ int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{ {
} }
return ERROR_OK; return ERROR_OK;
} }
@ -536,7 +536,7 @@ int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
LOG_WARNING("breakpoint not set"); LOG_WARNING("breakpoint not set");
return ERROR_OK; return ERROR_OK;
} }
if (breakpoint->type == BKPT_HARD) if (breakpoint->type == BKPT_HARD)
{ {
int bp_num = breakpoint->set - 1; int bp_num = breakpoint->set - 1;
@ -554,26 +554,26 @@ int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
} }
breakpoint->set = 0; breakpoint->set = 0;
return ERROR_OK; return ERROR_OK;
} }
int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{ {
mips32_common_t *mips32 = target->arch_info; mips32_common_t *mips32 = target->arch_info;
if (mips32->num_inst_bpoints_avail < 1) if (mips32->num_inst_bpoints_avail < 1)
{ {
LOG_INFO("no hardware breakpoint available"); LOG_INFO("no hardware breakpoint available");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
} }
/* default to hardware for now */ /* default to hardware for now */
breakpoint->type = BKPT_HARD; breakpoint->type = BKPT_HARD;
mips32->num_inst_bpoints_avail--; mips32->num_inst_bpoints_avail--;
mips_m4k_set_breakpoint(target, breakpoint); mips_m4k_set_breakpoint(target, breakpoint);
return ERROR_OK; return ERROR_OK;
} }
@ -581,21 +581,21 @@ int mips_m4k_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint
{ {
/* get pointers to arch-specific information */ /* get pointers to arch-specific information */
mips32_common_t *mips32 = target->arch_info; mips32_common_t *mips32 = target->arch_info;
if (target->state != TARGET_HALTED) if (target->state != TARGET_HALTED)
{ {
LOG_WARNING("target not halted"); LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED; return ERROR_TARGET_NOT_HALTED;
} }
if (breakpoint->set) if (breakpoint->set)
{ {
mips_m4k_unset_breakpoint(target, breakpoint); mips_m4k_unset_breakpoint(target, breakpoint);
} }
if (breakpoint->type == BKPT_HARD) if (breakpoint->type == BKPT_HARD)
mips32->num_inst_bpoints_avail++; mips32->num_inst_bpoints_avail++;
return ERROR_OK; return ERROR_OK;
} }
@ -626,7 +626,7 @@ int mips_m4k_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint
void mips_m4k_enable_watchpoints(struct target_s *target) void mips_m4k_enable_watchpoints(struct target_s *target)
{ {
watchpoint_t *watchpoint = target->watchpoints; watchpoint_t *watchpoint = target->watchpoints;
/* set any pending watchpoints */ /* set any pending watchpoints */
while (watchpoint) while (watchpoint)
{ {
@ -640,7 +640,7 @@ int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 cou
{ {
mips32_common_t *mips32 = target->arch_info; mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
if (target->state != TARGET_HALTED) if (target->state != TARGET_HALTED)
@ -655,7 +655,7 @@ int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 cou
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS; return ERROR_TARGET_UNALIGNED_ACCESS;
switch (size) switch (size)
{ {
case 4: case 4:
@ -679,7 +679,7 @@ int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 co
{ {
mips32_common_t *mips32 = target->arch_info; mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
if (target->state != TARGET_HALTED) if (target->state != TARGET_HALTED)
@ -694,7 +694,7 @@ int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 co
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS; return ERROR_TARGET_UNALIGNED_ACCESS;
switch (size) switch (size)
{ {
case 4: case 4:
@ -711,14 +711,14 @@ int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 co
exit(-1); exit(-1);
break; break;
} }
return ERROR_OK; return ERROR_OK;
} }
int mips_m4k_register_commands(struct command_context_s *cmd_ctx) int mips_m4k_register_commands(struct command_context_s *cmd_ctx)
{ {
int retval; int retval;
retval = mips32_register_commands(cmd_ctx); retval = mips32_register_commands(cmd_ctx);
return retval; return retval;
} }
@ -726,7 +726,7 @@ int mips_m4k_register_commands(struct command_context_s *cmd_ctx)
int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target) int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
{ {
mips32_build_reg_cache(target); mips32_build_reg_cache(target);
return ERROR_OK; return ERROR_OK;
} }
@ -738,7 +738,7 @@ int mips_m4k_quit(void)
int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap, const char *variant) int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap, const char *variant)
{ {
mips32_common_t *mips32 = &mips_m4k->mips32_common; mips32_common_t *mips32 = &mips_m4k->mips32_common;
if (variant) if (variant)
{ {
mips_m4k->variant = strdup(variant); mips_m4k->variant = strdup(variant);
@ -747,22 +747,22 @@ int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_
{ {
mips_m4k->variant = strdup(""); mips_m4k->variant = strdup("");
} }
mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC; mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
/* initialize mips4k specific info */ /* initialize mips4k specific info */
mips32_init_arch_info(target, mips32, tap, variant); mips32_init_arch_info(target, mips32, tap, variant);
mips32->arch_info = mips_m4k; mips32->arch_info = mips_m4k;
return ERROR_OK; return ERROR_OK;
} }
int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp) int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp)
{ {
mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t)); mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t));
mips_m4k_init_arch_info(target, mips_m4k, target->tap, target->variant); mips_m4k_init_arch_info(target, mips_m4k, target->tap, target->variant);
return ERROR_OK; return ERROR_OK;
} }
@ -772,11 +772,11 @@ int mips_m4k_examine(struct target_s *target)
mips32_common_t *mips32 = target->arch_info; mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
u32 idcode = 0; u32 idcode = 0;
if (!target->type->examined) if (!target->type->examined)
{ {
mips_ejtag_get_idcode(ejtag_info, &idcode, NULL); mips_ejtag_get_idcode(ejtag_info, &idcode, NULL);
if (((idcode >> 1) & 0x7FF) == 0x29) if (((idcode >> 1) & 0x7FF) == 0x29)
{ {
/* we are using a pic32mx so select ejtag port /* we are using a pic32mx so select ejtag port
@ -785,14 +785,14 @@ int mips_m4k_examine(struct target_s *target)
LOG_DEBUG("PIC32MX Detected - using EJTAG Interface"); LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
} }
} }
/* init rest of ejtag interface */ /* init rest of ejtag interface */
if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK) if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
return retval; return retval;
if ((retval = mips32_examine(target)) != ERROR_OK) if ((retval = mips32_examine(target)) != ERROR_OK)
return retval; return retval;
return ERROR_OK; return ERROR_OK;
} }

64
src/target/xscale.c
View File

@ -252,7 +252,7 @@ int xscale_read_dcsr(target_t *target)
u8 field2_check_value = 0x0; u8 field2_check_value = 0x0;
u8 field2_check_mask = 0x1; u8 field2_check_mask = 0x1;
jtag_add_end_state(TAP_PD); jtag_add_end_state(TAP_DRPAUSE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
buf_set_u32(&field0, 1, 1, xscale->hold_rst); buf_set_u32(&field0, 1, 1, xscale->hold_rst);
@ -300,7 +300,7 @@ int xscale_read_dcsr(target_t *target)
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value; fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
fields[1].in_value = NULL; fields[1].in_value = NULL;
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
jtag_add_dr_scan(3, fields, -1); jtag_add_dr_scan(3, fields, -1);
@ -332,9 +332,9 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words)
int i; int i;
path[0] = TAP_SDS; path[0] = TAP_DRSELECT;
path[1] = TAP_CD; path[1] = TAP_DRCAPTURE;
path[2] = TAP_SD; path[2] = TAP_DRSHIFT;
fields[0].tap = xscale->jtag_info.tap; fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 3; fields[0].num_bits = 3;
@ -362,9 +362,9 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words)
fields[2].in_value = NULL; fields[2].in_value = NULL;
jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
jtag_add_runtest(1, -1); /* ensures that we're in the TAP_RTI state as the above could be a no-op */ jtag_add_runtest(1, -1); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
/* repeat until all words have been collected */ /* repeat until all words have been collected */
int attempts=0; int attempts=0;
@ -379,7 +379,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words)
fields[1].in_handler_priv = (u8*)&field1[i]; fields[1].in_handler_priv = (u8*)&field1[i];
jtag_add_pathmove(3, path); jtag_add_pathmove(3, path);
jtag_add_dr_scan(3, fields, TAP_RTI); jtag_add_dr_scan(3, fields, TAP_IDLE);
words_scheduled++; words_scheduled++;
} }
@ -442,20 +442,20 @@ int xscale_read_tx(target_t *target, int consume)
u8 field2_check_value = 0x0; u8 field2_check_value = 0x0;
u8 field2_check_mask = 0x1; u8 field2_check_mask = 0x1;
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
path[0] = TAP_SDS; path[0] = TAP_DRSELECT;
path[1] = TAP_CD; path[1] = TAP_DRCAPTURE;
path[2] = TAP_SD; path[2] = TAP_DRSHIFT;
noconsume_path[0] = TAP_SDS; noconsume_path[0] = TAP_DRSELECT;
noconsume_path[1] = TAP_CD; noconsume_path[1] = TAP_DRCAPTURE;
noconsume_path[2] = TAP_E1D; noconsume_path[2] = TAP_DREXIT1;
noconsume_path[3] = TAP_PD; noconsume_path[3] = TAP_DRPAUSE;
noconsume_path[4] = TAP_E2D; noconsume_path[4] = TAP_DREXIT2;
noconsume_path[5] = TAP_SD; noconsume_path[5] = TAP_DRSHIFT;
fields[0].tap = xscale->jtag_info.tap; fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 3; fields[0].num_bits = 3;
@ -499,7 +499,7 @@ int xscale_read_tx(target_t *target, int consume)
jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path); jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path);
} }
jtag_add_dr_scan(3, fields, TAP_RTI); jtag_add_dr_scan(3, fields, TAP_IDLE);
if ((retval = jtag_execute_queue()) != ERROR_OK) if ((retval = jtag_execute_queue()) != ERROR_OK)
{ {
@ -551,7 +551,7 @@ int xscale_write_rx(target_t *target)
u8 field2_check_value = 0x0; u8 field2_check_value = 0x0;
u8 field2_check_mask = 0x1; u8 field2_check_mask = 0x1;
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx);
@ -588,7 +588,7 @@ int xscale_write_rx(target_t *target)
LOG_DEBUG("polling RX"); LOG_DEBUG("polling RX");
for (;;) for (;;)
{ {
jtag_add_dr_scan(3, fields, TAP_RTI); jtag_add_dr_scan(3, fields, TAP_IDLE);
if ((retval = jtag_execute_queue()) != ERROR_OK) if ((retval = jtag_execute_queue()) != ERROR_OK)
{ {
@ -617,7 +617,7 @@ int xscale_write_rx(target_t *target)
/* set rx_valid */ /* set rx_valid */
field2 = 0x1; field2 = 0x1;
jtag_add_dr_scan(3, fields, TAP_RTI); jtag_add_dr_scan(3, fields, TAP_IDLE);
if ((retval = jtag_execute_queue()) != ERROR_OK) if ((retval = jtag_execute_queue()) != ERROR_OK)
{ {
@ -640,7 +640,7 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size)
int done_count = 0; int done_count = 0;
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx);
@ -683,7 +683,7 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size)
3, 3,
bits, bits,
t, t,
TAP_RTI); TAP_IDLE);
buffer += size; buffer += size;
} }
@ -726,7 +726,7 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
if (ext_dbg_brk != -1) if (ext_dbg_brk != -1)
xscale->external_debug_break = ext_dbg_brk; xscale->external_debug_break = ext_dbg_brk;
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
buf_set_u32(&field0, 1, 1, xscale->hold_rst); buf_set_u32(&field0, 1, 1, xscale->hold_rst);
@ -796,7 +796,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8])
LOG_DEBUG("loading miniIC at 0x%8.8x", va); LOG_DEBUG("loading miniIC at 0x%8.8x", va);
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
/* CMD is b010 for Main IC and b011 for Mini IC */ /* CMD is b010 for Main IC and b011 for Mini IC */
@ -859,7 +859,7 @@ int xscale_invalidate_ic_line(target_t *target, u32 va)
scan_field_t fields[2]; scan_field_t fields[2];
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
/* CMD for invalidate IC line b000, bits [6:4] b000 */ /* CMD for invalidate IC line b000, bits [6:4] b000 */
@ -1597,7 +1597,7 @@ int xscale_assert_reset(target_t *target)
/* select DCSR instruction (set endstate to R-T-I to ensure we don't /* select DCSR instruction (set endstate to R-T-I to ensure we don't
* end up in T-L-R, which would reset JTAG * end up in T-L-R, which would reset JTAG
*/ */
jtag_add_end_state(TAP_RTI); jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
/* set Hold reset, Halt mode and Trap Reset */ /* set Hold reset, Halt mode and Trap Reset */
@ -1620,7 +1620,7 @@ int xscale_assert_reset(target_t *target)
if (target->reset_halt) if (target->reset_halt)
{ {
int retval; int retval;
if ((retval = target_halt(target))!=ERROR_OK) if ((retval = target_halt(target))!=ERROR_OK)
return retval; return retval;
} }
@ -1671,7 +1671,7 @@ int xscale_deassert_reset(target_t *target)
/* wait 300ms; 150 and 100ms were not enough */ /* wait 300ms; 150 and 100ms were not enough */
jtag_add_sleep(300*1000); jtag_add_sleep(300*1000);
jtag_add_runtest(2030, TAP_RTI); jtag_add_runtest(2030, TAP_IDLE);
jtag_execute_queue(); jtag_execute_queue();
/* set Hold reset, Halt mode and Trap Reset */ /* set Hold reset, Halt mode and Trap Reset */
@ -1734,7 +1734,7 @@ int xscale_deassert_reset(target_t *target)
xscale_load_ic(target, 1, 0x0, xscale->low_vectors); xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors); xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
jtag_add_runtest(30, TAP_RTI); jtag_add_runtest(30, TAP_IDLE);
jtag_add_sleep(100000); jtag_add_sleep(100000);
@ -3381,7 +3381,7 @@ int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char **
command_print(cmd_ctx, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled"); command_print(cmd_ctx, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled");
if (dcache) if (dcache)
command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled"); command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
return ERROR_OK; return ERROR_OK;
} }

76
src/xsvf/xsvf.c
View File

@ -62,9 +62,9 @@ int xenddr = 0;
enum tap_state xsvf_to_tap[] = enum tap_state xsvf_to_tap[] =
{ {
TAP_TLR, TAP_RTI, TAP_RESET, TAP_IDLE,
TAP_SDS, TAP_CD, TAP_SD, TAP_E1D, TAP_PD, TAP_E2D, TAP_UD, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT, TAP_DREXIT1, TAP_DRPAUSE, TAP_DREXIT2, TAP_DRUPDATE,
TAP_SIS, TAP_CI, TAP_SI, TAP_E1I, TAP_PI, TAP_E2I, TAP_UI, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT, TAP_IREXIT1, TAP_IRPAUSE, TAP_IREXIT2, TAP_IRUPDATE,
}; };
int tap_to_xsvf[] = int tap_to_xsvf[] =
@ -76,23 +76,23 @@ int tap_to_xsvf[] =
/* xsvf has it's own definition of a statemove. This needs /* xsvf has it's own definition of a statemove. This needs
* to be handled according to the specs, which has nothing * to be handled according to the specs, which has nothing
* to do with the JTAG spec or OpenOCD as such. * to do with the JTAG spec or OpenOCD as such.
* *
* Implemented via jtag_add_pathmove(). * Implemented via jtag_add_pathmove().
*/ */
void xsvf_add_statemove(enum tap_state state) void xsvf_add_statemove(enum tap_state state)
{ {
enum tap_state moves[7]; /* max # of transitions */ enum tap_state moves[7]; /* max # of transitions */
int i; int i;
enum tap_state curstate = cmd_queue_cur_state; enum tap_state curstate = cmd_queue_cur_state;
u8 move = TAP_MOVE(cmd_queue_cur_state, state); u8 move = TAP_MOVE(cmd_queue_cur_state, state);
if ((state != TAP_TLR) && (state == cmd_queue_cur_state)) if ((state != TAP_RESET) && (state == cmd_queue_cur_state))
return; return;
if(state==TAP_TLR) if(state==TAP_RESET)
{ {
jtag_add_tlr(); jtag_add_tlr();
return; return;
} }
for (i=0; i<7; i++) for (i=0; i<7; i++)
{ {
@ -135,7 +135,7 @@ int xsvf_read_xstates(int fd, enum tap_state *path, int max_path, int *path_len)
{ {
char c; char c;
unsigned char uc; unsigned char uc;
while ((read(fd, &c, 1) > 0) && (c == 0x12)) while ((read(fd, &c, 1) > 0) && (c == 0x12))
{ {
if (*path_len > max_path) if (*path_len > max_path)
@ -149,9 +149,9 @@ int xsvf_read_xstates(int fd, enum tap_state *path, int max_path, int *path_len)
} }
path[(*path_len)++] = xsvf_to_tap[uc]; path[(*path_len)++] = xsvf_to_tap[uc];
} }
lseek(fd, -1, SEEK_CUR); lseek(fd, -1, SEEK_CUR);
return ERROR_OK; return ERROR_OK;
} }
@ -166,9 +166,9 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
int do_abort = 0; int do_abort = 0;
int unsupported = 0; int unsupported = 0;
int tdo_mismatch = 0; int tdo_mismatch = 0;
int runtest_requires_tck = 0; int runtest_requires_tck = 0;
jtag_tap_t *tap = NULL; jtag_tap_t *tap = NULL;
/* use NULL to indicate a "plain" xsvf file which accounts for /* use NULL to indicate a "plain" xsvf file which accounts for
additional devices in the scan chain, otherwise the device additional devices in the scan chain, otherwise the device
@ -194,7 +194,7 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
command_print(cmd_ctx, "file %s not found", args[0]); command_print(cmd_ctx, "file %s not found", args[0]);
return ERROR_OK; return ERROR_OK;
} }
if ((argc > 2) && (strcmp(args[2], "virt2") == 0)) if ((argc > 2) && (strcmp(args[2], "virt2") == 0))
{ {
runtest_requires_tck = 1; runtest_requires_tck = 1;
@ -209,7 +209,7 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
if (jtag_execute_queue() != ERROR_OK) if (jtag_execute_queue() != ERROR_OK)
{ {
tdo_mismatch = 1; tdo_mismatch = 1;
break; break;
} }
break; break;
case 0x01: /* XTDOMASK */ case 0x01: /* XTDOMASK */
@ -239,9 +239,9 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
field.in_handler = NULL; field.in_handler = NULL;
field.in_handler_priv = NULL; field.in_handler_priv = NULL;
if (tap == NULL) if (tap == NULL)
jtag_add_plain_ir_scan(1, &field, TAP_PI); jtag_add_plain_ir_scan(1, &field, TAP_IRPAUSE);
else else
jtag_add_ir_scan(1, &field, TAP_PI); jtag_add_ir_scan(1, &field, TAP_IRPAUSE);
if (jtag_execute_queue() != ERROR_OK) if (jtag_execute_queue() != ERROR_OK)
{ {
tdo_mismatch = 1; tdo_mismatch = 1;
@ -254,7 +254,7 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
jtag_add_runtest(xruntest, xsvf_to_tap[xendir]); jtag_add_runtest(xruntest, xsvf_to_tap[xendir]);
else else
{ {
xsvf_add_statemove(TAP_RTI); xsvf_add_statemove(TAP_IDLE);
jtag_add_sleep(xruntest); jtag_add_sleep(xruntest);
xsvf_add_statemove(xsvf_to_tap[xendir]); xsvf_add_statemove(xsvf_to_tap[xendir]);
} }
@ -279,13 +279,13 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
field.in_value = NULL; field.in_value = NULL;
jtag_set_check_value(&field, dr_in_buf, dr_in_mask, NULL); jtag_set_check_value(&field, dr_in_buf, dr_in_mask, NULL);
if (tap == NULL) if (tap == NULL)
jtag_add_plain_dr_scan(1, &field, TAP_PD); jtag_add_plain_dr_scan(1, &field, TAP_DRPAUSE);
else else
jtag_add_dr_scan(1, &field, TAP_PD); jtag_add_dr_scan(1, &field, TAP_DRPAUSE);
if (jtag_execute_queue() != ERROR_OK) if (jtag_execute_queue() != ERROR_OK)
{ {
tdo_mismatch = 1; tdo_mismatch = 1;
break; break;
} }
if (xruntest) if (xruntest)
{ {
@ -293,7 +293,7 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
jtag_add_runtest(xruntest, xsvf_to_tap[xenddr]); jtag_add_runtest(xruntest, xsvf_to_tap[xenddr]);
else else
{ {
xsvf_add_statemove(TAP_RTI); xsvf_add_statemove(TAP_IDLE);
jtag_add_sleep(xruntest); jtag_add_sleep(xruntest);
xsvf_add_statemove(xsvf_to_tap[xenddr]); xsvf_add_statemove(xsvf_to_tap[xenddr]);
} }
@ -353,13 +353,13 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
field.in_value = NULL; field.in_value = NULL;
jtag_set_check_value(&field, dr_in_buf, dr_in_mask, NULL); jtag_set_check_value(&field, dr_in_buf, dr_in_mask, NULL);
if (tap == NULL) if (tap == NULL)
jtag_add_plain_dr_scan(1, &field, TAP_PD); jtag_add_plain_dr_scan(1, &field, TAP_DRPAUSE);
else else
jtag_add_dr_scan(1, &field, TAP_PD); jtag_add_dr_scan(1, &field, TAP_DRPAUSE);
if (jtag_execute_queue() != ERROR_OK) if (jtag_execute_queue() != ERROR_OK)
{ {
tdo_mismatch = 1; tdo_mismatch = 1;
break; break;
} }
if (xruntest) if (xruntest)
{ {
@ -367,7 +367,7 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
jtag_add_runtest(xruntest, xsvf_to_tap[xenddr]); jtag_add_runtest(xruntest, xsvf_to_tap[xenddr]);
else else
{ {
xsvf_add_statemove(TAP_RTI); xsvf_add_statemove(TAP_IDLE);
jtag_add_sleep(xruntest); jtag_add_sleep(xruntest);
xsvf_add_statemove(xsvf_to_tap[xenddr]); xsvf_add_statemove(xsvf_to_tap[xenddr]);
} }
@ -418,14 +418,14 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
{ {
int i,lasti; int i,lasti;
/* here the trick is that jtag_add_pathmove() must end in a stable /* here the trick is that jtag_add_pathmove() must end in a stable
state, so we must only invoke jtag_add_tlr() when we absolutely state, so we must only invoke jtag_add_tlr() when we absolutely
have to have to
*/ */
for(i=0,lasti=0;i<path_len;i++) for(i=0,lasti=0;i<path_len;i++)
{ {
if(path[i]==TAP_TLR) if(path[i]==TAP_RESET)
{ {
if(i>lasti) if(i>lasti)
{ {
jtag_add_pathmove(i-lasti,path+lasti); jtag_add_pathmove(i-lasti,path+lasti);
} }
@ -433,7 +433,7 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
jtag_add_tlr(); jtag_add_tlr();
} }
} }
if(i>=lasti) if(i>=lasti)
{ {
jtag_add_pathmove(i-lasti, path+lasti); jtag_add_pathmove(i-lasti, path+lasti);
} }
@ -536,7 +536,7 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
if (do_abort || unsupported || tdo_mismatch) if (do_abort || unsupported || tdo_mismatch)
break; break;
} }
if (tdo_mismatch) if (tdo_mismatch)
{ {
command_print(cmd_ctx, "TDO mismatch, aborting"); command_print(cmd_ctx, "TDO mismatch, aborting");
@ -554,18 +554,18 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
command_print(cmd_ctx, "premature end detected, aborting"); command_print(cmd_ctx, "premature end detected, aborting");
return ERROR_OK; return ERROR_OK;
} }
if (dr_out_buf) if (dr_out_buf)
free(dr_out_buf); free(dr_out_buf);
if (dr_in_buf) if (dr_in_buf)
free(dr_in_buf); free(dr_in_buf);
if (dr_in_mask) if (dr_in_mask)
free(dr_in_mask); free(dr_in_mask);
close(xsvf_fd); close(xsvf_fd);
command_print(cmd_ctx, "XSVF file programmed successfully"); command_print(cmd_ctx, "XSVF file programmed successfully");
return ERROR_OK; return ERROR_OK;