Add config files for STM32F7-DISCO and STM327[4|5]6G-EVAL.
Change-Id: I0803939f0ab1de97e544ca0f1257daac11fb50de Signed-off-by: Rémi PRUD'HOMME <prudhomme.remi@gmail.com> Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Reviewed-on: http://openocd.zylin.com/2754 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>__archive__
Rémi PRUD’HOMME
Freddie Chopin
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ed54838ea6
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# STM327[4|5]6G-EVAL: This is for the STM32F7 eval boards.
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# STM32746G-EVAL
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# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF261639
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# STM32756G-EVAL
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# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF261640
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# increase working area to 256KB
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set WORKAREASIZE 0x40000
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source [find target/stm32f7x.cfg]
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# This is an STM32F7 discovery board with a single STM32F756NGH6 chip.
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# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1848/PF261641
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# This is for using the onboard STLINK/V2-1
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source [find interface/stlink-v2-1.cfg]
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transport select hla_swd
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# increase working area to 256KB
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set WORKAREASIZE 0x40000
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source [find target/stm32f7x.cfg]
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# script for stm32f7x family
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#
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# stm32f7 devices support both JTAG and SWD transports.
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32f7x
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}
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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# By default use 128kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x20000
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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# See STM Document RM0385
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# Section 40.6.3 - corresponds to Cortex-M7 with FPU r0p0
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set _CPUTAPID 0x5ba00477
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} {
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set _CPUTAPID 0x5ba02477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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if { [info exists BSTAPID] } {
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set _BSTAPID $BSTAPID
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} else {
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# See STM Document RM0385
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# Section 40.6.1
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# STM32F75xxG
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set _BSTAPID1 0x06449071
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}
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if {[using_jtag]} {
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swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
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# adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
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adapter_khz 2000
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adapter_nsrst_delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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# use hardware reset, connect under reset
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reset_config srst_only srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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$_TARGETNAME configure -event examine-end {
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
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mmw 0xE0042004 0x00000007 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
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mww 0xE0042008 0x00001800
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}
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$_TARGETNAME configure -event trace-config {
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# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
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# change this value accordingly to configure trace pins
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# assignment
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mmw 0xE0042004 0x00000020 0
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}
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