- correct the register hi/lo read - wrong way round
- all the register now can be written to, including the special CP0 regs. git-svn-id: svn://svn.berlios.de/openocd/trunk@1169 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
ntfreak
parent
368daf44ff
commit
c0787b6994
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@ -66,7 +66,9 @@ typedef struct mips32_core_reg_s
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#define MIPS32_OP_LBU 0x24
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#define MIPS32_OP_LHU 0x25
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#define MIPS32_OP_MFHI 0x10
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#define MIPS32_OP_MTHI 0x11
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#define MIPS32_OP_MFLO 0x12
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#define MIPS32_OP_MTLO 0x13
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#define MIPS32_OP_SB 0x28
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#define MIPS32_OP_SH 0x29
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#define MIPS32_OP_SW 0x2B
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@ -90,8 +92,10 @@ typedef struct mips32_core_reg_s
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#define MIPS32_LHU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off)
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#define MIPS32_LUI(reg, val) MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val)
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#define MIPS32_LW(reg, off, base) MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)
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#define MIPS32_LO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
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#define MIPS32_HI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
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#define MIPS32_MFLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
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#define MIPS32_MFHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
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#define MIPS32_MTLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MTLO)
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#define MIPS32_MTHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MTHI)
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#define MIPS32_ORI(src, tar, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
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#define MIPS32_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
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#define MIPS32_SH(reg, off, base) MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)
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@ -258,10 +258,10 @@ int mips32_pracc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *
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MIPS32_B(NEG16(9)), /* b loop */
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MIPS32_NOP,
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/* end: */
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MIPS32_LW(11,0,15), /* sw $11,($15) */
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MIPS32_LW(10,0,15), /* sw $10,($15) */
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MIPS32_LW(9,0,15), /* sw $9,($15) */
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MIPS32_LW(8,0,15), /* sw $8,($15) */
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MIPS32_LW(11,0,15), /* lw $11,($15) */
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MIPS32_LW(10,0,15), /* lw $10,($15) */
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MIPS32_LW(9,0,15), /* lw $9,($15) */
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MIPS32_LW(8,0,15), /* lw $8,($15) */
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MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */
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MIPS32_NOP,
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MIPS32_B(NEG16(31)), /* b start */
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@ -331,10 +331,10 @@ int mips32_pracc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *
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MIPS32_B(NEG16(9)), /* b loop */
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MIPS32_NOP,
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MIPS32_LW(11,0,15), /* sw $11,($15) */
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MIPS32_LW(10,0,15), /* sw $10,($15) */
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MIPS32_LW(9,0,15), /* sw $9,($15) */
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MIPS32_LW(8,0,15), /* sw $8,($15) */
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MIPS32_LW(11,0,15), /* lw $11,($15) */
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MIPS32_LW(10,0,15), /* lw $10,($15) */
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MIPS32_LW(9,0,15), /* lw $9,($15) */
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MIPS32_LW(8,0,15), /* lw $8,($15) */
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MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */
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MIPS32_NOP,
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MIPS32_B(NEG16(31)), /* b start */
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@ -410,10 +410,10 @@ int mips32_pracc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *bu
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MIPS32_B(NEG16(9)), /* b loop */
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MIPS32_NOP,
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/* end: */
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MIPS32_LW(11,0,15), /* sw $11,($15) */
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MIPS32_LW(10,0,15), /* sw $10,($15) */
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MIPS32_LW(9,0,15), /* sw $9,($15) */
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MIPS32_LW(8,0,15), /* sw $8,($15) */
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MIPS32_LW(11,0,15), /* lw $11,($15) */
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MIPS32_LW(10,0,15), /* lw $10,($15) */
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MIPS32_LW(9,0,15), /* lw $9,($15) */
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MIPS32_LW(8,0,15), /* lw $8,($15) */
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MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */
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MIPS32_NOP,
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MIPS32_B(NEG16(31)), /* b start */
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@ -503,10 +503,10 @@ int mips32_pracc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32
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MIPS32_B(NEG16(9)), /* b loop */
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MIPS32_NOP,
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/* end: */
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MIPS32_LW(11,0,15), /* sw $11,($15) */
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MIPS32_LW(10,0,15), /* sw $10,($15) */
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MIPS32_LW(9,0,15), /* sw $9,($15) */
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MIPS32_LW(8,0,15), /* sw $8,($15) */
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MIPS32_LW(11,0,15), /* lw $11,($15) */
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MIPS32_LW(10,0,15), /* lw $10,($15) */
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MIPS32_LW(9,0,15), /* lw $9,($15) */
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MIPS32_LW(8,0,15), /* lw $8,($15) */
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MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */
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MIPS32_NOP,
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MIPS32_B(NEG16(30)), /* b start */
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@ -559,10 +559,10 @@ int mips32_pracc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16
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MIPS32_B(NEG16(9)), /* b loop */
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MIPS32_NOP,
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/* end: */
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MIPS32_LW(11,0,15), /* sw $11,($15) */
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MIPS32_LW(10,0,15), /* sw $10,($15) */
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MIPS32_LW(9,0,15), /* sw $9,($15) */
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MIPS32_LW(8,0,15), /* sw $8,($15) */
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MIPS32_LW(11,0,15), /* lw $11,($15) */
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MIPS32_LW(10,0,15), /* lw $10,($15) */
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MIPS32_LW(9,0,15), /* lw $9,($15) */
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MIPS32_LW(8,0,15), /* lw $8,($15) */
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MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */
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MIPS32_NOP,
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MIPS32_B(NEG16(30)), /* b start */
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@ -619,10 +619,10 @@ int mips32_pracc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *b
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MIPS32_B(NEG16(9)), /* b loop */
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MIPS32_NOP,
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/* end: */
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MIPS32_LW(11,0,15), /* sw $11,($15) */
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MIPS32_LW(10,0,15), /* sw $10,($15) */
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MIPS32_LW(9,0,15), /* sw $9,($15) */
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MIPS32_LW(8,0,15), /* sw $8,($15) */
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MIPS32_LW(11,0,15), /* lw $11,($15) */
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MIPS32_LW(10,0,15), /* lw $10,($15) */
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MIPS32_LW(9,0,15), /* lw $9,($15) */
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MIPS32_LW(8,0,15), /* lw $8,($15) */
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MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */
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MIPS32_NOP,
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MIPS32_B(NEG16(30)), /* b start */
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@ -649,21 +649,18 @@ int mips32_pracc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *b
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int mips32_pracc_write_regs(mips_ejtag_t *ejtag_info, u32 *regs)
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{
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/* TODO restore all core registers */
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u32 code[] = {
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/* start: */
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MIPS32_MTC0(2,31,0), /* move $2 to COP0 DeSave */
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MIPS32_LUI(2,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $2 = MIPS32_PRACC_PARAM_IN */
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MIPS32_ORI(2,2,LOWER16(MIPS32_PRACC_PARAM_IN)),
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/*MIPS32_LW(0,0*4,2),*/ /* lw $0,0*4($2) */
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MIPS32_LW(1,1*4,2), /* lw $1,1*4($2) */
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MIPS32_MFC0(2,31,0), /* move COP0 DeSave to $2 */
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MIPS32_MTC0(1,31,0), /* move $1 to COP0 DeSave */
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MIPS32_LW(15,15*4,2), /* lw $15,15*4($2) */
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MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */
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MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
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MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)),
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MIPS32_SW(1,0,15), /* sw $1,($15) */
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MIPS32_LUI(1,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $1 = MIPS32_PRACC_PARAM_IN */
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MIPS32_ORI(1,1,LOWER16(MIPS32_PRACC_PARAM_IN)),
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MIPS32_LW(2,2*4,1), /* lw $2,2*4($1) */
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MIPS32_LW(3,3*4,1), /* lw $3,3*4($1) */
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MIPS32_LW(4,4*4,1), /* lw $4,4*4($1) */
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MIPS32_LW(5,5*4,1), /* lw $5,5*4($1) */
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@ -676,7 +673,6 @@ int mips32_pracc_write_regs(mips_ejtag_t *ejtag_info, u32 *regs)
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MIPS32_LW(12,12*4,1), /* lw $12,12*4($1) */
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MIPS32_LW(13,13*4,1), /* lw $13,13*4($1) */
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MIPS32_LW(14,14*4,1), /* lw $14,14*4($1) */
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MIPS32_LW(15,15*4,1), /* lw $15,15*4($1) */
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MIPS32_LW(16,16*4,1), /* lw $16,16*4($1) */
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MIPS32_LW(17,17*4,1), /* lw $17,17*4($1) */
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MIPS32_LW(18,18*4,1), /* lw $18,18*4($1) */
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@ -694,16 +690,31 @@ int mips32_pracc_write_regs(mips_ejtag_t *ejtag_info, u32 *regs)
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MIPS32_LW(30,30*4,1), /* lw $30,30*4($1) */
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MIPS32_LW(31,31*4,1), /* lw $31,31*4($1) */
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MIPS32_MFC0(1,31,0), /* move COP0 DeSave to $1 */
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MIPS32_LW(2,32*4,1), /* lw $2,32*4($1) */
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MIPS32_MTC0(2,12,0), /* move $2 to status */
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MIPS32_LW(2,33*4,1), /* lw $2,33*4($1) */
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MIPS32_MTLO(2), /* move $2 to lo */
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MIPS32_LW(2,34*4,1), /* lw $2,34*4($1) */
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MIPS32_MTHI(2), /* move $2 to hi */
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MIPS32_LW(2,35*4,1), /* lw $2,35*4($1) */
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MIPS32_MTC0(2,8,0), /* move $2 to badvaddr */
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MIPS32_LW(2,36*4,1), /* lw $2,36*4($1) */
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MIPS32_MTC0(2,13,0), /* move $2 to cause*/
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MIPS32_LW(2,37*4,1), /* lw $2,37*4($1) */
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MIPS32_MTC0(2,24,0), /* move $2 to pc */
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MIPS32_LW(2,2*4,1), /* lw $2,2*4($1) */
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MIPS32_LW(1,0,15), /* lw $1,($15) */
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MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */
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MIPS32_NOP,
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MIPS32_B(NEG16(41)), /* b start */
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MIPS32_B(NEG16(55)), /* b start */
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MIPS32_NOP,
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};
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int retval;
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retval = mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \
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32, regs, 0, NULL, 1);
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38, regs, 0, NULL, 1);
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return retval;
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}
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@ -758,9 +769,9 @@ int mips32_pracc_read_regs(mips_ejtag_t *ejtag_info, u32 *regs)
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MIPS32_MFC0(2,12,0), /* move status to $2 */
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MIPS32_SW(2,32*4,1), /* sw $2,32*4($1) */
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MIPS32_LO(2), /* move lo to $2 */
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MIPS32_MFLO(2), /* move lo to $2 */
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MIPS32_SW(2,33*4,1), /* sw $2,33*4($1) */
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MIPS32_HI(2), /* move hi to $2 */
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MIPS32_MFHI(2), /* move hi to $2 */
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MIPS32_SW(2,34*4,1), /* sw $2,34*4($1) */
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MIPS32_MFC0(2,8,0), /* move badvaddr to $2 */
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MIPS32_SW(2,35*4,1), /* sw $2,35*4($1) */
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@ -769,8 +780,8 @@ int mips32_pracc_read_regs(mips_ejtag_t *ejtag_info, u32 *regs)
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MIPS32_MFC0(2,24,0), /* move pc to $2 */
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MIPS32_SW(2,37*4,1), /* sw $2,37*4($1) */
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MIPS32_LW(2,0,15), /* sw $2,($15) */
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MIPS32_LW(1,0,15), /* sw $1,($15) */
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MIPS32_LW(2,0,15), /* lw $2,($15) */
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MIPS32_LW(1,0,15), /* lw $1,($15) */
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MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */
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MIPS32_NOP,
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MIPS32_B(NEG16(60)), /* b start */
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@ -164,8 +164,8 @@ int mips_ejtag_step_disable(mips_ejtag_t *ejtag_info)
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MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */
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MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
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MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)),
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MIPS32_SW(1,0,15), /* sw $2,($15) */
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MIPS32_SW(2,0,15), /* sw $3,($15) */
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MIPS32_SW(1,0,15), /* sw $1,($15) */
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MIPS32_SW(2,0,15), /* sw $2,($15) */
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MIPS32_MFC0(1,23,0), /* move COP0 Debug to $1 */
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MIPS32_LUI(2,0xFFFF), /* $2 = 0xfffffeff */
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MIPS32_ORI(2,2,0xFEFF),
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@ -235,7 +235,7 @@ int mips_ejtag_read_debug(mips_ejtag_t *ejtag_info, u32* debug_reg)
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MIPS32_SW(2,0,15), /* sw $2,($15) */
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MIPS32_LUI(1,UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $1 = MIPS32_PRACC_PARAM_OUT */
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MIPS32_ORI(1,1,LOWER16(MIPS32_PRACC_PARAM_OUT)),
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MIPS32_MFC0(2,23,0), /* move COP0 Debug to $1 */
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MIPS32_MFC0(2,23,0), /* move COP0 Debug to $2 */
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MIPS32_SW(2,0,1),
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MIPS32_LW(2,0,15),
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MIPS32_LW(1,0,15),
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@ -139,6 +139,21 @@ int mips_m4k_poll(target_t *target)
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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/* clear this bit before handling polling
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* as after reset registers will read zero */
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if (ejtag_ctrl & EJTAG_CTRL_ROCC)
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{
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/* we have detected a reset, clear flag
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* otherwise ejtag will not work */
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jtag_add_end_state(TAP_RTI);
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ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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LOG_DEBUG("Reset Detected");
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}
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/* check for processor halted */
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if (ejtag_ctrl & EJTAG_CTRL_BRKST)
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{
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if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
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@ -168,18 +183,6 @@ int mips_m4k_poll(target_t *target)
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target->state = TARGET_RUNNING;
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}
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if (ejtag_ctrl & EJTAG_CTRL_ROCC)
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{
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/* we have detected a reset, clear flag
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* otherwise ejtag will not work */
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jtag_add_end_state(TAP_RTI);
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ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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LOG_DEBUG("Reset Detected");
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}
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// LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
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return ERROR_OK;
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@ -289,7 +292,6 @@ int mips_m4k_assert_reset(target_t *target)
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return retval;
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}
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return ERROR_OK;
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}
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