From bebdbe8b73b8d7cb2837687c0d38396fee0142fd Mon Sep 17 00:00:00 2001
From: Oleksij Rempel <linux@rempel-privat.de>
Date: Sat, 2 Dec 2017 19:55:11 +0100
Subject: [PATCH] tcl/target/atheros_ar9331: add documentation and extra
 helpers

Sync it with experience gathered on Qualcomm QCA4531 SoC. This
chips are in many ways similar.

Change-Id: I06b9c85e5985a09a9be3cb6cc0ce3b37695d2e54
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/4423
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
---
 tcl/target/atheros_ar9331.cfg | 92 ++++++++++++++++++++++++++++++++---
 1 file changed, 85 insertions(+), 7 deletions(-)

diff --git a/tcl/target/atheros_ar9331.cfg b/tcl/target/atheros_ar9331.cfg
index 290825f0c..bea37ed3c 100644
--- a/tcl/target/atheros_ar9331.cfg
+++ b/tcl/target/atheros_ar9331.cfg
@@ -1,20 +1,98 @@
+# The Atheros AR9331 is a highly integrated and cost effective
+# IEEE 802.11n 1x1 2.4 GHz System- on-a-Chip (SoC) for wireless
+# local area network (WLAN) AP and router platforms.
+#
+# Notes:
+# - MIPS Processor ID (PRId): 0x00019374
+# - 24Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache,
+#   operating at up to 400 MHz
+# - External 16-bit DDR1, DDR2, or SDRAM memory interface
+# - TRST is not available.
+# - EJTAG PrRst signal is not supported
+# - RESET_L pin A72 on the SoC will reset internal JTAG logic.
+#
+
+# Pins related for debug and bootstrap:
+# Name		Pin		Description
+#   JTAG
+# JTAG_TCK	GPIO0, (A27)	Software configurable, default JTAG
+# JTAG_TDI	GPIO6, (B46)	Software configurable, default JTAG
+# JTAG_TDO	GPIO7, (A54)	Software configurable, default JTAG
+# JTAG_TMS	GPIO8, (A52)	Software configurable, default JTAG
+#   Reset
+# RESET_L	-, (A72)	Input only
+# SYS_RST_L	????????	Output reset request or GPIO
+#   Bootstrap
+# MEM_TYPE[1]	GPIO28, (A74)	0 - SDRAM, 1 - DDR1 RAM, 2 - DDR2 RAM
+# MEM_TYPE[0]	GPIO12, (A56)
+# FW_DOWNLOAD	GPIO16, (A75)	Used if BOOT_FROM_SPI = 0. 0 - boot from USB
+#                               1 - boot from MDIO.
+# JTAG_MODE(JS)	GPIO11, (B48)	0 - JTAG (Default); 1 - EJTAG
+# BOOT_FROM_SPI	GPIO1, (A77)	0 - ROM boot; 1 - SPI boot
+# SEL_25M_40M	GPIO0, (A78)	0 - 25MHz; 1 - 40MHz
+#   UART
+# UART0_SOUT	GPIO10, (A79)
+# UART0_SIN	GPIO9, (B68)
+
+# Per default we need to use "none" variant to be able properly "reset init"
+# or "reset halt" the CPU.
+reset_config none srst_pulls_trst
+
+# For SRST based variant we still need proper timings.
+# For ETH part the reset should be asserted at least for 10ms
+# Since there is no other information let's take 100ms to be sure.
+adapter_nsrst_assert_width 100
+
+# according to the SoC documentation it should take at least 5ms from
+# reset end till bootstrap end. In the practice we need 8ms to get JTAG back
+# to live.
+adapter_nsrst_delay 8
+
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $_CHIPNAME
 } else {
 	set _CHIPNAME ar9331
 }
 
-if { [info exists CPUTAPID] } {
-	set _CPUTAPID $CPUTAPID
-} else {
-	set _CPUTAPID 0x00000001
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00000001
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
 
+# provide watchdog helper.
+proc disable_watchdog { } {
+	mww 0xb8060008 0x0
+}
+
+$_TARGETNAME configure -event halted { disable_watchdog }
+
+# Since PrRst is not supported and SRST will reset complete chip
+# with JTAG engine, we need to reset CPU from CPU itself.
+$_TARGETNAME configure -event reset-assert-pre {
+	halt
+}
+
+$_TARGETNAME configure -event reset-assert {
+	catch "mww 0xb806001C 0x01000000"
+}
+
+# To be able to trigger complete chip reset, in case JTAG is blocked
+# or CPU not responding, we still can use this helper.
+proc full_reset { } {
+	reset_config srst_only
+	reset
+	halt
+	reset_config none
+}
+
+proc disable_watchdog { } {
+	;# disable watchdog
+	mww 0xb8060008 0x0
+}
+
+$_TARGETNAME configure -event reset-end { disable_watchdog }
+
+# Section with helpers which can be used by boards
 proc ar9331_25mhz_pll_init {} {
 	mww 0xb8050008 0x00018004	;# bypass PLL; AHB_POST_DIV - ratio 4
 	mww 0xb8050004 0x00000352	;# 34000(ns)/40ns(25MHz) = 0x352 (850)