Kinetis: FlexNVM handling
FlexNVM (data flash) is memory mapped at 0x10000000. Driver used to send the same address to FTFx controller for erase/write ops. This was wrong as FTFx accepts only low 24 bits of address. To fix addressing for flash controller kinfo->prog_base was introduced. Added FlexNVM protection check, blank check and data flash size calculation. Blank check cannot use block operation on FlexNVM when EEPROM backup is enabled. Removed non functional reassign logic and bank_ordinal stuff. Now one can re-probe FlexNVM banks after nvm_partition change. Change-Id: Ia60b938266963e5d056701278cdf7bf2f62a429a Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/2987 Tested-by: jenkins__archive__
Tomas Vanek
Andreas Fritiofson
parent
50d4f76e13
commit
be6d14d1fb
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@ -83,6 +83,7 @@
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#define FTFx_FCNFG 0x40020001
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#define FTFx_FCCOB3 0x40020004
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#define FTFx_FPROT3 0x40020010
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#define FTFx_FDPROT 0x40020017
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#define SIM_SDID 0x40048024
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#define SIM_SOPT1 0x40047000
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#define SIM_FCFG1 0x4004804c
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@ -188,10 +189,13 @@
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#define KINETIS_SDID_FAMILYID_K7X 0x70000000
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struct kinetis_flash_bank {
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unsigned bank_ordinal;
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bool probed;
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uint32_t sector_size;
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uint32_t max_flash_prog_size;
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uint32_t protection_size;
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uint32_t prog_base; /* base address for FTFx operations */
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/* same as bank->base for pflash, differs for FlexNVM */
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uint32_t protection_block; /* number of first protection block in this bank */
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uint32_t sim_sdid;
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uint32_t sim_fcfg1;
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@ -703,7 +707,8 @@ static int kinetis_write_block(struct flash_bank *bank, const uint8_t *buffer,
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uint32_t buffer_size = 2048; /* Default minimum value */
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struct working_area *write_algorithm;
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struct working_area *source;
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uint32_t address = bank->base + offset;
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struct kinetis_flash_bank *kinfo = bank->driver_priv;
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uint32_t address = kinfo->prog_base + offset;
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struct reg_param reg_params[3];
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struct armv7m_algorithm armv7m_info;
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int retval = ERROR_OK;
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@ -814,6 +819,9 @@ static int kinetis_protect(struct flash_bank *bank, int set, int first, int last
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static int kinetis_protect_check(struct flash_bank *bank)
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{
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struct kinetis_flash_bank *kinfo = bank->driver_priv;
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int result;
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int i, b;
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uint32_t fprot, psec;
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if (bank->target->state != TARGET_HALTED) {
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LOG_ERROR("Target not halted");
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@ -821,10 +829,7 @@ static int kinetis_protect_check(struct flash_bank *bank)
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}
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if (kinfo->flash_class == FC_PFLASH) {
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int result;
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uint8_t buffer[4];
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uint32_t fprot, psec;
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int i, b;
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/* read protection register */
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result = target_read_memory(bank->target, FTFx_FPROT3, 1, 4, buffer);
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@ -833,13 +838,25 @@ static int kinetis_protect_check(struct flash_bank *bank)
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return result;
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fprot = target_buffer_get_u32(bank->target, buffer);
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/* Every bit protects 1/32 of the full flash (not necessarily just this bank) */
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/*
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* Every bit protects 1/32 of the full flash (not necessarily
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* just this bank), but we enforce the bank ordinals for
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* PFlash to start at zero.
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*/
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b = kinfo->bank_ordinal * (bank->size / kinfo->protection_size);
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} else if (kinfo->flash_class == FC_FLEX_NVM) {
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uint8_t fdprot;
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/* read protection register */
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result = target_read_memory(bank->target, FTFx_FDPROT, 1, 1, &fdprot);
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if (result != ERROR_OK)
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return result;
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fprot = fdprot;
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} else {
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LOG_ERROR("Protection checks for FlexRAM not supported");
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return ERROR_FLASH_BANK_INVALID;
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}
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b = kinfo->protection_block;
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for (psec = 0, i = 0; i < bank->num_sectors; i++) {
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if ((fprot >> b) & 1)
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bank->sectors[i].is_protected = 0;
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@ -853,10 +870,6 @@ static int kinetis_protect_check(struct flash_bank *bank)
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b++;
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}
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}
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} else {
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LOG_ERROR("Protection checks for FlexNVM not yet supported");
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return ERROR_FLASH_BANK_INVALID;
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}
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return ERROR_OK;
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}
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@ -955,6 +968,7 @@ COMMAND_HANDLER(kinetis_securing_test)
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static int kinetis_erase(struct flash_bank *bank, int first, int last)
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{
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int result, i;
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struct kinetis_flash_bank *kinfo = bank->driver_priv;
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if (bank->target->state != TARGET_HALTED) {
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LOG_ERROR("Target not halted");
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@ -972,7 +986,7 @@ static int kinetis_erase(struct flash_bank *bank, int first, int last)
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for (i = first; i <= last; i++) {
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uint8_t ftfx_fstat;
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/* set command and sector address */
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result = kinetis_ftfx_command(bank, FTFx_CMD_SECTERASE, bank->base + bank->sectors[i].offset,
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result = kinetis_ftfx_command(bank, FTFx_CMD_SECTERASE, kinfo->prog_base + bank->sectors[i].offset,
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0, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
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if (result != ERROR_OK) {
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@ -1112,7 +1126,7 @@ static int kinetis_write(struct flash_bank *bank, const uint8_t *buffer,
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}
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/* execute section-write command */
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result = kinetis_ftfx_command(bank, FTFx_CMD_SECTWRITE, bank->base + offset + i,
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result = kinetis_ftfx_command(bank, FTFx_CMD_SECTWRITE, kinfo->prog_base + offset + i,
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section_count>>8, section_count, 0, 0,
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0, 0, 0, 0, &ftfx_fstat);
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@ -1158,7 +1172,7 @@ static int kinetis_write(struct flash_bank *bank, const uint8_t *buffer,
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uint8_t padding[4] = {0xff, 0xff, 0xff, 0xff};
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memcpy(padding, buffer + i, MIN(4, count-i));
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result = kinetis_ftfx_command(bank, FTFx_CMD_LWORDPROG, bank->base + offset + i,
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result = kinetis_ftfx_command(bank, FTFx_CMD_LWORDPROG, kinfo->prog_base + offset + i,
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padding[3], padding[2], padding[1], padding[0],
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0, 0, 0, 0, &ftfx_fstat);
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@ -1178,13 +1192,16 @@ static int kinetis_read_part_info(struct flash_bank *bank)
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{
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int result, i;
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uint32_t offset = 0;
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uint8_t fcfg1_nvmsize, fcfg1_pfsize, fcfg1_eesize, fcfg2_pflsh;
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uint32_t nvm_size = 0, pf_size = 0, ee_size = 0;
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uint8_t fcfg1_nvmsize, fcfg1_pfsize, fcfg1_eesize, fcfg1_depart;
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uint8_t fcfg2_pflsh;
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uint32_t nvm_size = 0, pf_size = 0, df_size = 0, ee_size = 0;
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unsigned num_blocks = 0, num_pflash_blocks = 0, num_nvm_blocks = 0, first_nvm_bank = 0,
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reassign = 0, pflash_sector_size_bytes = 0, nvm_sector_size_bytes = 0;
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pflash_sector_size_bytes = 0, nvm_sector_size_bytes = 0;
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struct target *target = bank->target;
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struct kinetis_flash_bank *kinfo = bank->driver_priv;
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kinfo->probed = false;
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result = target_read_u32(target, SIM_SDID, &kinfo->sim_sdid);
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if (result != ERROR_OK)
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return result;
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@ -1358,7 +1375,6 @@ static int kinetis_read_part_info(struct flash_bank *bank)
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result = target_read_u32(target, SIM_FCFG2, &kinfo->sim_fcfg2);
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if (result != ERROR_OK)
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return result;
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fcfg2_pflsh = (kinfo->sim_fcfg2 >> 23) & 0x01;
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LOG_DEBUG("SDID: 0x%08" PRIX32 " FCFG1: 0x%08" PRIX32 " FCFG2: 0x%08" PRIX32, kinfo->sim_sdid,
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kinfo->sim_fcfg1, kinfo->sim_fcfg2);
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@ -1366,11 +1382,15 @@ static int kinetis_read_part_info(struct flash_bank *bank)
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fcfg1_nvmsize = (uint8_t)((kinfo->sim_fcfg1 >> 28) & 0x0f);
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fcfg1_pfsize = (uint8_t)((kinfo->sim_fcfg1 >> 24) & 0x0f);
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fcfg1_eesize = (uint8_t)((kinfo->sim_fcfg1 >> 16) & 0x0f);
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fcfg1_depart = (uint8_t)((kinfo->sim_fcfg1 >> 8) & 0x0f);
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fcfg2_pflsh = (uint8_t)((kinfo->sim_fcfg2 >> 23) & 0x01);
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/* when the PFLSH bit is set, there is no FlexNVM/FlexRAM */
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if (!fcfg2_pflsh) {
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switch (fcfg1_nvmsize) {
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case 0x03:
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case 0x05:
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case 0x07:
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case 0x09:
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case 0x0b:
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@ -1405,6 +1425,30 @@ static int kinetis_read_part_info(struct flash_bank *bank)
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ee_size = 0;
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break;
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}
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switch (fcfg1_depart) {
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case 0x01:
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case 0x02:
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case 0x03:
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case 0x04:
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case 0x05:
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case 0x06:
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df_size = nvm_size - (4096 << fcfg1_depart);
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break;
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case 0x08:
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df_size = 0;
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break;
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case 0x09:
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case 0x0a:
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case 0x0b:
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case 0x0c:
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case 0x0d:
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df_size = 4096 << (fcfg1_depart & 0x7);
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break;
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default:
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df_size = nvm_size;
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break;
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}
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}
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switch (fcfg1_pfsize) {
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@ -1439,101 +1483,52 @@ static int kinetis_read_part_info(struct flash_bank *bank)
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LOG_DEBUG("%d blocks total: %d PFlash, %d FlexNVM",
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num_blocks, num_pflash_blocks, num_nvm_blocks);
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/*
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* If the flash class is already assigned, verify the
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* parameters.
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*/
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if (kinfo->flash_class != FC_AUTO) {
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if (kinfo->bank_ordinal != (unsigned) bank->bank_number) {
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LOG_WARNING("Flash ordinal/bank number mismatch");
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reassign = 1;
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} else {
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switch (kinfo->flash_class) {
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case FC_PFLASH:
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if (kinfo->bank_ordinal >= first_nvm_bank) {
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LOG_WARNING("Class mismatch, bank %d is not PFlash", bank->bank_number);
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reassign = 1;
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} else if (bank->size != (pf_size / num_pflash_blocks)) {
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LOG_WARNING("PFlash size mismatch");
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reassign = 1;
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} else if (bank->base !=
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(0x00000000 + bank->size * kinfo->bank_ordinal)) {
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LOG_WARNING("PFlash address range mismatch");
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reassign = 1;
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} else if (kinfo->sector_size != pflash_sector_size_bytes) {
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LOG_WARNING("PFlash sector size mismatch");
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reassign = 1;
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} else {
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LOG_DEBUG("PFlash bank %d already configured okay",
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kinfo->bank_ordinal);
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}
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break;
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case FC_FLEX_NVM:
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if ((kinfo->bank_ordinal >= num_blocks) ||
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(kinfo->bank_ordinal < first_nvm_bank)) {
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LOG_WARNING("Class mismatch, bank %d is not FlexNVM", bank->bank_number);
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reassign = 1;
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} else if (bank->size != (nvm_size / num_nvm_blocks)) {
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LOG_WARNING("FlexNVM size mismatch");
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reassign = 1;
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} else if (bank->base !=
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(0x10000000 + bank->size * kinfo->bank_ordinal)) {
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LOG_WARNING("FlexNVM address range mismatch");
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reassign = 1;
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} else if (kinfo->sector_size != nvm_sector_size_bytes) {
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LOG_WARNING("FlexNVM sector size mismatch");
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reassign = 1;
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} else {
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LOG_DEBUG("FlexNVM bank %d already configured okay",
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kinfo->bank_ordinal);
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}
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break;
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case FC_FLEX_RAM:
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if (kinfo->bank_ordinal != num_blocks) {
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LOG_WARNING("Class mismatch, bank %d is not FlexRAM", bank->bank_number);
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reassign = 1;
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} else if (bank->size != ee_size) {
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LOG_WARNING("FlexRAM size mismatch");
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reassign = 1;
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} else if (bank->base != FLEXRAM) {
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LOG_WARNING("FlexRAM address mismatch");
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reassign = 1;
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} else if (kinfo->sector_size != nvm_sector_size_bytes) {
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LOG_WARNING("FlexRAM sector size mismatch");
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reassign = 1;
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} else {
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LOG_DEBUG("FlexRAM bank %d already configured okay", kinfo->bank_ordinal);
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}
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break;
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default:
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LOG_WARNING("Unknown or inconsistent flash class");
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reassign = 1;
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break;
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}
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}
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} else {
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LOG_INFO("Probing flash info for bank %d", bank->bank_number);
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reassign = 1;
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}
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if (!reassign)
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return ERROR_OK;
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if ((unsigned)bank->bank_number < num_pflash_blocks) {
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/* pflash, banks start at address zero */
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kinfo->flash_class = FC_PFLASH;
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bank->size = (pf_size / num_pflash_blocks);
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bank->base = 0x00000000 + bank->size * bank->bank_number;
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kinfo->prog_base = bank->base;
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kinfo->sector_size = pflash_sector_size_bytes;
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kinfo->protection_size = pf_size / 32;
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kinfo->protection_block = (32 / num_pflash_blocks) * bank->bank_number;
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} else if ((unsigned)bank->bank_number < num_blocks) {
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/* nvm, banks start at address 0x10000000 */
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unsigned nvm_ord = bank->bank_number - first_nvm_bank;
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uint32_t limit;
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kinfo->flash_class = FC_FLEX_NVM;
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bank->size = (nvm_size / num_nvm_blocks);
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bank->base = 0x10000000 + bank->size * (bank->bank_number - first_nvm_bank);
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bank->base = 0x10000000 + bank->size * nvm_ord;
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kinfo->prog_base = 0x00800000 + bank->size * nvm_ord;
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kinfo->sector_size = nvm_sector_size_bytes;
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kinfo->protection_size = 0; /* FIXME: TODO: depends on DEPART bits, chip */
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if (df_size == 0) {
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kinfo->protection_size = 0;
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} else {
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for (i = df_size; ~i & 1; i >>= 1)
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;
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if (i == 1)
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kinfo->protection_size = df_size / 8; /* data flash size = 2^^n */
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else
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kinfo->protection_size = nvm_size / 8; /* TODO: verify on SF1, not documented in RM */
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}
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kinfo->protection_block = (8 / num_nvm_blocks) * nvm_ord;
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/* EEPROM backup part of FlexNVM is not accessible, use df_size as a limit */
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if (df_size > bank->size * nvm_ord)
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limit = df_size - bank->size * nvm_ord;
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else
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limit = 0;
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if (bank->size > limit) {
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bank->size = limit;
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LOG_DEBUG("FlexNVM bank %d limited to 0x%08" PRIx32 " due to active EEPROM backup",
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bank->bank_number, limit);
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}
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} else if ((unsigned)bank->bank_number == num_blocks) {
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LOG_ERROR("FlexRAM support not yet implemented");
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return ERROR_FLASH_OPER_UNSUPPORTED;
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@ -1560,7 +1555,9 @@ static int kinetis_read_part_info(struct flash_bank *bank)
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}
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bank->num_sectors = bank->size / kinfo->sector_size;
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assert(bank->num_sectors > 0);
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if (bank->num_sectors > 0) {
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/* FlexNVM bank can be used for EEPROM backup therefore zero sized */
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bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
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for (i = 0; i < bank->num_sectors; i++) {
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@ -1570,6 +1567,9 @@ static int kinetis_read_part_info(struct flash_bank *bank)
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bank->sectors[i].is_erased = -1;
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bank->sectors[i].is_protected = 1;
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}
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}
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kinfo->probed = true;
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return ERROR_OK;
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}
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@ -1588,7 +1588,7 @@ static int kinetis_auto_probe(struct flash_bank *bank)
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{
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struct kinetis_flash_bank *kinfo = bank->driver_priv;
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if (kinfo->sim_sdid)
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if (kinfo && kinfo->probed)
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return ERROR_OK;
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return kinetis_probe(bank);
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@ -1619,22 +1619,33 @@ static int kinetis_blank_check(struct flash_bank *bank)
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return ERROR_TARGET_NOT_HALTED;
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}
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if (kinfo->flash_class == FC_PFLASH) {
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if (kinfo->flash_class == FC_PFLASH || kinfo->flash_class == FC_FLEX_NVM) {
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int result;
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bool block_dirty = false;
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uint8_t ftfx_fstat;
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if (kinfo->flash_class == FC_FLEX_NVM) {
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uint8_t fcfg1_depart = (uint8_t)((kinfo->sim_fcfg1 >> 8) & 0x0f);
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/* block operation cannot be used on FlexNVM when EEPROM backup partition is set */
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if (fcfg1_depart != 0xf && fcfg1_depart != 0)
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block_dirty = true;
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}
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if (!block_dirty) {
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/* check if whole bank is blank */
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||||
result = kinetis_ftfx_command(bank, FTFx_CMD_BLOCKSTAT, bank->base, 0, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
|
||||
result = kinetis_ftfx_command(bank, FTFx_CMD_BLOCKSTAT, kinfo->prog_base,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
|
||||
|
||||
if (result != ERROR_OK)
|
||||
return result;
|
||||
if (result != ERROR_OK || (ftfx_fstat & 0x01))
|
||||
block_dirty = true;
|
||||
}
|
||||
|
||||
if (ftfx_fstat & 0x01) {
|
||||
if (block_dirty) {
|
||||
/* the whole bank is not erased, check sector-by-sector */
|
||||
int i;
|
||||
for (i = 0; i < bank->num_sectors; i++) {
|
||||
/* normal margin */
|
||||
result = kinetis_ftfx_command(bank, FTFx_CMD_SECTSTAT, bank->base + bank->sectors[i].offset,
|
||||
result = kinetis_ftfx_command(bank, FTFx_CMD_SECTSTAT, kinfo->prog_base + bank->sectors[i].offset,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
|
||||
|
||||
if (result == ERROR_OK) {
|
||||
|
|
@ -1651,7 +1662,7 @@ static int kinetis_blank_check(struct flash_bank *bank)
|
|||
bank->sectors[i].is_erased = 1;
|
||||
}
|
||||
} else {
|
||||
LOG_WARNING("kinetis_blank_check not supported yet for FlexNVM");
|
||||
LOG_WARNING("kinetis_blank_check not supported yet for FlexRAM");
|
||||
return ERROR_FLASH_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue