ARM: rework "arm reg" output for new mode
Change the layout to show the "Secure Monitor" registers too, when they're present. Instead of lining registers for each of six (or seven) modes up in adjacent vertical columns, display each mode's registers (or shadows) in a single block, avoiding duplicate value displays. This also lets us shrink the line length to fits in standard 80 character lines ... six or seven 18-character columns can't fit. Relabel "r13" as "sp", so it's more meaningful. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>__archive__
David Brownell
parent
f0c9e89e1a
commit
bd9d05e14b
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@ -39,26 +39,59 @@
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static const char *armv4_5_core_reg_list[] =
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{
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc",
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"r8", "r9", "r10", "r11", "r12", "sp_usr", "lr_usr", "pc",
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"r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "r13_fiq", "lr_fiq",
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"r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq", "lr_fiq",
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"r13_irq", "lr_irq",
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"sp_irq", "lr_irq",
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"r13_svc", "lr_svc",
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"sp_svc", "lr_svc",
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"r13_abt", "lr_abt",
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"sp_abt", "lr_abt",
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"r13_und", "lr_und",
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"sp_und", "lr_und",
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"cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und",
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"r13_mon", "lr_mon", "spsr_mon",
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"sp_mon", "lr_mon", "spsr_mon",
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};
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static const uint8_t arm_usr_indices[17] = {
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
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};
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static const uint8_t arm_fiq_indices[8] = {
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16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ,
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};
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static const uint8_t arm_irq_indices[3] = {
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23, 24, ARMV4_5_SPSR_IRQ,
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};
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static const uint8_t arm_svc_indices[3] = {
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25, 26, ARMV4_5_SPSR_SVC,
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};
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static const uint8_t arm_abt_indices[3] = {
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27, 28, ARMV4_5_SPSR_ABT,
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};
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static const uint8_t arm_und_indices[3] = {
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29, 30, ARMV4_5_SPSR_UND,
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};
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static const uint8_t arm_mon_indices[3] = {
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37, 38, ARM_SPSR_MON,
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};
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static const struct {
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const char *name;
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unsigned psr;
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unsigned short psr;
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/* For user and system modes, these list indices for all registers.
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* otherwise they're just indices for the shadow registers and SPSR.
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*/
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unsigned short n_indices;
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const uint8_t *indices;
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} arm_mode_data[] = {
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/* Seven modes are standard from ARM7 on. "System" and "User" share
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* the same registers; other modes shadow from 3 to 8 registers.
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@ -66,30 +99,44 @@ static const struct {
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{
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.name = "User",
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.psr = ARMV4_5_MODE_USR,
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.n_indices = ARRAY_SIZE(arm_usr_indices),
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.indices = arm_usr_indices,
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},
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{
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.name = "FIQ",
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.psr = ARMV4_5_MODE_FIQ,
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.n_indices = ARRAY_SIZE(arm_fiq_indices),
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.indices = arm_fiq_indices,
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},
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{
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.name = "Supervisor",
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.psr = ARMV4_5_MODE_SVC,
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.n_indices = ARRAY_SIZE(arm_svc_indices),
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.indices = arm_svc_indices,
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},
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{
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.name = "Abort",
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.psr = ARMV4_5_MODE_ABT,
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.n_indices = ARRAY_SIZE(arm_abt_indices),
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.indices = arm_abt_indices,
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},
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{
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.name = "IRQ",
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.psr = ARMV4_5_MODE_IRQ,
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.n_indices = ARRAY_SIZE(arm_irq_indices),
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.indices = arm_irq_indices,
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},
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{
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.name = "Undefined" /* instruction */,
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.name = "Undefined instruction",
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.psr = ARMV4_5_MODE_UND,
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.n_indices = ARRAY_SIZE(arm_und_indices),
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.indices = arm_und_indices,
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},
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{
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.name = "System",
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.psr = ARMV4_5_MODE_SYS,
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.n_indices = ARRAY_SIZE(arm_usr_indices),
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.indices = arm_usr_indices,
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},
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/* TrustZone "Security Extensions" add a secure monitor mode.
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* This is distinct from a "debug monitor" which can support
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@ -98,6 +145,8 @@ static const struct {
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{
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.name = "Secure Monitor",
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.psr = ARM_MODE_MON,
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.n_indices = ARRAY_SIZE(arm_mon_indices),
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.indices = arm_mon_indices,
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},
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};
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@ -461,11 +510,10 @@ int armv4_5_arch_state(struct target *target)
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COMMAND_HANDLER(handle_armv4_5_reg_command)
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{
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char output[128];
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int output_len;
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int mode, num;
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struct target *target = get_current_target(CMD_CTX);
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struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
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unsigned num_regs;
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struct reg *regs;
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if (!is_arm(armv4_5))
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{
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@ -476,7 +524,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
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if (target->state != TARGET_HALTED)
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{
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command_print(CMD_CTX, "error: target must be halted for register accesses");
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return ERROR_OK;
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return ERROR_FAIL;
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}
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if (!is_arm_mode(armv4_5->core_mode))
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@ -488,31 +536,61 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
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return ERROR_FAIL;
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}
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for (num = 0; num <= 15; num++)
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{
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output_len = 0;
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for (mode = 0; mode < 6; mode++)
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{
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if (!ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).valid)
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{
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armv4_5->full_context(target);
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}
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output_len += snprintf(output + output_len,
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128 - output_len,
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"%8s: %8.8" PRIx32 " ",
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ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name,
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buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32));
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num_regs = armv4_5->core_cache->num_regs;
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regs = armv4_5->core_cache->reg_list;
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for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
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const char *name;
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char *sep = "\n";
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char *shadow = "";
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/* label this bank of registers (or shadows) */
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switch (arm_mode_data[mode].psr) {
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case ARMV4_5_MODE_SYS:
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continue;
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case ARMV4_5_MODE_USR:
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name = "System and User";
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sep = "";
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break;
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case ARM_MODE_MON:
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if (armv4_5->core_type != ARM_MODE_MON)
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continue;
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/* FALLTHROUGH */
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default:
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name = arm_mode_data[mode].name;
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shadow = "shadow ";
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break;
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}
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command_print(CMD_CTX, "%s%s mode %sregisters",
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sep, name, shadow);
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/* display N rows of up to 4 registers each */
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for (unsigned i = 0; i < arm_mode_data[mode].n_indices;) {
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char output[80];
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int output_len = 0;
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for (unsigned j = 0; j < 4; j++, i++) {
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uint32_t value;
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struct reg *reg = regs;
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if (i >= arm_mode_data[mode].n_indices)
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break;
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reg += arm_mode_data[mode].indices[i];
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/* REVISIT be smarter about faults... */
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if (!reg->valid)
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armv4_5->full_context(target);
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value = buf_get_u32(reg->value, 0, 32);
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output_len += snprintf(output + output_len,
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sizeof(output) - output_len,
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"%8s: %8.8" PRIx32 " ",
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reg->name, value);
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}
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command_print(CMD_CTX, "%s", output);
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}
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command_print(CMD_CTX, "%s", output);
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}
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command_print(CMD_CTX,
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" cpsr: %8.8" PRIx32 " spsr_fiq: %8.8" PRIx32 " spsr_irq: %8.8" PRIx32 " spsr_svc: %8.8" PRIx32 " spsr_abt: %8.8" PRIx32 " spsr_und: %8.8" PRIx32 "",
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buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
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buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_FIQ].value, 0, 32),
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buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_IRQ].value, 0, 32),
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buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_SVC].value, 0, 32),
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buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_ABT].value, 0, 32),
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buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_UND].value, 0, 32));
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return ERROR_OK;
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}
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