parent
eaabf76fde
commit
bd7d75d4b9
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@ -3001,7 +3001,7 @@ bool riscv_has_register(struct target *target, int hartid, int regid)
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return 1;
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return 1;
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}
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}
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/**
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/**
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* If write is true:
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* If write is true:
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* return true iff we are guaranteed that the register will contain exactly
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* return true iff we are guaranteed that the register will contain exactly
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* the value we just wrote when it's read.
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* the value we just wrote when it's read.
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@ -3035,7 +3035,7 @@ static bool gdb_regno_cacheable(enum gdb_regno regno, bool write)
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case GDB_REGNO_MEPC:
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case GDB_REGNO_MEPC:
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case GDB_REGNO_MCAUSE:
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case GDB_REGNO_MCAUSE:
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case GDB_REGNO_SATP:
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case GDB_REGNO_SATP:
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/*
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/*
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* WARL registers might not contain the value we just wrote, but
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* WARL registers might not contain the value we just wrote, but
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* these ones won't spontaneously change their value either. *
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* these ones won't spontaneously change their value either. *
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*/
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*/
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