diff --git a/doc/openocd.texi b/doc/openocd.texi
index e5781a118..14dec6d21 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4612,10 +4612,12 @@ The target may later be resumed in the currently set core_state.
 that is not currently supported in OpenOCD.)
 @end deffn
 
-@deffn Command {armv4_5 disassemble} address count [thumb]
+@deffn Command {armv4_5 disassemble} address [count [@option{thumb}]]
 @cindex disassemble
 Disassembles @var{count} instructions starting at @var{address}.
-If @option{thumb} is specified, Thumb (16-bit) instructions are used;
+If @var{count} is not specified, a single instruction is disassembled.
+If @option{thumb} is specified, or the low bit of the address is set,
+Thumb (16-bit) instructions are used;
 else ARM (32-bit) instructions are used.
 (Processors may also support the Jazelle state, but
 those instructions are not currently understood by OpenOCD.)
@@ -5086,9 +5088,10 @@ If @var{value} is defined, first assigns that.
 @subsection Cortex-M3 specific commands
 @cindex Cortex-M3
 
-@deffn Command {cortex_m3 disassemble} address count
+@deffn Command {cortex_m3 disassemble} address [count]
 @cindex disassemble
 Disassembles @var{count} Thumb2 instructions starting at @var{address}.
+If @var{count} is not specified, a single instruction is disassembled.
 @end deffn
 
 @deffn Command {cortex_m3 maskisr} (@option{on}|@option{off})
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 9861843ea..9f9aa2f5f 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -387,13 +387,15 @@ int handle_armv4_5_core_state_command(struct command_context_s *cmd_ctx, char *c
 	return ERROR_OK;
 }
 
-int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int
+handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	int retval = ERROR_OK;
 	target_t *target = get_current_target(cmd_ctx);
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	uint32_t address;
-	int count;
+	int count = 1;
 	int i;
 	arm_instruction_t cur_instruction;
 	uint32_t opcode;
@@ -406,19 +408,32 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *
 		return ERROR_OK;
 	}
 
-	if (argc < 2)
-	{
-		command_print(cmd_ctx, "usage: armv4_5 disassemble <address> <count> ['thumb']");
+	switch (argc) {
+	case 3:
+		if (strcmp(args[2], "thumb") != 0)
+			goto usage;
+		thumb = 1;
+		/* FALL THROUGH */
+	case 2:
+		count = strtoul(args[1], NULL, 0);
+		/* FALL THROUGH */
+	case 1:
+		address = strtoul(args[0], NULL, 0);
+		if (address & 0x01) {
+			if (!thumb) {
+				command_print(cmd_ctx, "Disassemble as Thumb");
+				thumb = 1;
+			}
+			address &= ~1;
+		}
+		break;
+	default:
+usage:
+		command_print(cmd_ctx,
+			"usage: armv4_5 disassemble <address> [<count> ['thumb']]");
 		return ERROR_OK;
 	}
 
-	address = strtoul(args[0], NULL, 0);
-	count = strtoul(args[1], NULL, 0);
-
-	if (argc >= 3)
-		if (strcmp(args[2], "thumb") == 0)
-			thumb = 1;
-
 	for (i = 0; i < count; i++)
 	{
 		if (thumb)
@@ -453,12 +468,20 @@ int armv4_5_register_commands(struct command_context_s *cmd_ctx)
 {
 	command_t *armv4_5_cmd;
 
-	armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5", NULL, COMMAND_ANY, "armv4/5 specific commands");
+	armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5",
+			NULL, COMMAND_ANY,
+			"armv4/5 specific commands");
 
-	register_command(cmd_ctx, armv4_5_cmd, "reg", handle_armv4_5_reg_command, COMMAND_EXEC, "display ARM core registers");
-	register_command(cmd_ctx, armv4_5_cmd, "core_state", handle_armv4_5_core_state_command, COMMAND_EXEC, "display/change ARM core state <arm | thumb>");
+	register_command(cmd_ctx, armv4_5_cmd, "reg",
+			handle_armv4_5_reg_command, COMMAND_EXEC,
+			"display ARM core registers");
+	register_command(cmd_ctx, armv4_5_cmd, "core_state",
+			handle_armv4_5_core_state_command, COMMAND_EXEC,
+			"display/change ARM core state <arm | thumb>");
+	register_command(cmd_ctx, armv4_5_cmd, "disassemble",
+			handle_armv4_5_disassemble_command, COMMAND_EXEC,
+			"disassemble instructions <address> [<count> ['thumb']]");
 
-	register_command(cmd_ctx, armv4_5_cmd, "disassemble", handle_armv4_5_disassemble_command, COMMAND_EXEC, "disassemble instructions <address> <count> ['thumb']");
 	return ERROR_OK;
 }
 
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index ea20dfd14..df00fc19e 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -1702,23 +1702,27 @@ handle_cortex_m3_disassemble_command(struct command_context_s *cmd_ctx,
 	int retval = ERROR_OK;
 	target_t *target = get_current_target(cmd_ctx);
 	uint32_t address;
-	unsigned long count;
+	unsigned long count = 1;
 	arm_instruction_t cur_instruction;
 
-	if (argc != 2) {
+	errno = 0;
+	switch (argc) {
+	case 2:
+		count = strtoul(args[1], NULL, 0);
+		if (errno)
+			return ERROR_FAIL;
+		/* FALL THROUGH */
+	case 1:
+		address = strtoul(args[0], NULL, 0);
+		if (errno)
+			return ERROR_FAIL;
+		break;
+	default:
 		command_print(cmd_ctx,
-			"usage: cortex_m3 disassemble <address> <count>");
+			"usage: cortex_m3 disassemble <address> [<count>]");
 		return ERROR_OK;
 	}
 
-	errno = 0;
-	address = strtoul(args[0], NULL, 0);
-	if (errno)
-		return ERROR_FAIL;
-	count = strtoul(args[1], NULL, 0);
-	if (errno)
-		return ERROR_FAIL;
-
 	while (count--) {
 		retval = thumb2_opcode(target, address, &cur_instruction);
 		if (retval != ERROR_OK)
@@ -1809,7 +1813,7 @@ int cortex_m3_register_commands(struct command_context_s *cmd_ctx)
 
 	register_command(cmd_ctx, cortex_m3_cmd, "disassemble",
 			handle_cortex_m3_disassemble_command, COMMAND_EXEC,
-			"disassemble Thumb2 instructions <address> <count>");
+			"disassemble Thumb2 instructions <address> [<count>]");
 	register_command(cmd_ctx, cortex_m3_cmd, "maskisr",
 			handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC,
 			"mask cortex_m3 interrupts ['on'|'off']");