nrf51: Add UICR writing support
SoftDevice stack ihex binary, provided by Nordic expects being able to write data necessary for its correct operation at the adresses inside UICR. This patch exposes UICR region of flash as a second bank on the MCU to facilitate that. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Change-Id: Idbc140b8de027f60655f78043877b7c054eb06f9 Reviewed-on: http://openocd.zylin.com/2013 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>__archive__
Andrey Smirnov
Paul Fertser
parent
c619f74ca4
commit
ba66b4c594
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@ -73,6 +73,8 @@ enum nrf51_uicr_registers {
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NRF51_UICR_BASE = 0x10001000, /* User Information
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* Configuration Regsters */
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NRF51_UICR_SIZE = 252,
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#define NRF51_UICR_REG(offset) (NRF51_UICR_BASE + offset)
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NRF51_UICR_CLENR0 = NRF51_UICR_REG(0x000),
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@ -105,7 +107,12 @@ struct nrf51_info {
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uint32_t code_page_size;
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uint32_t code_memory_size;
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bool probed;
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struct {
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bool probed;
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int (*write) (struct flash_bank *bank,
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struct nrf51_info *chip,
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const uint8_t *buffer, uint32_t offset, uint32_t count);
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} bank[2];
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struct target *target;
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};
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@ -194,6 +201,14 @@ static const struct nrf51_device_spec nrf51_known_devices_table[] = {
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};
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static int nrf51_bank_is_probed(struct flash_bank *bank)
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{
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struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
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assert(chip != NULL);
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return chip->bank[bank->bank_number].probed;
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}
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static int nrf51_probe(struct flash_bank *bank);
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static int nrf51_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf51_info **chip)
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@ -205,10 +220,13 @@ static int nrf51_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf51
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*chip = (struct nrf51_info *)bank->driver_priv;
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if (!(*chip)->probed)
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int probed = nrf51_bank_is_probed(bank);
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if (probed < 0)
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return probed;
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else if (!probed)
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return nrf51_probe(bank);
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return ERROR_OK;
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else
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return ERROR_OK;
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}
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static int nrf51_wait_for_nvmc(struct nrf51_info *chip)
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@ -335,6 +353,10 @@ static int nrf51_protect_check(struct flash_bank *bank)
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int res;
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uint32_t clenr0;
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/* UICR cannot be write protected so just return early */
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if (bank->base == NRF51_UICR_BASE)
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return ERROR_OK;
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struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
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assert(chip != NULL);
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@ -368,6 +390,10 @@ static int nrf51_protect(struct flash_bank *bank, int set, int first, int last)
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uint32_t clenr0, ppfc;
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struct nrf51_info *chip;
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/* UICR cannot be write protected so just bail out early */
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if (bank->base == NRF51_UICR_BASE)
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return ERROR_FAIL;
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res = nrf51_get_probed_chip_if_halted(bank, &chip);
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if (res != ERROR_OK)
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return res;
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@ -419,7 +445,6 @@ static int nrf51_probe(struct flash_bank *bank)
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int res;
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struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
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res = target_read_u32(chip->target, NRF51_FICR_CONFIGID, &hwid);
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if (res != ERROR_OK) {
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LOG_ERROR("Couldn't read CONFIGID register");
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@ -436,65 +461,87 @@ static int nrf51_probe(struct flash_bank *bank)
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break;
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}
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if (spec) {
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LOG_INFO("nRF51822-%s(build code: %s) %ukB Flash",
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spec->variant, spec->build_code, spec->flash_size_kb);
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if (!chip->bank[0].probed && !chip->bank[1].probed) {
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if (spec)
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LOG_INFO("nRF51822-%s(build code: %s) %ukB Flash",
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spec->variant, spec->build_code, spec->flash_size_kb);
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else
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LOG_WARNING("Unknown device (HWID 0x%08" PRIx32 ")", hwid);
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}
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if (bank->base == NRF51_FLASH_BASE) {
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res = target_read_u32(chip->target, NRF51_FICR_CODEPAGESIZE,
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&chip->code_page_size);
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if (res != ERROR_OK) {
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LOG_ERROR("Couldn't read code page size");
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return res;
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}
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res = target_read_u32(chip->target, NRF51_FICR_CODESIZE,
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&chip->code_memory_size);
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if (res != ERROR_OK) {
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LOG_ERROR("Couldn't read code memory size");
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return res;
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}
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if (spec && chip->code_memory_size != spec->flash_size_kb) {
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LOG_ERROR("Chip's reported Flash capacity does not match expected one");
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return ERROR_FAIL;
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}
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bank->size = chip->code_memory_size * 1024;
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bank->num_sectors = bank->size / chip->code_page_size;
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bank->sectors = calloc(bank->num_sectors,
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sizeof((bank->sectors)[0]));
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if (!bank->sectors)
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return ERROR_FLASH_BANK_NOT_PROBED;
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/* Fill out the sector information: all NRF51 sectors are the same size and
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* there is always a fixed number of them. */
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for (int i = 0; i < bank->num_sectors; i++) {
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bank->sectors[i].size = chip->code_page_size;
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bank->sectors[i].offset = i * chip->code_page_size;
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/* mark as unknown */
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bank->sectors[i].is_erased = -1;
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bank->sectors[i].is_protected = -1;
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}
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nrf51_protect_check(bank);
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chip->bank[0].probed = true;
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} else {
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LOG_WARNING("Unknown device (HWID 0x%08" PRIx32 ")", hwid);
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}
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bank->size = NRF51_UICR_SIZE;
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bank->num_sectors = 1;
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bank->sectors = calloc(bank->num_sectors,
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sizeof((bank->sectors)[0]));
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if (!bank->sectors)
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return ERROR_FLASH_BANK_NOT_PROBED;
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res = target_read_u32(chip->target, NRF51_FICR_CODEPAGESIZE,
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&chip->code_page_size);
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if (res != ERROR_OK) {
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LOG_ERROR("Couldn't read code page size");
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return res;
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}
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res = target_read_u32(chip->target, NRF51_FICR_CODESIZE,
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&chip->code_memory_size);
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if (res != ERROR_OK) {
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LOG_ERROR("Couldn't read code memory size");
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return res;
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}
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if (spec && chip->code_memory_size != spec->flash_size_kb) {
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LOG_ERROR("Chip's reported Flash capacity does not match expected one");
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return ERROR_FAIL;
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}
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bank->size = chip->code_memory_size * 1024;
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bank->num_sectors = bank->size / chip->code_page_size;
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bank->sectors = calloc(bank->num_sectors,
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sizeof((bank->sectors)[0]));
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if (!bank->sectors)
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return ERROR_FLASH_BANK_NOT_PROBED;
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/* Fill out the sector information: all NRF51 sectors are the same size and
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* there is always a fixed number of them. */
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for (int i = 0; i < bank->num_sectors; i++) {
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bank->sectors[i].size = chip->code_page_size;
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bank->sectors[i].offset = i * chip->code_page_size;
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bank->sectors[0].size = bank->size;
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bank->sectors[0].offset = 0;
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/* mark as unknown */
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bank->sectors[i].is_erased = -1;
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bank->sectors[i].is_protected = -1;
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bank->sectors[0].is_erased = 0;
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bank->sectors[0].is_protected = 0;
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chip->bank[1].probed = true;
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}
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nrf51_protect_check(bank);
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chip->probed = true;
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return ERROR_OK;
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}
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static int nrf51_auto_probe(struct flash_bank *bank)
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{
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struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
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int probed = nrf51_bank_is_probed(bank);
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if (chip->probed)
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if (probed < 0)
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return probed;
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else if (probed)
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return ERROR_OK;
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return nrf51_probe(bank);
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else
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return nrf51_probe(bank);
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}
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static struct flash_sector *nrf51_find_sector_by_address(struct flash_bank *bank, uint32_t address)
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@ -522,9 +569,31 @@ static int nrf51_erase_page(struct nrf51_info *chip, struct flash_sector *sector
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if (sector->is_protected)
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return ERROR_FAIL;
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res = nrf51_nvmc_generic_erase(chip,
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NRF51_NVMC_ERASEPAGE,
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sector->offset);
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if (sector->offset == NRF51_UICR_BASE) {
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uint32_t ppfc;
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res = target_read_u32(chip->target, NRF51_FICR_PPFC,
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&ppfc);
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if (res != ERROR_OK) {
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LOG_ERROR("Couldn't read PPFC register");
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return res;
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}
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if ((ppfc & 0xFF) == 0xFF) {
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LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
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return ERROR_FAIL;
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};
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res = nrf51_nvmc_generic_erase(chip,
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NRF51_NVMC_ERASEUICR,
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0x00000001);
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} else {
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res = nrf51_nvmc_generic_erase(chip,
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NRF51_NVMC_ERASEPAGE,
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sector->offset);
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}
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if (res == ERROR_OK)
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sector->is_erased = 1;
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@ -547,8 +616,10 @@ static int nrf51_write_page(struct flash_bank *bank, uint32_t offset, const uint
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if (!sector->is_erased) {
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res = nrf51_erase_page(chip, sector);
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if (res != ERROR_OK)
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to erase sector @ 0x%08"PRIx32, sector->offset);
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goto error;
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}
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}
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res = nrf51_nvmc_write_enable(chip);
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@ -586,18 +657,14 @@ static int nrf51_erase(struct flash_bank *bank, int first, int last)
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return res;
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}
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static int nrf51_write(struct flash_bank *bank, const uint8_t *buffer,
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uint32_t offset, uint32_t count)
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static int nrf51_code_flash_write(struct flash_bank *bank,
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struct nrf51_info *chip,
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const uint8_t *buffer, uint32_t offset, uint32_t count)
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{
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int res;
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struct {
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uint32_t start, end;
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} region;
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struct nrf51_info *chip;
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res = nrf51_get_probed_chip_if_halted(bank, &chip);
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if (res != ERROR_OK)
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return res;
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region.start = offset;
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region.end = offset + count;
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@ -669,39 +736,118 @@ static int nrf51_write(struct flash_bank *bank, const uint8_t *buffer,
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return ERROR_OK;
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}
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FLASH_BANK_COMMAND_HANDLER(nrf51_flash_bank_command)
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static int nrf51_uicr_flash_write(struct flash_bank *bank,
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struct nrf51_info *chip,
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const uint8_t *buffer, uint32_t offset, uint32_t count)
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{
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int res;
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uint8_t uicr[NRF51_UICR_SIZE];
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struct flash_sector *sector = &bank->sectors[0];
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if ((offset + count) > NRF51_UICR_SIZE)
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return ERROR_FAIL;
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res = target_read_memory(bank->target,
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NRF51_UICR_BASE,
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1,
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NRF51_UICR_SIZE,
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uicr);
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if (res != ERROR_OK)
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return res;
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if (!sector->is_erased) {
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res = nrf51_erase_page(chip, sector);
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if (res != ERROR_OK)
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return res;
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}
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res = nrf51_nvmc_write_enable(chip);
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if (res != ERROR_OK)
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return res;
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memcpy(&uicr[offset], buffer, count);
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res = target_write_memory(bank->target,
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NRF51_UICR_BASE,
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4,
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NRF51_UICR_SIZE / 4,
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uicr);
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if (res != ERROR_OK) {
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nrf51_nvmc_read_only(chip);
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return res;
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}
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return nrf51_nvmc_read_only(chip);
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}
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static int nrf51_write(struct flash_bank *bank, const uint8_t *buffer,
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uint32_t offset, uint32_t count)
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{
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int res;
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struct nrf51_info *chip;
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/* Create a new chip */
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chip = calloc(1, sizeof(*chip));
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if (!chip)
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return ERROR_FAIL;
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res = nrf51_get_probed_chip_if_halted(bank, &chip);
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if (res != ERROR_OK)
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return res;
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chip->target = bank->target;
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chip->probed = false;
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return chip->bank[bank->bank_number].write(bank, chip, buffer, offset, count);
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}
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bank->driver_priv = chip;
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if (bank->base != NRF51_FLASH_BASE) {
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LOG_ERROR("Address 0x%08" PRIx32 " invalid bank address (try 0x%08" PRIx32
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"[nrf51 series] )",
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bank->base, NRF51_FLASH_BASE);
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FLASH_BANK_COMMAND_HANDLER(nrf51_flash_bank_command)
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{
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static struct nrf51_info *chip;
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switch (bank->base) {
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case NRF51_FLASH_BASE:
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bank->bank_number = 0;
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break;
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case NRF51_UICR_BASE:
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bank->bank_number = 1;
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break;
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default:
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LOG_ERROR("Invalid bank address 0x%08" PRIx32, bank->base);
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return ERROR_FAIL;
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}
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if (!chip) {
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/* Create a new chip */
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chip = calloc(1, sizeof(*chip));
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if (!chip)
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return ERROR_FAIL;
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chip->target = bank->target;
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}
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switch (bank->base) {
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case NRF51_FLASH_BASE:
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chip->bank[bank->bank_number].write = nrf51_code_flash_write;
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break;
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case NRF51_UICR_BASE:
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chip->bank[bank->bank_number].write = nrf51_uicr_flash_write;
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break;
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}
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chip->bank[bank->bank_number].probed = false;
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bank->driver_priv = chip;
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return ERROR_OK;
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}
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COMMAND_HANDLER(nrf51_handle_mass_erase_command)
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{
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int res;
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struct flash_bank *bank;
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struct flash_bank *bank = NULL;
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struct target *target = get_current_target(CMD_CTX);
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res = get_flash_bank_by_num(0, &bank);
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res = get_flash_bank_by_addr(target, NRF51_FLASH_BASE, true, &bank);
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if (res != ERROR_OK)
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return res;
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assert(bank != NULL);
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struct nrf51_info *chip;
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res = nrf51_get_probed_chip_if_halted(bank, &chip);
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@ -710,7 +856,7 @@ COMMAND_HANDLER(nrf51_handle_mass_erase_command)
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uint32_t ppfc;
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res = target_read_u32(chip->target, NRF51_FICR_PPFC,
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res = target_read_u32(target, NRF51_FICR_PPFC,
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&ppfc);
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if (res != ERROR_OK) {
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LOG_ERROR("Couldn't read PPFC register");
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@ -733,7 +879,19 @@ COMMAND_HANDLER(nrf51_handle_mass_erase_command)
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for (int i = 0; i < bank->num_sectors; i++)
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bank->sectors[i].is_erased = 1;
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return nrf51_protect_check(bank);
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res = nrf51_protect_check(bank);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to check chip's write protection");
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return res;
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}
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res = get_flash_bank_by_addr(target, NRF51_UICR_BASE, true, &bank);
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if (res != ERROR_OK)
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return res;
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bank->sectors[0].is_erased = 1;
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return ERROR_OK;
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}
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static int nrf51_info(struct flash_bank *bank, char *buf, int buf_size)
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@ -66,5 +66,5 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
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# non-"hla" targets it would be useful to have the following in the config.
|
||||
# cortex_m reset_config sysresetreq
|
||||
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME nrf51 0x00000000 0 1 1 $_TARGETNAME
|
||||
flash bank $_CHIPNAME.flash nrf51 0x00000000 0 1 1 $_TARGETNAME
|
||||
flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME
|
||||
|
|
|
|||
Loading…
Reference in New Issue