lpc1768.cfg abstracted and moved to lpc17xx.cfg
- Moved variant-independent code to lpc17xx.cfg, which will be included from lpc17??.cfg files automatically. - lpc1768.cfg filled with variant-dependent code. Change-Id: I7dabe6ed7da7be640ed38c13aaaa096b8796d9a0 Signed-off-by: Vandra Akos <axos88@gmail.com> Reviewed-on: http://openocd.zylin.com/675 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>__archive__
Vandra Akos
Freddie Chopin
parent
52125f1d13
commit
ba00ef3c40
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@ -1,14 +1,8 @@
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# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
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# LPC17xx chips support both JTAG and SWD transports.
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# Adapt based on what transport is active.
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source [find target/swj-dp.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME lpc1768
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}
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set CHIPNAME lpc1768
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set CPUTAPID 0x4ba00477
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set CPURAMSIZE 0x8000
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set CPUROMSIZE 0x80000
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# After reset the chip is clocked by the ~4MHz internal RC oscillator.
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# When board-specific code (reset-init handler or device firmware)
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@ -17,70 +11,7 @@ if { [info exists CHIPNAME] } {
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# (The ROM code doing those updates cares about core clock speed...)
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#
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# CCLK is the core clock frequency in KHz
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if { [info exists CCLK] } {
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set _CCLK $CCLK
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} else {
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set _CCLK 4000
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}
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set CCLK 4000
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x4ba00477
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}
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if { [info exists CPURAMSIZE] } {
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set _CPURAMSIZE $CPURAMSIZE
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} else {
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set _CPURAMSIZE 0x8000
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}
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if { [info exists CPUROMSIZE] } {
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set _CPUROMSIZE $CPUROMSIZE
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} else {
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set _CPUROMSIZE 0x80000
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}
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#delays on reset lines
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adapter_nsrst_delay 200
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jtag_ntrst_delay 200
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#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
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swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
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# LPC1768 has 32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
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# and 32K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000).
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$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
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# LPC1768 has 512kB of flash memory, managed by ROM code (including a
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# boot loader which verifies the flash exception table's checksum).
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# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \
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lpc1700 $_CCLK calc_checksum
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# Run with *real slow* clock by default since the
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# boot rom could have been playing with the PLL, so
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# we have no idea what clock the target is running at.
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adapter_khz 10
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$_TARGETNAME configure -event reset-init {
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# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
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# "User Flash Mode" where interrupt vectors are _not_ remapped,
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# and reside in flash instead).
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#
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# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
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# Bit Symbol Value Description Reset
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# value
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# 0 MAP Memory map control. 0
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# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
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# 1 User mode. The on-chip Flash memory is mapped to address 0.
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# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
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#
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# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
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mww 0x400FC040 0x01
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}
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#Include the main configuration file.
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source [find target/lpc17xx.cfg];
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@ -0,0 +1,93 @@
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# Main file for NXP LPC17xx Cortex-M3
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#
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# !!!!!!
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#
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# This file should not be included directly, rather
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# by the lpc1751.cfg, lpc1752.cfg, etc. which set the
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# needed variables to the appropriate values.
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#
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# !!!!!!
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# LPC17xx chips support both JTAG and SWD transports.
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# Adapt based on what transport is active.
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source [find target/swj-dp.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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error "_CHIPNAME not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
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}
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# After reset the chip is clocked by the ~4MHz internal RC oscillator.
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# When board-specific code (reset-init handler or device firmware)
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# configures another oscillator and/or PLL0, set CCLK to match; if
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# you don't, then flash erase and write operations may misbehave.
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# (The ROM code doing those updates cares about core clock speed...)
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#
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# CCLK is the core clock frequency in KHz
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if { [info exists CCLK] } {
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set _CCLK $CCLK
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} else {
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set _CCLK 4000
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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error "_CPUTAPID not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
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}
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if { [info exists CPURAMSIZE] } {
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set _CPURAMSIZE $CPURAMSIZE
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} else {
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error "_CPURAMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
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}
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if { [info exists CPUROMSIZE] } {
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set _CPUROMSIZE $CPUROMSIZE
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} else {
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error "_CPUROMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
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}
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#delays on reset lines
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adapter_nsrst_delay 200
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jtag_ntrst_delay 200
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#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
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swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
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# The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
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$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
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# The LPC17xx devies have 32/64/128/256/512kB of flash memory, managed by ROM code
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# (including a boot loader which verifies the flash exception table's checksum).
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# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \
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lpc1700 $_CCLK calc_checksum
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# Run with *real slow* clock by default since the
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# boot rom could have been playing with the PLL, so
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# we have no idea what clock the target is running at.
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adapter_khz 10
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$_TARGETNAME configure -event reset-init {
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# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
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# "User Flash Mode" where interrupt vectors are _not_ remapped,
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# and reside in flash instead).
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#
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# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
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# Bit Symbol Value Description Reset
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# value
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# 0 MAP Memory map control. 0
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# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
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# 1 User mode. The on-chip Flash memory is mapped to address 0.
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# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
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#
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# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
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mww 0x400FC040 0x01
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}
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