- the 'help' command now takes an optional argument to display help only on a certain command (thanks to Andrew Dyer for this enhancement)

- OpenOCD now includes the ability to diassemble instructions on its own (only ARM for now, Thumb might follow). 
The command is "armv4_5 disassemble <address> <count> ['thumb']" (thumb is currently unsupported).
I've compared the produced disassembly against GDB/GNU Objdump output, and it seems to be correct, but there may still be some bugs left.


git-svn-id: svn://svn.berlios.de/openocd/trunk@68 b42882b7-edfa-0310-969c-e2dbd0fdcd60

src/helper/command.c

@@ -443,6 +443,15 @@ int command_print_help(command_context_t* context, char* name, char** args, int
 
 	for (c = context->commands; c; c = c->next)
 	{
+		if (argc == 1)
+		{
+			 if (strncasecmp(c->name, args[0], c->unique_len))
+				 continue;
+
+			 if (strncasecmp(c->name, args[0], strlen(args[0])))
+				 continue;
+		} 
+
 		command_print_help_line(context, c, 0);
 	}
 	

src/target/Makefile.am

@@ -2,6 +2,7 @@ INCLUDES = -I$(top_srcdir)/src/gdb -I$(top_srcdir)/src/helper 	-I$(top_srcdir)/s
 METASOURCES = AUTO
 noinst_LIBRARIES = libtarget.a
 libtarget_a_SOURCES = target.c register.c breakpoints.c armv4_5.c embeddedice.c etm.c arm7tdmi.c arm9tdmi.c \
-	arm_jtag.c arm7_9_common.c algorithm.c arm920t.c arm720t.c armv4_5_mmu.c armv4_5_cache.c
+	arm_jtag.c arm7_9_common.c algorithm.c arm920t.c arm720t.c armv4_5_mmu.c armv4_5_cache.c arm_disassembler.c
 noinst_HEADERS = target.h register.h armv4_5.h embeddedice.h etm.h arm7tdmi.h arm9tdmi.h \
-		arm_jtag.h arm7_9_common.h arm920t.h arm720t.h armv4_5_mmu.h armv4_5_cache.h breakpoints.h algorithm.h
+		arm_jtag.h arm7_9_common.h arm920t.h arm720t.h armv4_5_mmu.h armv4_5_cache.h breakpoints.h algorithm.h \
+		arm_disassembler.h

src/target/arm_disassembler.h

@@ -0,0 +1,138 @@
+/***************************************************************************
+ *   Copyright (C) 2006 by Dominic Rath                                    *
+ *   Dominic.Rath@gmx.de                                                   *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+#ifndef ARM_DISASSEMBLER_H
+#define ARM_DISASSEMBLER_H
+
+#include "types.h"
+
+enum arm_instruction_type
+{
+	ARM_UNKNOWN_INSTUCTION,
+	
+	/* Branch instructions */
+	ARM_B,
+	ARM_BL,
+	ARM_BX,
+	ARM_BLX,
+	
+	/* Data processing instructions */
+	ARM_AND,
+	ARM_EOR,
+	ARM_SUB,
+	ARM_RSB,
+	ARM_ADD,
+	ARM_ADC,
+	ARM_SBC,
+	ARM_RSC,
+	ARM_TST,
+	ARM_TEQ,
+	ARM_CMP,
+	ARM_CMN,
+	ARM_ORR,
+	ARM_MOV,
+	ARM_BIC,
+	ARM_MVN,
+	
+	/* Load/store instructions */
+	ARM_LDR,
+	ARM_LDRB,
+	ARM_LDRT,
+	ARM_LDRBT,
+	
+	ARM_LDRH,
+	ARM_LDRSB,
+	ARM_LDRSH,
+	
+	ARM_LDM,
+
+	ARM_STR,
+	ARM_STRB,
+	ARM_STRT,
+	ARM_STRBT,
+	
+	ARM_STRH,
+	
+	ARM_STM,
+	
+	/* Status register access instructions */
+	ARM_MRS,
+	ARM_MSR,
+	
+	/* Multiply instructions */
+	ARM_MUL,
+	ARM_MLA,
+	ARM_SMULL,
+	ARM_SMLAL,
+	ARM_UMULL,
+	ARM_UMLAL,
+	
+	/* Miscellaneous instructions */
+	ARM_CLZ,
+	
+	/* Exception generating instructions */
+	ARM_BKPT,
+	ARM_SWI,
+	
+	/* Coprocessor instructions */
+	ARM_CDP,
+	ARM_LDC,
+	ARM_STC,
+	ARM_MCR,
+	ARM_MRC,
+	
+	/* Semaphore instructions */
+	ARM_SWP,
+	ARM_SWPB,
+	
+	/* Enhanced DSP extensions */
+	ARM_MCRR,
+	ARM_MRRC,
+	ARM_PLD,
+	ARM_QADD,
+	ARM_QDADD,
+	ARM_QSUB,
+	ARM_QDSUB,
+	ARM_SMLAxy,
+	ARM_SMLALxy,
+	ARM_SMLAWy,
+	ARM_SMULxy,
+	ARM_SMULWy,
+	ARM_LDRD,
+	ARM_STRD,
+
+	ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
+};
+
+typedef struct arm_instruction_s
+{
+	enum arm_instruction_type type;
+	char text[128];
+	u32 opcode;
+	
+	/* target */
+	u32 target_address;
+	
+} arm_instruction_t;
+
+extern int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction);
+
+#define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000)>>28])
+
+#endif /* ARM_DISASSEMBLER_H */

src/target/armv4_5.c

@@ -19,6 +19,8 @@
  ***************************************************************************/
 #include "config.h"
 
+#include "arm_disassembler.h"
+
 #include "armv4_5.h"
 
 #include "target.h"
@@ -377,6 +379,47 @@ int handle_armv4_5_core_state_command(struct command_context_s *cmd_ctx, char *c
 	return ERROR_OK;
 }
 
+int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+	target_t *target = get_current_target(cmd_ctx);
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	u32 address;
+	int count;
+	int i;
+	arm_instruction_t cur_instruction;
+	u32 opcode;
+	int thumb;
+	
+	if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
+	{
+		command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
+		return ERROR_OK;
+	}
+	
+	if (argc < 2)
+	{
+		command_print(cmd_ctx, "usage: armv4_5 disassemble <address> <count> ['thumb']");
+		return ERROR_OK;
+	}
+	
+	address = strtoul(args[0], NULL, 0);
+	count = strtoul(args[1], NULL, 0);
+	
+	if (argc >= 3)
+		if (strcmp(args[2], "thumb") == 0)
+			thumb = 1;
+	
+	for (i = 0; i < count; i++)
+	{
+		target->type->read_memory(target, address, 4, 1, (u8*)&opcode);
+		evaluate_opcode(opcode, address, &cur_instruction);
+		command_print(cmd_ctx, "%s", cur_instruction.text);
+		address += (thumb) ? 2 : 4;
+	}
+	
+	return ERROR_OK;
+}
+
 int armv4_5_register_commands(struct command_context_s *cmd_ctx)
 {
 	command_t *armv4_5_cmd;
@@ -386,6 +429,7 @@ int armv4_5_register_commands(struct command_context_s *cmd_ctx)
 	register_command(cmd_ctx, armv4_5_cmd, "reg", handle_armv4_5_reg_command, COMMAND_EXEC, "display ARM core registers");
 	register_command(cmd_ctx, armv4_5_cmd, "core_state", handle_armv4_5_core_state_command, COMMAND_EXEC, "display/change ARM core state <arm|thumb>");
 	
+	register_command(cmd_ctx, armv4_5_cmd, "disassemble", handle_armv4_5_disassemble_command, COMMAND_EXEC, "disassemble instructions <address> <count> ['thumb']");
 	return ERROR_OK;
 }