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flash/nor, contrib/loaders: add stm32 loaders Makefile and generated .inc 

Flash loaders refactored to the new style - use generated .inc
instead of hexadecimal machine code in the flash driver source.

Change-Id: If65a2099589e210f9450819b467d67819fd841fc
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4439
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
riscv-compliance
Tomas Vanek 2018-03-01 22:57:08 +01:00
parent 2eadf1e847
commit b941e2e727
16 changed files with 87 additions and 178 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
contrib/loaders/flash/stm32/Makefile Normal file
View File

@ -0,0 +1,28 @@
BIN2C = ../../../../src/helper/bin2char.sh
CROSS_COMPILE ?= arm-none-eabi-
CC=$(CROSS_COMPILE)gcc
OBJCOPY=$(CROSS_COMPILE)objcopy
OBJDUMP=$(CROSS_COMPILE)objdump
CFLAGS = -static -nostartfiles -mlittle-endian -Wa,-EL
all: stm32f1x.inc stm32f2x.inc stm32h7x.inc stm32l4x.inc stm32lx.inc
.PHONY: clean
%.elf: %.S
$(CC) $(CFLAGS) $< -o $@
%.lst: %.elf
$(OBJDUMP) -S $< > $@
%.bin: %.elf
$(OBJCOPY) -Obinary $< $@
%.inc: %.bin
$(BIN2C) < $< > $@
clean:
-rm -f *.elf *.lst *.bin *.inc

5
contrib/loaders/flash/stm32f1x.S → contrib/loaders/flash/stm32/stm32f1x.S
View File

@ -22,8 +22,6 @@
.syntax unified .syntax unified
.cpu cortex-m0 .cpu cortex-m0
.thumb .thumb
.thumb_func
.global write
/* Params: /* Params:
* r0 - flash base (in), status (out) * r0 - flash base (in), status (out)
@ -39,6 +37,9 @@
#define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register from flash reg base */ #define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register from flash reg base */
.thumb_func
.global _start
_start:
wait_fifo: wait_fifo:
ldr r6, [r2, #0] /* read wp */ ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */ cmp r6, #0 /* abort if wp == 0 */

5
contrib/loaders/flash/stm32/stm32f1x.inc Normal file
View File

@ -0,0 +1,5 @@
/* Autogenerated with ../../../../src/helper/bin2char.sh */
0x16,0x68,0x00,0x2e,0x18,0xd0,0x55,0x68,0xb5,0x42,0xf9,0xd0,0x2e,0x88,0x26,0x80,
0x02,0x35,0x02,0x34,0xc6,0x68,0x01,0x27,0x3e,0x42,0xfb,0xd1,0x14,0x27,0x3e,0x42,
0x08,0xd1,0x9d,0x42,0x01,0xd3,0x15,0x46,0x08,0x35,0x55,0x60,0x01,0x39,0x00,0x29,
0x02,0xd0,0xe5,0xe7,0x00,0x20,0x50,0x60,0x30,0x46,0x00,0xbe,

10
contrib/loaders/flash/stm32f2x.S → contrib/loaders/flash/stm32/stm32f2x.S
View File

@ -25,7 +25,6 @@
.syntax unified .syntax unified
.cpu cortex-m3 .cpu cortex-m3
.thumb .thumb
.thumb_func
/* /*
* Params : * Params :
@ -44,6 +43,11 @@
#define STM32_FLASH_CR_OFFSET 0x10 /* offset of CR register in FLASH struct */ #define STM32_FLASH_CR_OFFSET 0x10 /* offset of CR register in FLASH struct */
#define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register in FLASH struct */ #define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register in FLASH struct */
#define STM32_PROG16 0x101 /* PG | PSIZE_16*/
.thumb_func
.global _start
_start:
wait_fifo: wait_fifo:
ldr r8, [r0, #0] /* read wp */ ldr r8, [r0, #0] /* read wp */
cmp r8, #0 /* abort if wp == 0 */ cmp r8, #0 /* abort if wp == 0 */
@ -52,7 +56,7 @@ wait_fifo:
cmp r7, r8 /* wait until rp != wp */ cmp r7, r8 /* wait until rp != wp */
beq wait_fifo beq wait_fifo
ldr r6, STM32_PROG16 ldr r6, =STM32_PROG16
str r6, [r4, #STM32_FLASH_CR_OFFSET] str r6, [r4, #STM32_FLASH_CR_OFFSET]
ldrh r6, [r7], #0x02 /* read one half-word from src, increment ptr */ ldrh r6, [r7], #0x02 /* read one half-word from src, increment ptr */
strh r6, [r2], #0x02 /* write one half-word from src, increment ptr */ strh r6, [r2], #0x02 /* write one half-word from src, increment ptr */
@ -78,4 +82,4 @@ exit:
mov r0, r6 /* return status in r0 */ mov r0, r6 /* return status in r0 */
bkpt #0x00 bkpt #0x00
STM32_PROG16: .word 0x101 /* PG | PSIZE_16*/ .pool

6
contrib/loaders/flash/stm32/stm32f2x.inc Normal file
View File

@ -0,0 +1,6 @@
/* Autogenerated with ../../../../src/helper/bin2char.sh */
0xd0,0xf8,0x00,0x80,0xb8,0xf1,0x00,0x0f,0x1b,0xd0,0x47,0x68,0x47,0x45,0xf7,0xd0,
0x0d,0x4e,0x26,0x61,0x37,0xf8,0x02,0x6b,0x22,0xf8,0x02,0x6b,0xbf,0xf3,0x4f,0x8f,
0xe6,0x68,0x16,0xf4,0x80,0x3f,0xfb,0xd1,0x16,0xf0,0xf0,0x0f,0x07,0xd1,0x8f,0x42,
0x28,0xbf,0x00,0xf1,0x08,0x07,0x47,0x60,0x01,0x3b,0x13,0xb1,0xe0,0xe7,0x00,0x21,
0x41,0x60,0x30,0x46,0x00,0xbe,0x00,0x00,0x01,0x01,0x00,0x00,

25
contrib/loaders/flash/stm32h7x.S → contrib/loaders/flash/stm32/stm32h7x.S
View File

@ -20,21 +20,6 @@
.syntax unified .syntax unified
.cpu cortex-m7 .cpu cortex-m7
.thumb .thumb
.thumb_func
/*
* To assemble:
* arm-none-eabi-gcc -c stm32h7x.S
*
* To disassemble:
* arm-none-eabi-objdump -d stm32h7x.o
*
* To generate binary file:
* arm-none-eabi-objcopy -O binary stm32h7x.o stm32h7_flash_write_code.bin
*
* To generate include file:
* xxd -i stm32h7_flash_write_code.bin
*/
/* /*
* Code limitations: * Code limitations:
@ -67,7 +52,9 @@
#define STM32_SR_ERROR_MASK 0x03ee0000 /* DBECCERR | SNECCERR | RDSERR | RDPERR | OPERR #define STM32_SR_ERROR_MASK 0x03ee0000 /* DBECCERR | SNECCERR | RDSERR | RDPERR | OPERR
| INCERR | STRBERR | PGSERR | WRPERR */ | INCERR | STRBERR | PGSERR | WRPERR */
code: .thumb_func
.global _start
_start:
ldr r5, [r0, #4] /* read rp */ ldr r5, [r0, #4] /* read rp */
wait_fifo: wait_fifo:
@ -100,7 +87,7 @@ busy:
tst r6, #STM32_SR_BUSY_MASK tst r6, #STM32_SR_BUSY_MASK
bne busy /* operation in progress, wait ... */ bne busy /* operation in progress, wait ... */
ldr r7, stm32_sr_error_mask ldr r7, =STM32_SR_ERROR_MASK
tst r6, r7 tst r6, r7
bne error /* fail... */ bne error /* fail... */
@ -117,5 +104,5 @@ exit:
mov r0, r6 /* return status in r0 */ mov r0, r6 /* return status in r0 */
bkpt #0x00 bkpt #0x00
stm32_sr_error_mask: .pool
.word STM32_SR_ERROR_MASK

7
contrib/loaders/flash/stm32/stm32h7x.inc Normal file
View File

@ -0,0 +1,7 @@
/* Autogenerated with ../../../../src/helper/bin2char.sh */
0x45,0x68,0x06,0x68,0x26,0xb3,0x76,0x1b,0x42,0xbf,0x76,0x18,0x36,0x1a,0x08,0x3e,
0x20,0x2e,0xf6,0xd3,0x4f,0xf0,0x32,0x06,0xe6,0x60,0x4f,0xf0,0x08,0x07,0x55,0xf8,
0x04,0x6b,0x42,0xf8,0x04,0x6b,0xbf,0xf3,0x4f,0x8f,0x8d,0x42,0x28,0xbf,0x00,0xf1,
0x08,0x05,0x01,0x3f,0xf3,0xd1,0x26,0x69,0x16,0xf0,0x01,0x0f,0xfb,0xd1,0x05,0x4f,
0x3e,0x42,0x03,0xd1,0x45,0x60,0x01,0x3b,0xdb,0xd1,0x01,0xe0,0x00,0x27,0x47,0x60,
0x30,0x46,0x00,0xbe,0x00,0x00,0xee,0x03,

24
contrib/loaders/flash/stm32l4x.S → contrib/loaders/flash/stm32/stm32l4x.S
View File

@ -27,20 +27,6 @@
.syntax unified .syntax unified
.cpu cortex-m4 .cpu cortex-m4
.thumb .thumb
.thumb_func
/* To assemble:
* arm-none-eabi-gcc -c stm32l4x.S
*
* To disassemble:
* arm-none-eabi-objdump -o stm32l4x.o
*
* To generate binary file:
* arm-none-eabi-objcopy -O binary stm32l4x.o stm32l4_flash_write_code.bin
*
* To generate include file:
* xxd -i stm32l4_flash_write_code.bin
*/
/* /*
* Params : * Params :
@ -59,6 +45,11 @@
#define STM32_FLASH_CR_OFFSET 0x14 /* offset of CR register in FLASH struct */ #define STM32_FLASH_CR_OFFSET 0x14 /* offset of CR register in FLASH struct */
#define STM32_FLASH_SR_OFFSET 0x10 /* offset of SR register in FLASH struct */ #define STM32_FLASH_SR_OFFSET 0x10 /* offset of SR register in FLASH struct */
#define STM32_PROG 0x1 /* PG */
.thumb_func
.global _start
_start:
wait_fifo: wait_fifo:
ldr r8, [r0, #0] /* read wp */ ldr r8, [r0, #0] /* read wp */
cmp r8, #0 /* abort if wp == 0 */ cmp r8, #0 /* abort if wp == 0 */
@ -71,7 +62,7 @@ wait_fifo:
cmp r6, #8 /* wait until 8 bytes are available */ cmp r6, #8 /* wait until 8 bytes are available */
bcc wait_fifo bcc wait_fifo
ldr r6, STM32_PROG ldr r6, =STM32_PROG
str r6, [r4, #STM32_FLASH_CR_OFFSET] str r6, [r4, #STM32_FLASH_CR_OFFSET]
ldrd r6, [r5], #0x08 /* read one word from src, increment ptr */ ldrd r6, [r5], #0x08 /* read one word from src, increment ptr */
strd r6, [r2], #0x08 /* write one word to dst, increment ptr */ strd r6, [r2], #0x08 /* write one word to dst, increment ptr */
@ -97,4 +88,5 @@ exit:
mov r0, r6 /* return status in r0 */ mov r0, r6 /* return status in r0 */
bkpt #0x00 bkpt #0x00
STM32_PROG: .word 0x1 /* PG */ .pool

7
contrib/loaders/flash/stm32/stm32l4x.inc Normal file
View File

@ -0,0 +1,7 @@
/* Autogenerated with ../../../../src/helper/bin2char.sh */
0xd0,0xf8,0x00,0x80,0xb8,0xf1,0x00,0x0f,0x20,0xd0,0x45,0x68,0xb8,0xeb,0x05,0x06,
0x44,0xbf,0x76,0x18,0x36,0x1a,0x08,0x2e,0xf2,0xd3,0x0d,0x4e,0x66,0x61,0xf5,0xe8,
0x02,0x67,0xe2,0xe8,0x02,0x67,0xbf,0xf3,0x4f,0x8f,0x26,0x69,0x16,0xf4,0x80,0x3f,
0xfb,0xd1,0x16,0xf0,0xfa,0x0f,0x07,0xd1,0x8d,0x42,0x28,0xbf,0x00,0xf1,0x08,0x05,
0x45,0x60,0x01,0x3b,0x13,0xb1,0xdb,0xe7,0x00,0x21,0x41,0x60,0x30,0x46,0x00,0xbe,
0x01,0x00,0x00,0x00,

6
contrib/loaders/flash/stm32lx.S → contrib/loaders/flash/stm32/stm32lx.S
View File

@ -28,13 +28,10 @@
***************************************************************************/ ***************************************************************************/
// Build : arm-eabi-gcc -c stm32lx.S
.text .text
.syntax unified .syntax unified
.cpu cortex-m0 .cpu cortex-m0
.thumb .thumb
.thumb_func
.global write
/* /*
r0 - destination address r0 - destination address
@ -42,6 +39,9 @@
r2 - count r2 - count
*/ */
.thumb_func
.global _start
_start:
// r2 = source + count * 4 // r2 = source + count * 4
lsls r2, r2, #2 lsls r2, r2, #2
adds r2, r1, r2 adds r2, r1, r2

2
contrib/loaders/flash/stm32/stm32lx.inc Normal file
View File

@ -0,0 +1,2 @@
/* Autogenerated with ../../../../src/helper/bin2char.sh */
0x92,0x00,0x8a,0x18,0x01,0xe0,0x08,0xc9,0x08,0xc0,0x91,0x42,0xfb,0xd1,0x00,0xbe,

39
src/flash/nor/stm32f1x.c
View File

@ -572,45 +572,8 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
struct armv7m_algorithm armv7m_info; struct armv7m_algorithm armv7m_info;
int retval = ERROR_OK; int retval = ERROR_OK;
/* see contrib/loaders/flash/stm32f1x.S for src */
static const uint8_t stm32x_flash_write_code[] = { static const uint8_t stm32x_flash_write_code[] = {
/* #define STM32_FLASH_SR_OFFSET 0x0C */ #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
/* wait_fifo: */
0x16, 0x68, /* ldr r6, [r2, #0] */
0x00, 0x2e, /* cmp r6, #0 */
0x18, 0xd0, /* beq exit */
0x55, 0x68, /* ldr r5, [r2, #4] */
0xb5, 0x42, /* cmp r5, r6 */
0xf9, 0xd0, /* beq wait_fifo */
0x2e, 0x88, /* ldrh r6, [r5, #0] */
0x26, 0x80, /* strh r6, [r4, #0] */
0x02, 0x35, /* adds r5, #2 */
0x02, 0x34, /* adds r4, #2 */
/* busy: */
0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
0x01, 0x27, /* movs r7, #1 */
0x3e, 0x42, /* tst r6, r7 */
0xfb, 0xd1, /* bne busy */
0x14, 0x27, /* movs r7, #0x14 */
0x3e, 0x42, /* tst r6, r7 */
0x08, 0xd1, /* bne error */
0x9d, 0x42, /* cmp r5, r3 */
0x01, 0xd3, /* bcc no_wrap */
0x15, 0x46, /* mov r5, r2 */
0x08, 0x35, /* adds r5, #8 */
/* no_wrap: */
0x55, 0x60, /* str r5, [r2, #4] */
0x01, 0x39, /* subs r1, r1, #1 */
0x00, 0x29, /* cmp r1, #0 */
0x02, 0xd0, /* beq exit */
0xe5, 0xe7, /* b wait_fifo */
/* error: */
0x00, 0x20, /* movs r0, #0 */
0x50, 0x60, /* str r0, [r2, #4] */
/* exit: */
0x30, 0x46, /* mov r0, r6 */
0x00, 0xbe, /* bkpt #0 */
}; };
/* flash write code */ /* flash write code */

39
src/flash/nor/stm32f2x.c
View File

@ -584,45 +584,8 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
struct armv7m_algorithm armv7m_info; struct armv7m_algorithm armv7m_info;
int retval = ERROR_OK; int retval = ERROR_OK;
/* see contrib/loaders/flash/stm32f2x.S for src */
static const uint8_t stm32x_flash_write_code[] = { static const uint8_t stm32x_flash_write_code[] = {
/* wait_fifo: */ #include "../../../contrib/loaders/flash/stm32/stm32f2x.inc"
0xD0, 0xF8, 0x00, 0x80, /* ldr r8, [r0, #0] */
0xB8, 0xF1, 0x00, 0x0F, /* cmp r8, #0 */
0x1A, 0xD0, /* beq exit */
0x47, 0x68, /* ldr r7, [r0, #4] */
0x47, 0x45, /* cmp r7, r8 */
0xF7, 0xD0, /* beq wait_fifo */
0xDF, 0xF8, 0x34, 0x60, /* ldr r6, STM32_PROG16 */
0x26, 0x61, /* str r6, [r4, #STM32_FLASH_CR_OFFSET] */
0x37, 0xF8, 0x02, 0x6B, /* ldrh r6, [r7], #0x02 */
0x22, 0xF8, 0x02, 0x6B, /* strh r6, [r2], #0x02 */
0xBF, 0xF3, 0x4F, 0x8F, /* dsb sy */
/* busy: */
0xE6, 0x68, /* ldr r6, [r4, #STM32_FLASH_SR_OFFSET] */
0x16, 0xF4, 0x80, 0x3F, /* tst r6, #0x10000 */
0xFB, 0xD1, /* bne busy */
0x16, 0xF0, 0xF0, 0x0F, /* tst r6, #0xf0 */
0x07, 0xD1, /* bne error */
0x8F, 0x42, /* cmp r7, r1 */
0x28, 0xBF, /* it cs */
0x00, 0xF1, 0x08, 0x07, /* addcs r7, r0, #8 */
0x47, 0x60, /* str r7, [r0, #4] */
0x01, 0x3B, /* subs r3, r3, #1 */
0x13, 0xB1, /* cbz r3, exit */
0xDF, 0xE7, /* b wait_fifo */
/* error: */
0x00, 0x21, /* movs r1, #0 */
0x41, 0x60, /* str r1, [r0, #4] */
/* exit: */
0x30, 0x46, /* mov r0, r6 */
0x00, 0xBE, /* bkpt #0x00 */
/* <STM32_PROG16>: */
0x01, 0x01, 0x00, 0x00, /* .word 0x00000101 */
}; };
if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),

45
src/flash/nor/stm32h7x.c
View File

@ -568,51 +568,8 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv; struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
int retval = ERROR_OK; int retval = ERROR_OK;
/* see contrib/loaders/flash/smt32h7x.S for src */
static const uint8_t stm32x_flash_write_code[] = { static const uint8_t stm32x_flash_write_code[] = {
/* <code>: */ #include "../../../contrib/loaders/flash/stm32/stm32h7x.inc"
0x45, 0x68, /* ldr r5, [r0, #4] */
/* <wait_fifo>: */
0x06, 0x68, /* ldr r6, [r0, #0] */
0x26, 0xb3, /* cbz r6, <exit> */
0x76, 0x1b, /* subs r6, r6, r5 */
0x42, 0xbf, /* ittt mi */
0x76, 0x18, /* addmi r6, r6, r1 */
0x36, 0x1a, /* submi r6, r6, r0 */
0x08, 0x3e, /* submi r6, #8 */
0x20, 0x2e, /* cmp r6, #32 */
0xf6, 0xd3, /* bcc.n <wait_fifo> */
0x4f, 0xf0, 0x32, 0x06, /* mov.w r6, #STM32_PROG */
0xe6, 0x60, /* str r6, [r4, #STM32_FLASH_CR_OFFSET] */
0x4f, 0xf0, 0x08, 0x07, /* mov.w r7, #8 */
/* <write_flash>: */
0x55, 0xf8, 0x04, 0x6b, /* ldr.w r6, [r5], #4 */
0x42, 0xf8, 0x04, 0x6b, /* str.w r6, [r2], #4 */
0xbf, 0xf3, 0x4f, 0x8f, /* dsb sy */
0x8d, 0x42, /* cmp r5, r1 */
0x28, 0xbf, /* it cs */
0x00, 0xf1, 0x08, 0x05, /* addcs.w r5, r0, #8 */
0x01, 0x3f, /* subs r7, #1 */
0xf3, 0xd1, /* bne.n <write_flash> */
/* <busy>: */
0x26, 0x69, /* ldr r6, [r4, #STM32_FLASH_SR_OFFSET] */
0x16, 0xf0, 0x01, 0x0f, /* tst.w r6, #STM32_SR_BUSY_MASK */
0xfb, 0xd1, /* bne.n <busy> */
0x05, 0x4f, /* ldr r7, [pc, #20] ; (<stm32_sr_error_mask>) */
0x3e, 0x42, /* tst r6, r7 */
0x03, 0xd1, /* bne.n <error> */
0x45, 0x60, /* str r5, [r0, #4] */
0x01, 0x3b, /* subs r3, #1 */
0xdb, 0xd1, /* bne.n <wait_fifo> */
0x01, 0xe0, /* b.n <exit> */
/* <error>: */
0x00, 0x27, /* movs r7, #0 */
0x47, 0x60, /* str r7, [r0, #4] */
/* <exit>: */
0x30, 0x46, /* mov r0, r6 */
0x00, 0xbe, /* bkpt 0x0000 */
/* <stm32_sr_error_mask>: */
0x00, 0x00, 0xee, 0x03 /* .word 0x03ee0000 ; (STM32_SR_ERROR_MASK) */
}; };
if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),

13
src/flash/nor/stm32l4x.c
View File

@ -461,19 +461,8 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
struct armv7m_algorithm armv7m_info; struct armv7m_algorithm armv7m_info;
int retval = ERROR_OK; int retval = ERROR_OK;
/* See contrib/loaders/flash/stm32l4x.S for source and
* hints how to generate the data!
*/
static const uint8_t stm32l4_flash_write_code[] = { static const uint8_t stm32l4_flash_write_code[] = {
0xd0, 0xf8, 0x00, 0x80, 0xb8, 0xf1, 0x00, 0x0f, 0x21, 0xd0, 0x45, 0x68, #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
0xb8, 0xeb, 0x05, 0x06, 0x44, 0xbf, 0x76, 0x18, 0x36, 0x1a, 0x08, 0x2e,
0xf2, 0xd3, 0xdf, 0xf8, 0x36, 0x60, 0x66, 0x61, 0xf5, 0xe8, 0x02, 0x67,
0xe2, 0xe8, 0x02, 0x67, 0xbf, 0xf3, 0x4f, 0x8f, 0x26, 0x69, 0x16, 0xf4,
0x80, 0x3f, 0xfb, 0xd1, 0x16, 0xf0, 0xfa, 0x0f, 0x07, 0xd1, 0x8d, 0x42,
0x28, 0xbf, 0x00, 0xf1, 0x08, 0x05, 0x45, 0x60, 0x01, 0x3b, 0x13, 0xb1,
0xda, 0xe7, 0x00, 0x21, 0x41, 0x60, 0x30, 0x46, 0x00, 0xbe, 0x01, 0x00,
0x00, 0x00
}; };
if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code), if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),

4
src/flash/nor/stm32lx.c
View File

@ -448,10 +448,8 @@ static int stm32lx_write_half_pages(struct flash_bank *bank, const uint8_t *buff
int retval = ERROR_OK; int retval = ERROR_OK;
/* see contib/loaders/flash/stm32lx.S for src */
static const uint8_t stm32lx_flash_write_code[] = { static const uint8_t stm32lx_flash_write_code[] = {
0x92, 0x00, 0x8A, 0x18, 0x01, 0xE0, 0x08, 0xC9, 0x08, 0xC0, 0x91, 0x42, 0xFB, 0xD1, 0x00, 0xBE #include "../../../contrib/loaders/flash/stm32/stm32lx.inc"
}; };
/* Make sure we're performing a half-page aligned write. */ /* Make sure we're performing a half-page aligned write. */