comments on doc/manual/primer/jtag.txt
1. fix some errors in jtag.txt(in my personal opinion, please review). 2. remove a broken link Signed-off-by: Jun Ma <sync.jma@gmail.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>__archive__
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@ -29,7 +29,7 @@ TMS which will select different shift registers.
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The first thing you need to do is reset the state machine, because when
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The first thing you need to do is reset the state machine, because when
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you connect to a chip you do not know what state the controller is in,you need
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you connect to a chip you do not know what state the controller is in,you need
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to clock TMS as 1, at least 7 times. This will put you into "Test Logic
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to clock TMS as 1, at least 5 times. This will put you into "Test Logic
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Reset" State. Knowing this, you can, once reset, then track what each
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Reset" State. Knowing this, you can, once reset, then track what each
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transition on TMS will do, and hence know what state the JTAG state
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transition on TMS will do, and hence know what state the JTAG state
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machine is in.
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machine is in.
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@ -45,9 +45,9 @@ instruction register.
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For example, one of the data registers will be known as "bypass" this is
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For example, one of the data registers will be known as "bypass" this is
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(usually) a single bit which has no function and is used to bypass the
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(usually) a single bit which has no function and is used to bypass the
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chip. Assume we have 3 identical chips, wired up like the picture
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chip. Assume we have 3 identical chips, wired up like the picture(wikipedia)
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and each has a 3 bit instruction register, and there are 2 known
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and each has a 3 bits instruction register, and there are 2 known
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instructions (110 = bypass, 010 = some other function) if we want to use
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instructions (110 = bypass, 010 = "some other function") if we want to use
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"some other function", on the second chip in the line, and not change
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"some other function", on the second chip in the line, and not change
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the other chips we would do the following transitions.
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the other chips we would do the following transitions.
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@ -66,13 +66,13 @@ each chip [110] [010] [110]
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The order is reversed, because we shift out the least significant bit
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The order is reversed, because we shift out the least significant bit
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first. Then we transition TMS:
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first. Then we transition TMS:
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1 1 1 1 0 0
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1 1 1 0 0
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which puts us in the "Shift DR state".
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which puts us in the "Shift DR state".
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Now when we clock data onto TDI (again while holding TMS to 0) , the
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Now when we clock data onto TDI (again while holding TMS to 0) , the
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data shifts through the data registers, and because of the instruction
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data shifts through the data registers, and because of the instruction
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registers we selected (some other function has 8 bits in its data
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registers we selected ("some other function" has 8 bits in its data
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register), our total data register in the chain looks like this:
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register), our total data register in the chain looks like this:
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0 00000000 0
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0 00000000 0
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@ -107,10 +107,6 @@ gets interesting. But in and of itself, JTAG is actually very simple.
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@section primerjtag More Reading
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@section primerjtag More Reading
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The following link goes to an HTML (or PDF) introduction to JTAG,
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written by one of the original members of the JTAG committee: @par
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http://www.asset-intertech.com/products/boundscan.htm
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A separate primer contains information about @subpage primerjtagbs for
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A separate primer contains information about @subpage primerjtagbs for
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developers that want to extend OpenOCD for such purposes.
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developers that want to extend OpenOCD for such purposes.
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