target: rename cortex_m3 to cortex_m
Rename cortex_m3 target to use a more correct cortex_m name. This also adds a deprecated_name var so that older scripts issue a warning to update the target name. cfg files have also been updated to the new target name. Change-Id: Ia8429f38e88da677249c5caa560c50f8ce56ea10 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1129 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>__archive__
parent
564a5eb537
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b7d2cdc0d4
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@ -986,7 +986,7 @@ that the @code{reset-init} event handler does.
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Likewise, the @command{arm9 vector_catch} command (or
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Likewise, the @command{arm9 vector_catch} command (or
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@cindex vector_catch
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@cindex vector_catch
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its siblings @command{xscale vector_catch}
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its siblings @command{xscale vector_catch}
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and @command{cortex_m3 vector_catch}) can be a timesaver
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and @command{cortex_m vector_catch}) can be a timesaver
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during some debug sessions, but don't make everyone use that either.
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during some debug sessions, but don't make everyone use that either.
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Keep those kinds of debugging aids in your user config file,
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Keep those kinds of debugging aids in your user config file,
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along with messaging and tracing setup.
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along with messaging and tracing setup.
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@ -1948,7 +1948,7 @@ don't want to reset all targets at once.
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Such a handler might write to chip registers to force a reset,
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Such a handler might write to chip registers to force a reset,
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use a JRC to do that (preferable -- the target may be wedged!),
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use a JRC to do that (preferable -- the target may be wedged!),
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or force a watchdog timer to trigger.
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or force a watchdog timer to trigger.
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(For Cortex-M3 targets, this is not necessary. The target
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(For Cortex-M targets, this is not necessary. The target
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driver knows how to use trigger an NVIC reset when SRST is
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driver knows how to use trigger an NVIC reset when SRST is
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not available.)
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not available.)
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@ -3953,7 +3953,7 @@ look like with more than one:
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TargetName Type Endian TapName State
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TargetName Type Endian TapName State
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-- ------------------ ---------- ------ ------------------ ------------
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-- ------------------ ---------- ------ ------------------ ------------
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0* at91rm9200.cpu arm920t little at91rm9200.cpu running
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0* at91rm9200.cpu arm920t little at91rm9200.cpu running
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1 MyTarget cortex_m3 little mychip.foo tap-disabled
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1 MyTarget cortex_m little mychip.foo tap-disabled
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@end verbatim
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@end verbatim
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One member of that list is the @dfn{current target}, which
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One member of that list is the @dfn{current target}, which
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@ -4065,7 +4065,7 @@ At this writing, the supported CPU types and variants are:
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@item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
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@item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
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(Support for this is preliminary and incomplete.)
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(Support for this is preliminary and incomplete.)
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@item @code{cortex_a8} -- this is an ARMv7 core with an MMU
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@item @code{cortex_a8} -- this is an ARMv7 core with an MMU
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@item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
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@item @code{cortex_m} -- this is an ARMv7 core, supporting only the
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compact Thumb2 instruction set.
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compact Thumb2 instruction set.
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@item @code{dragonite} -- resembles arm966e
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@item @code{dragonite} -- resembles arm966e
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@item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
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@item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
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@ -4119,7 +4119,7 @@ to be much more board-specific.
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The key steps you use might look something like this
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The key steps you use might look something like this
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@example
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@example
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target create MyTarget cortex_m3 -chain-position mychip.cpu
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target create MyTarget cortex_m -chain-position mychip.cpu
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$MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
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$MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
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$MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
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$MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
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$MyTarget configure -event reset-init @{ myboard_reinit @}
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$MyTarget configure -event reset-init @{ myboard_reinit @}
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@ -7300,7 +7300,7 @@ cores @emph{except the ARM1176} use the same six bits.
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@cindex Debug Access Port
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@cindex Debug Access Port
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@cindex DAP
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@cindex DAP
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These commands are specific to ARM architecture v7 Debug Access Port (DAP),
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These commands are specific to ARM architecture v7 Debug Access Port (DAP),
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included on Cortex-M3 and Cortex-A8 systems.
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included on Cortex-M and Cortex-A8 systems.
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They are available in addition to other core-specific commands that may be available.
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They are available in addition to other core-specific commands that may be available.
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@deffn Command {dap apid} [num]
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@deffn Command {dap apid} [num]
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@ -7333,10 +7333,10 @@ fix CSW_SPROT from register AP_REG_CSW on selected dap.
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Defaulting to 0.
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Defaulting to 0.
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@end deffn
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@end deffn
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@subsection Cortex-M3 specific commands
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@subsection Cortex-M specific commands
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@cindex Cortex-M3
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@cindex Cortex-M
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@deffn Command {cortex_m3 maskisr} (@option{auto}|@option{on}|@option{off})
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@deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off})
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Control masking (disabling) interrupts during target step/resume.
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Control masking (disabling) interrupts during target step/resume.
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The @option{auto} option handles interrupts during stepping a way they get
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The @option{auto} option handles interrupts during stepping a way they get
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@ -7353,7 +7353,7 @@ with interrupts enabled, i.e. the same way the @option{off} option does.
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Default is @option{auto}.
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Default is @option{auto}.
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@end deffn
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@end deffn
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@deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
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@deffn Command {cortex_m vector_catch} [@option{all}|@option{none}|list]
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@cindex vector_catch
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@cindex vector_catch
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Vector Catch hardware provides dedicated breakpoints
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Vector Catch hardware provides dedicated breakpoints
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for certain hardware events.
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for certain hardware events.
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@ -7380,7 +7380,7 @@ must also be explicitly enabled.
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This finishes by listing the current vector catch configuration.
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This finishes by listing the current vector catch configuration.
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@end deffn
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@end deffn
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@deffn Command {cortex_m3 reset_config} (@option{srst}|@option{sysresetreq}|@option{vectreset})
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@deffn Command {cortex_m reset_config} (@option{srst}|@option{sysresetreq}|@option{vectreset})
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Control reset handling. The default @option{srst} is to use srst if fitted,
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Control reset handling. The default @option{srst} is to use srst if fitted,
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otherwise fallback to @option{vectreset}.
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otherwise fallback to @option{vectreset}.
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@itemize @minus
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@itemize @minus
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@ -7388,7 +7388,7 @@ otherwise fallback to @option{vectreset}.
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@item @option{sysresetreq} use NVIC SYSRESETREQ to reset system.
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@item @option{sysresetreq} use NVIC SYSRESETREQ to reset system.
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@item @option{vectreset} use NVIC VECTRESET to reset system.
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@item @option{vectreset} use NVIC VECTRESET to reset system.
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@end itemize
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@end itemize
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Using @option{vectreset} is a safe option for all current Cortex-M3 cores.
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Using @option{vectreset} is a safe option for all current Cortex-M cores.
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This however has the disadvantage of only resetting the core, all peripherals
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This however has the disadvantage of only resetting the core, all peripherals
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are uneffected. A solution would be to use a @code{reset-init} event handler to manually reset
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are uneffected. A solution would be to use a @code{reset-init} event handler to manually reset
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the peripherals.
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the peripherals.
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@ -7407,7 +7407,7 @@ The most powerful mechanism is semihosting, but there is also
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a lighter weight mechanism using only the DCC channel.
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a lighter weight mechanism using only the DCC channel.
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Currently @command{target_request debugmsgs}
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Currently @command{target_request debugmsgs}
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is supported only for @option{arm7_9} and @option{cortex_m3} cores.
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is supported only for @option{arm7_9} and @option{cortex_m} cores.
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These messages are received as part of target polling, so
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These messages are received as part of target polling, so
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you need to have @command{poll on} active to receive them.
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you need to have @command{poll on} active to receive them.
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They are intrusive in that they will affect program execution
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They are intrusive in that they will affect program execution
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@ -7913,10 +7913,10 @@ and an RTOS until he told GDB to disable the IRQs while stepping:
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@example
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@example
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define hook-step
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define hook-step
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mon cortex_m3 maskisr on
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mon cortex_m maskisr on
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end
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end
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define hookpost-step
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define hookpost-step
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mon cortex_m3 maskisr off
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mon cortex_m maskisr off
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end
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end
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@end example
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@end example
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@ -94,7 +94,7 @@ struct ChibiOS_params {
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struct ChibiOS_params ChibiOS_params_list[] = {
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struct ChibiOS_params ChibiOS_params_list[] = {
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{
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{
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"cortex_m3", /* target_name */
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"cortex_m", /* target_name */
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0,
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0,
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NULL, /* stacking_info */
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NULL, /* stacking_info */
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},
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},
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@ -50,7 +50,7 @@ struct FreeRTOS_params {
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const struct FreeRTOS_params FreeRTOS_params_list[] = {
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const struct FreeRTOS_params FreeRTOS_params_list[] = {
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{
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{
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"cortex_m3", /* target_name */
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"cortex_m", /* target_name */
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4, /* thread_count_width; */
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4, /* thread_count_width; */
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4, /* pointer_width; */
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4, /* pointer_width; */
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16, /* list_next_offset; */
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16, /* list_next_offset; */
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@ -73,7 +73,7 @@ struct ThreadX_params {
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const struct ThreadX_params ThreadX_params_list[] = {
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const struct ThreadX_params ThreadX_params_list[] = {
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{
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{
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"cortex_m3", /* target_name */
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"cortex_m", /* target_name */
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4, /* pointer_width; */
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4, /* pointer_width; */
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8, /* thread_stack_offset; */
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8, /* thread_stack_offset; */
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40, /* thread_name_offset; */
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40, /* thread_name_offset; */
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@ -64,7 +64,7 @@ struct eCos_params {
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const struct eCos_params eCos_params_list[] = {
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const struct eCos_params eCos_params_list[] = {
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{
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{
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"cortex_m3", /* target_name */
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"cortex_m", /* target_name */
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4, /* pointer_width; */
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4, /* pointer_width; */
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0x0c, /* thread_stack_offset; */
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0x0c, /* thread_stack_offset; */
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0x9c, /* thread_name_offset; */
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0x9c, /* thread_name_offset; */
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@ -2256,9 +2256,9 @@ static const struct command_registration cortex_m3_command_handlers[] = {
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.chain = armv7m_command_handlers,
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.chain = armv7m_command_handlers,
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},
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},
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{
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{
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.name = "cortex_m3",
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.name = "cortex_m",
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.mode = COMMAND_EXEC,
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.mode = COMMAND_EXEC,
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.help = "Cortex-M3 command group",
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.help = "Cortex-M command group",
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.usage = "",
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.usage = "",
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.chain = cortex_m3_exec_command_handlers,
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.chain = cortex_m3_exec_command_handlers,
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},
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},
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@ -2266,7 +2266,8 @@ static const struct command_registration cortex_m3_command_handlers[] = {
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};
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};
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struct target_type cortexm3_target = {
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struct target_type cortexm3_target = {
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.name = "cortex_m3",
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.name = "cortex_m",
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.deprecated_name = "cortex_m3",
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.poll = cortex_m3_poll,
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.poll = cortex_m3_poll,
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.arch_state = armv7m_arch_state,
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.arch_state = armv7m_arch_state,
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@ -167,3 +167,9 @@ proc init_targets {} {
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# Additionally board config scripts can define a procedure init_board that will be executed after init and init_targets
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# Additionally board config scripts can define a procedure init_board that will be executed after init and init_targets
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proc init_board {} {
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proc init_board {} {
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}
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}
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# deprecated target name cmds
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proc cortex_m3 args {
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echo "DEPRECATED! use 'cortex_m' not 'cortex_m3'"
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eval cortex_m $args
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}
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@ -58,7 +58,7 @@ if { [info exists CPUTAPID] } {
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
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# 16K is plenty, the smallest chip has this much
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# 16K is plenty, the smallest chip has this much
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
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@ -69,4 +69,4 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
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# if srst is not fitted use SYSRESETREQ to
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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# perform a soft reset
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cortex_m3 reset_config sysresetreq
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cortex_m reset_config sysresetreq
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@ -18,12 +18,12 @@ if { [info exists CPUTAPID] } {
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -endian little -chain-position $_TARGETNAME
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target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME
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set _FLASHNAME $_CHIPNAME.flash
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set _FLASHNAME $_CHIPNAME.flash
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flash bank flash0 at91sam3 0x00400000 0 0 0 $_TARGETNAME
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flash bank flash0 at91sam3 0x00400000 0 0 0 $_TARGETNAME
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# if srst is not fitted use SYSRESETREQ to
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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# perform a soft reset
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cortex_m3 reset_config sysresetreq
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cortex_m reset_config sysresetreq
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
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# 16K is plenty, the smallest chip has this much
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# 16K is plenty, the smallest chip has this much
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
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# if srst is not fitted use SYSRESETREQ to
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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# perform a soft reset
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cortex_m3 reset_config sysresetreq
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cortex_m reset_config sysresetreq
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@ -29,7 +29,7 @@ reset_config trst_only
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
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# MB9BF506 has 64kB of SRAM on its main system bus
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# MB9BF506 has 64kB of SRAM on its main system bus
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$_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0
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$_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0
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@ -44,4 +44,4 @@ adapter_khz 500
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# if srst is not fitted use SYSRESETREQ to
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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# perform a soft reset
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cortex_m3 reset_config sysresetreq
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cortex_m reset_config sysresetreq
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@ -29,11 +29,11 @@ set _TARGETNAME $_CHIPNAME.cpu
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
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$_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
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$_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
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$_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
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$_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
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# if srst is not fitted use SYSRESETREQ to
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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# perform a soft reset
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cortex_m3 reset_config sysresetreq
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cortex_m reset_config sysresetreq
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@ -29,11 +29,11 @@ set _TARGETNAME $_CHIPNAME.cpu
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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|
||||||
target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
|
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
|
||||||
|
|
||||||
$_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
|
$_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
|
||||||
$_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
|
$_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
|
||||||
|
|
||||||
# if srst is not fitted use SYSRESETREQ to
|
# if srst is not fitted use SYSRESETREQ to
|
||||||
# perform a soft reset
|
# perform a soft reset
|
||||||
cortex_m3 reset_config sysresetreq
|
cortex_m reset_config sysresetreq
|
||||||
|
|
|
@ -17,4 +17,4 @@ set CCLK 12000
|
||||||
source [find target/lpc17xx.cfg];
|
source [find target/lpc17xx.cfg];
|
||||||
|
|
||||||
# if srst is not fitted, use SYSRESETREQ to perform a soft reset
|
# if srst is not fitted, use SYSRESETREQ to perform a soft reset
|
||||||
cortex_m3 reset_config sysresetreq
|
cortex_m reset_config sysresetreq
|
||||||
|
|
|
@ -57,7 +57,7 @@ jtag_ntrst_delay 200
|
||||||
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
|
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
|
||||||
|
|
||||||
set _TARGETNAME $_CHIPNAME.cpu
|
set _TARGETNAME $_CHIPNAME.cpu
|
||||||
target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
|
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
|
||||||
|
|
||||||
# The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
|
# The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
|
||||||
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
|
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
|
||||||
|
@ -94,4 +94,4 @@ $_TARGETNAME configure -event reset-init {
|
||||||
|
|
||||||
# if srst is not fitted use VECTRESET to
|
# if srst is not fitted use VECTRESET to
|
||||||
# perform a soft reset - SYSRESETREQ is not supported
|
# perform a soft reset - SYSRESETREQ is not supported
|
||||||
cortex_m3 reset_config vectreset
|
cortex_m reset_config vectreset
|
||||||
|
|
|
@ -24,8 +24,8 @@ if { [info exists M3_JTAG_TAPID] } {
|
||||||
jtag newtap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID
|
jtag newtap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID
|
||||||
|
|
||||||
set _TARGETNAME $_CHIPNAME.m3
|
set _TARGETNAME $_CHIPNAME.m3
|
||||||
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
|
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||||
|
|
||||||
# if srst is not fitted use SYSRESETREQ to
|
# if srst is not fitted use SYSRESETREQ to
|
||||||
# perform a soft reset
|
# perform a soft reset
|
||||||
cortex_m3 reset_config sysresetreq
|
cortex_m reset_config sysresetreq
|
||||||
|
|
|
@ -40,12 +40,12 @@ jtag newtap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
|
||||||
jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
|
jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
|
||||||
-expected-id $_M0_JTAG_TAPID
|
-expected-id $_M0_JTAG_TAPID
|
||||||
|
|
||||||
target create $_CHIPNAME.m4 cortex_m3 -chain-position $_CHIPNAME.m4
|
target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
|
||||||
target create $_CHIPNAME.m0 cortex_m3 -chain-position $_CHIPNAME.m0
|
target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0
|
||||||
|
|
||||||
# on this CPU we should use VECTRESET to perform a soft reset and
|
# on this CPU we should use VECTRESET to perform a soft reset and
|
||||||
# manually reset the periphery
|
# manually reset the periphery
|
||||||
# SRST or SYSRESETREQ disable the debug interface for the time of
|
# SRST or SYSRESETREQ disable the debug interface for the time of
|
||||||
# the reset and will not fit our requirements for a consistent debug
|
# the reset and will not fit our requirements for a consistent debug
|
||||||
# session
|
# session
|
||||||
cortex_m3 reset_config vectreset
|
cortex_m reset_config vectreset
|
||||||
|
|
|
@ -104,8 +104,8 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
|
||||||
#
|
#
|
||||||
# M3 targets, separate TAP/DAP for each core
|
# M3 targets, separate TAP/DAP for each core
|
||||||
#
|
#
|
||||||
target create $_CHIPNAME.m30 cortex_m3 -chain-position $_CHIPNAME.m30_dap
|
target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap
|
||||||
target create $_CHIPNAME.m31 cortex_m3 -chain-position $_CHIPNAME.m31_dap
|
target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap
|
||||||
|
|
||||||
|
|
||||||
# Once the JRC is up, enable our TAPs
|
# Once the JRC is up, enable our TAPs
|
||||||
|
|
|
@ -104,8 +104,8 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
|
||||||
#
|
#
|
||||||
# M3 targets, separate TAP/DAP for each core
|
# M3 targets, separate TAP/DAP for each core
|
||||||
#
|
#
|
||||||
target create $_CHIPNAME.m30 cortex_m3 -chain-position $_CHIPNAME.m30_dap
|
target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap
|
||||||
target create $_CHIPNAME.m31 cortex_m3 -chain-position $_CHIPNAME.m31_dap
|
target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap
|
||||||
|
|
||||||
|
|
||||||
# Once the JRC is up, enable our TAPs
|
# Once the JRC is up, enable our TAPs
|
||||||
|
|
|
@ -52,7 +52,7 @@ if { [info exists WORKAREASIZE] } {
|
||||||
}
|
}
|
||||||
|
|
||||||
set _TARGETNAME $_CHIPNAME.cpu
|
set _TARGETNAME $_CHIPNAME.cpu
|
||||||
target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
|
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
|
||||||
|
|
||||||
# 8K working area at base of ram, not backed up
|
# 8K working area at base of ram, not backed up
|
||||||
#
|
#
|
||||||
|
@ -157,11 +157,11 @@ $_TARGETNAME configure -event reset-start {
|
||||||
if {$device_class == 0 || $device_class == 1 ||
|
if {$device_class == 0 || $device_class == 1 ||
|
||||||
$device_class == 3 || $device_class == 5} {
|
$device_class == 3 || $device_class == 5} {
|
||||||
# Sandstorm, Fury, DustDevil and Blizzard are able to use NVIC SYSRESETREQ
|
# Sandstorm, Fury, DustDevil and Blizzard are able to use NVIC SYSRESETREQ
|
||||||
cortex_m3 reset_config sysresetreq
|
cortex_m reset_config sysresetreq
|
||||||
} else {
|
} else {
|
||||||
# Tempest and Firestorm default to using NVIC VECTRESET
|
# Tempest and Firestorm default to using NVIC VECTRESET
|
||||||
# peripherals will need reseting manually, see proc reset_peripherals
|
# peripherals will need reseting manually, see proc reset_peripherals
|
||||||
cortex_m3 reset_config vectreset
|
cortex_m reset_config vectreset
|
||||||
|
|
||||||
# reset peripherals, based on code in
|
# reset peripherals, based on code in
|
||||||
# http://www.ti.com/lit/er/spmz573a/spmz573a.pdf
|
# http://www.ti.com/lit/er/spmz573a/spmz573a.pdf
|
||||||
|
|
|
@ -68,7 +68,7 @@ jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
|
||||||
-expected-id $_BSTAPID8 -expected-id $_BSTAPID9
|
-expected-id $_BSTAPID8 -expected-id $_BSTAPID9
|
||||||
|
|
||||||
set _TARGETNAME $_CHIPNAME.cpu
|
set _TARGETNAME $_CHIPNAME.cpu
|
||||||
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
|
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||||
|
|
||||||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
||||||
|
|
||||||
|
@ -78,4 +78,4 @@ flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
|
||||||
|
|
||||||
# if srst is not fitted use SYSRESETREQ to
|
# if srst is not fitted use SYSRESETREQ to
|
||||||
# perform a soft reset
|
# perform a soft reset
|
||||||
cortex_m3 reset_config sysresetreq
|
cortex_m reset_config sysresetreq
|
||||||
|
|
|
@ -52,7 +52,7 @@ if { [info exists BSTAPID] } {
|
||||||
jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
|
jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
|
||||||
|
|
||||||
set _TARGETNAME $_CHIPNAME.cpu
|
set _TARGETNAME $_CHIPNAME.cpu
|
||||||
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
|
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||||
|
|
||||||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
||||||
|
|
||||||
|
@ -61,4 +61,4 @@ flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
|
||||||
|
|
||||||
# if srst is not fitted use SYSRESETREQ to
|
# if srst is not fitted use SYSRESETREQ to
|
||||||
# perform a soft reset
|
# perform a soft reset
|
||||||
cortex_m3 reset_config sysresetreq
|
cortex_m reset_config sysresetreq
|
||||||
|
|
|
@ -52,7 +52,7 @@ if { [info exists BSTAPID] } {
|
||||||
jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
|
jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
|
||||||
|
|
||||||
set _TARGETNAME $_CHIPNAME.cpu
|
set _TARGETNAME $_CHIPNAME.cpu
|
||||||
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
|
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||||
|
|
||||||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
||||||
|
|
||||||
|
@ -61,4 +61,4 @@ flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
|
||||||
|
|
||||||
# if srst is not fitted use SYSRESETREQ to
|
# if srst is not fitted use SYSRESETREQ to
|
||||||
# perform a soft reset
|
# perform a soft reset
|
||||||
cortex_m3 reset_config sysresetreq
|
cortex_m reset_config sysresetreq
|
||||||
|
|
|
@ -51,7 +51,7 @@ if { [info exists BSTAPID] } {
|
||||||
jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
|
jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
|
||||||
|
|
||||||
set _TARGETNAME $_CHIPNAME.cpu
|
set _TARGETNAME $_CHIPNAME.cpu
|
||||||
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
|
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||||
|
|
||||||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
||||||
|
|
||||||
|
@ -60,4 +60,4 @@ flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
|
||||||
|
|
||||||
# if srst is not fitted use SYSRESETREQ to
|
# if srst is not fitted use SYSRESETREQ to
|
||||||
# perform a soft reset
|
# perform a soft reset
|
||||||
cortex_m3 reset_config sysresetreq
|
cortex_m reset_config sysresetreq
|
||||||
|
|
|
@ -48,7 +48,7 @@ if { [info exists BSTAPID] } {
|
||||||
jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
|
jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
|
||||||
|
|
||||||
set _TARGETNAME $_CHIPNAME.cpu
|
set _TARGETNAME $_CHIPNAME.cpu
|
||||||
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
|
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||||
|
|
||||||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
||||||
|
|
||||||
|
@ -59,7 +59,7 @@ flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
|
||||||
|
|
||||||
# if srst is not fitted use SYSRESETREQ to
|
# if srst is not fitted use SYSRESETREQ to
|
||||||
# perform a soft reset
|
# perform a soft reset
|
||||||
cortex_m3 reset_config sysresetreq
|
cortex_m reset_config sysresetreq
|
||||||
|
|
||||||
proc stm32l_enable_HSI {} {
|
proc stm32l_enable_HSI {} {
|
||||||
# Enable HSI as clock source
|
# Enable HSI as clock source
|
||||||
|
|
Loading…
Reference in New Issue