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Make m*deleg regs conditional on U/S/N 

Change-Id: I544fc15625400d8ad64d4a65f0fc9d77f428ca84
riscv-compliance-dev
Tim Newsome 2018-03-23 13:43:12 -07:00
parent ca13327abf
commit b6dca68b2e
1 changed files with 9 additions and 0 deletions
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9
src/target/riscv/riscv.c
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@ -2323,6 +2323,15 @@ int riscv_init_registers(struct target *target)
case CSR_SATP: case CSR_SATP:
r->exist = riscv_supports_extension(target, 'S'); r->exist = riscv_supports_extension(target, 'S');
break; break;
case CSR_MEDELEG:
case CSR_MIDELEG:
/* "In systems with only M-mode, or with both M-mode and
* U-mode but without U-mode trap support, the medeleg and
* mideleg registers should not exist." */
r->exist = (riscv_supports_extension(target, 'S') ||
riscv_supports_extension(target, 'U')) &&
!riscv_supports_extension(target, 'N');
break;
} }
if (!r->exist && expose_csr) { if (!r->exist && expose_csr) {