From b6dca68b2e03a1344007939702f1a84faa56343d Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Fri, 23 Mar 2018 13:43:12 -0700 Subject: [PATCH] Make m*deleg regs conditional on U/S/N Change-Id: I544fc15625400d8ad64d4a65f0fc9d77f428ca84 --- src/target/riscv/riscv.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 9f16a400a..073a355e1 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -2323,6 +2323,15 @@ int riscv_init_registers(struct target *target) case CSR_SATP: r->exist = riscv_supports_extension(target, 'S'); break; + case CSR_MEDELEG: + case CSR_MIDELEG: + /* "In systems with only M-mode, or with both M-mode and + * U-mode but without U-mode trap support, the medeleg and + * mideleg registers should not exist." */ + r->exist = (riscv_supports_extension(target, 'S') || + riscv_supports_extension(target, 'U')) && + !riscv_supports_extension(target, 'N'); + break; } if (!r->exist && expose_csr) {