xscale: stackframe corruption bugfix
Resolve a "FIX" comment; yes that was superfluous given that the JTAG core does that check by default. It was also buggy since it wrote to a stack frame that went away before the write happened!! Other fixes: remove pointless malloc(); zero-init scan_field_t values wherever they appear; whitespace scrub; spelling fix. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>__archive__
David Brownell
parent
85398ccdcf
commit
b6c4d1006f
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@ -42,7 +42,7 @@
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* Intel XScale® Core Developer’s Manual, January 2004
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* Order Number: 273473-002
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* This has a chapter detailing debug facilities, and punts some
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* details to chip-specific microarchitecture documentats.
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* details to chip-specific microarchitecture documents.
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*
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* Hot-Debug for Intel XScale® Core Debug White Paper, May 2005
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* Document Number: 273539-005
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@ -166,21 +166,15 @@ static int xscale_jtag_set_instr(jtag_tap_t *tap, uint32_t new_instr)
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if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
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{
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scan_field_t field;
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uint8_t scratch[4];
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memset(&field, 0, sizeof field);
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field.tap = tap;
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field.num_bits = tap->ir_length;
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field.out_value = calloc(CEIL(field.num_bits, 8), 1);
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field.out_value = scratch;
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buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
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uint8_t tmp[4];
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field.in_value = tmp;
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jtag_add_ir_scan(1, &field, jtag_get_end_state());
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/* FIX!!!! isn't this check superfluous? verify_ircapture handles this? */
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jtag_check_value_mask(&field, tap->expected, tap->expected_mask);
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free(field.out_value);
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}
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return ERROR_OK;
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@ -190,9 +184,7 @@ static int xscale_read_dcsr(target_t *target)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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xscale_common_t *xscale = armv4_5->arch_info;
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int retval;
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scan_field_t fields[3];
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uint8_t field0 = 0x0;
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uint8_t field0_check_value = 0x2;
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@ -207,6 +199,8 @@ static int xscale_read_dcsr(target_t *target)
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buf_set_u32(&field0, 1, 1, xscale->hold_rst);
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buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
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memset(&fields, 0, sizeof fields);
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fields[0].tap = target->tap;
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fields[0].num_bits = 3;
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fields[0].out_value = &field0;
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@ -215,7 +209,6 @@ static int xscale_read_dcsr(target_t *target)
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fields[1].tap = target->tap;
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fields[1].num_bits = 32;
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fields[1].out_value = NULL;
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fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
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fields[2].tap = target->tap;
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@ -277,30 +270,24 @@ static int xscale_receive(target_t *target, uint32_t *buffer, int num_words)
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uint8_t field2_check_mask = 0x1;
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int words_done = 0;
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int words_scheduled = 0;
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int i;
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path[0] = TAP_DRSELECT;
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path[1] = TAP_DRCAPTURE;
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path[2] = TAP_DRSHIFT;
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memset(&fields, 0, sizeof fields);
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fields[0].tap = target->tap;
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fields[0].num_bits = 3;
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fields[0].out_value = NULL;
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fields[0].in_value = NULL;
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fields[0].check_value = &field0_check_value;
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fields[0].check_mask = &field0_check_mask;
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fields[1].tap = target->tap;
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fields[1].num_bits = 32;
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fields[1].out_value = NULL;
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fields[1].check_value = NULL;
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fields[1].check_mask = NULL;
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fields[2].tap = target->tap;
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fields[2].num_bits = 1;
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fields[2].out_value = NULL;
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fields[2].in_value = NULL;
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fields[2].check_value = &field2_check_value;
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fields[2].check_mask = &field2_check_mask;
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@ -377,10 +364,8 @@ static int xscale_read_tx(target_t *target, int consume)
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xscale_common_t *xscale = armv4_5->arch_info;
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tap_state_t path[3];
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tap_state_t noconsume_path[6];
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int retval;
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struct timeval timeout, now;
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scan_field_t fields[3];
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uint8_t field0_in = 0x0;
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uint8_t field0_check_value = 0x2;
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@ -403,19 +388,18 @@ static int xscale_read_tx(target_t *target, int consume)
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noconsume_path[4] = TAP_DREXIT2;
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noconsume_path[5] = TAP_DRSHIFT;
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memset(&fields, 0, sizeof fields);
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fields[0].tap = target->tap;
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fields[0].num_bits = 3;
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fields[0].out_value = NULL;
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fields[0].in_value = &field0_in;
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fields[1].tap = target->tap;
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fields[1].num_bits = 32;
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fields[1].out_value = NULL;
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fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
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fields[2].tap = target->tap;
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fields[2].num_bits = 1;
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fields[2].out_value = NULL;
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uint8_t tmp;
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fields[2].in_value = &tmp;
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@ -477,10 +461,8 @@ static int xscale_write_rx(target_t *target)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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xscale_common_t *xscale = armv4_5->arch_info;
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int retval;
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struct timeval timeout, now;
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scan_field_t fields[3];
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uint8_t field0_out = 0x0;
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uint8_t field0_in = 0x0;
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@ -494,6 +476,8 @@ static int xscale_write_rx(target_t *target)
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xscale_jtag_set_instr(target->tap, XSCALE_DBGRX);
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memset(&fields, 0, sizeof fields);
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fields[0].tap = target->tap;
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fields[0].num_bits = 3;
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fields[0].out_value = &field0_out;
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@ -502,7 +486,6 @@ static int xscale_write_rx(target_t *target)
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fields[1].tap = target->tap;
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fields[1].num_bits = 32;
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fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
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fields[1].in_value = NULL;
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fields[2].tap = target->tap;
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fields[2].num_bits = 1;
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@ -637,9 +620,7 @@ static int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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xscale_common_t *xscale = armv4_5->arch_info;
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int retval;
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scan_field_t fields[3];
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uint8_t field0 = 0x0;
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uint8_t field0_check_value = 0x2;
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@ -660,6 +641,8 @@ static int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
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buf_set_u32(&field0, 1, 1, xscale->hold_rst);
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buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
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memset(&fields, 0, sizeof fields);
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fields[0].tap = target->tap;
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fields[0].num_bits = 3;
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fields[0].out_value = &field0;
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@ -669,7 +652,6 @@ static int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
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fields[1].tap = target->tap;
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fields[1].num_bits = 32;
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fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
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fields[1].in_value = NULL;
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fields[2].tap = target->tap;
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fields[2].num_bits = 1;
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@ -728,15 +710,15 @@ static int xscale_load_ic(target_t *target, uint32_t va, uint32_t buffer[8])
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/* virtual address of desired cache line */
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buf_set_u32(packet, 0, 27, va >> 5);
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memset(&fields, 0, sizeof fields);
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fields[0].tap = target->tap;
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fields[0].num_bits = 6;
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fields[0].out_value = &cmd;
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fields[0].in_value = NULL;
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fields[1].tap = target->tap;
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fields[1].num_bits = 27;
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fields[1].out_value = packet;
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fields[1].in_value = NULL;
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jtag_add_dr_scan(2, fields, jtag_get_end_state());
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@ -776,15 +758,15 @@ static int xscale_invalidate_ic_line(target_t *target, uint32_t va)
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/* virtual address of desired cache line */
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buf_set_u32(packet, 0, 27, va >> 5);
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memset(&fields, 0, sizeof fields);
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fields[0].tap = target->tap;
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fields[0].num_bits = 6;
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fields[0].out_value = &cmd;
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fields[0].in_value = NULL;
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fields[1].tap = target->tap;
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fields[1].num_bits = 27;
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fields[1].out_value = packet;
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fields[1].in_value = NULL;
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jtag_add_dr_scan(2, fields, jtag_get_end_state());
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