aarch64: armv8 cache functions update
Update cache identification to match functionality present in armv7a_cache.c Change-Id: I2dc4bee80f5a22b8728334d40331c183d1406f27 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>gitignore-build
Matthias Welwarsky
parent
ef263a45a2
commit
b69750fd0d
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@ -735,8 +735,10 @@ static int aarch64_post_debug_entry(struct target *target)
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LOG_DEBUG("System_register: %8.8" PRIx32, aarch64->system_control_reg);
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aarch64->system_control_reg_curr = aarch64->system_control_reg;
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if (armv8->armv8_mmu.armv8_cache.ctype == -1)
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armv8_identify_cache(target);
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if (armv8->armv8_mmu.armv8_cache.info == -1) {
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armv8_identify_cache(armv8);
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armv8_read_mpidr(armv8);
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}
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armv8->armv8_mmu.mmu_enabled =
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(aarch64->system_control_reg & 0x1U) ? 1 : 0;
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@ -37,6 +37,8 @@
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#include "target.h"
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#include "target_type.h"
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#define __unused __attribute__((unused))
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static const char * const armv8_state_strings[] = {
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"AArch32", "Thumb", "Jazelle", "ThumbEE", "AArch64",
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};
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@ -208,6 +210,38 @@ static int armv8_write_core_reg(struct target *target, struct reg *r,
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return ERROR_OK;
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}
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#endif
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/* retrieve core id cluster id */
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int armv8_read_mpidr(struct armv8_common *armv8)
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{
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int retval = ERROR_FAIL;
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struct arm_dpm *dpm = armv8->arm.dpm;
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uint32_t mpidr;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_MPIDR), &mpidr);
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if (retval != ERROR_OK)
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goto done;
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if (mpidr & 1<<31) {
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armv8->multi_processor_system = (mpidr >> 30) & 1;
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armv8->cluster_id = (mpidr >> 8) & 0xf;
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armv8->cpu_id = mpidr & 0x3;
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LOG_INFO("%s cluster %x core %x %s", target_name(armv8->arm.target),
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armv8->cluster_id,
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armv8->cpu_id,
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armv8->multi_processor_system == 0 ? "multi core" : "mono core");
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} else
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LOG_ERROR("mpdir not in multiprocessor format");
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done:
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dpm->finish(dpm);
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return retval;
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}
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/**
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* Configures host-side ARM records to reflect the specified CPSR.
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* Later, code can use arm_reg_current() to map register numbers
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@ -368,7 +402,7 @@ static uint8_t armv8_pa_size(uint32_t ps)
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return ret;
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}
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static int armv8_read_ttbcr32(struct target *target)
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static __unused int armv8_read_ttbcr32(struct target *target)
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{
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struct armv8_common *armv8 = target_to_armv8(target);
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struct arm_dpm *dpm = armv8->arm.dpm;
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@ -528,103 +562,10 @@ int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
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return ERROR_OK;
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}
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static int armv8_handle_inner_cache_info_command(struct command_context *cmd_ctx,
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struct armv8_cache_common *armv8_cache)
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{
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if (armv8_cache->ctype == -1) {
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command_print(cmd_ctx, "cache not yet identified");
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return ERROR_OK;
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}
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command_print(cmd_ctx,
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"D-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
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armv8_cache->d_u_size.linelen,
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armv8_cache->d_u_size.associativity,
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armv8_cache->d_u_size.nsets,
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armv8_cache->d_u_size.cachesize);
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command_print(cmd_ctx,
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"I-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
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armv8_cache->i_size.linelen,
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armv8_cache->i_size.associativity,
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armv8_cache->i_size.nsets,
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armv8_cache->i_size.cachesize);
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return ERROR_OK;
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}
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static int _armv8_flush_all_data(struct target *target)
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{
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struct armv8_common *armv8 = target_to_armv8(target);
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struct arm_dpm *dpm = armv8->arm.dpm;
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struct armv8_cachesize *d_u_size =
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&(armv8->armv8_mmu.armv8_cache.d_u_size);
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int32_t c_way, c_index = d_u_size->index;
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int retval;
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/* check that cache data is on at target halt */
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if (!armv8->armv8_mmu.armv8_cache.d_u_cache_enabled) {
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LOG_INFO("flushed not performed :cache not on at target halt");
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return ERROR_OK;
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}
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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do {
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c_way = d_u_size->way;
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do {
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uint32_t value = (c_index << d_u_size->index_shift)
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| (c_way << d_u_size->way_shift);
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/* DCCISW */
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/* LOG_INFO ("%d %d %x",c_way,c_index,value); */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV8_MSR_GP(SYSTEM_DCCISW, 0),
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value);
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if (retval != ERROR_OK)
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goto done;
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c_way -= 1;
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} while (c_way >= 0);
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c_index -= 1;
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} while (c_index >= 0);
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return retval;
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done:
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LOG_ERROR("flushed failed");
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dpm->finish(dpm);
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return retval;
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}
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static int armv8_flush_all_data(struct target *target)
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{
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int retval = ERROR_FAIL;
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/* check that armv8_cache is correctly identify */
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struct armv8_common *armv8 = target_to_armv8(target);
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if (armv8->armv8_mmu.armv8_cache.ctype == -1) {
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LOG_ERROR("trying to flush un-identified cache");
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return retval;
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}
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if (target->smp) {
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/* look if all the other target have been flushed in order to flush level
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* 2 */
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struct target_list *head;
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struct target *curr;
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head = target->head;
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while (head != (struct target_list *)NULL) {
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curr = head->target;
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if (curr->state == TARGET_HALTED) {
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LOG_INFO("Wait flushing data l1 on core %" PRId32, curr->coreid);
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retval = _armv8_flush_all_data(curr);
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}
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head = head->next;
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}
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} else
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retval = _armv8_flush_all_data(target);
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return retval;
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}
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int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
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struct armv8_cache_common *armv8_cache)
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{
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if (armv8_cache->ctype == -1) {
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if (armv8_cache->info == -1) {
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command_print(cmd_ctx, "cache not yet identified");
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return ERROR_OK;
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}
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@ -634,174 +575,6 @@ int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
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return ERROR_OK;
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}
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/* retrieve core id cluster id */
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static int armv8_read_mpidr(struct target *target)
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{
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int retval = ERROR_FAIL;
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struct armv8_common *armv8 = target_to_armv8(target);
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struct arm_dpm *dpm = armv8->arm.dpm;
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uint32_t mpidr;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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/* MRC p15,0,<Rd>,c0,c0,5; read Multiprocessor ID register*/
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retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_MPIDR), &mpidr);
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if (retval != ERROR_OK)
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goto done;
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if (mpidr & 1<<31) {
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armv8->multi_processor_system = (mpidr >> 30) & 1;
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armv8->cluster_id = (mpidr >> 8) & 0xf;
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armv8->cpu_id = mpidr & 0x3;
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LOG_INFO("%s cluster %x core %x %s", target_name(target),
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armv8->cluster_id,
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armv8->cpu_id,
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armv8->multi_processor_system == 0 ? "multi core" : "mono core");
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} else
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LOG_ERROR("mpdir not in multiprocessor format");
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done:
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dpm->finish(dpm);
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return retval;
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}
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int armv8_identify_cache(struct target *target)
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{
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/* read cache descriptor */
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int retval = ERROR_FAIL;
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struct armv8_common *armv8 = target_to_armv8(target);
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struct arm_dpm *dpm = armv8->arm.dpm;
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uint32_t cache_selected, clidr;
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uint32_t cache_i_reg, cache_d_reg;
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struct armv8_cache_common *cache = &(armv8->armv8_mmu.armv8_cache);
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int is_aarch64 = armv8->arm.core_state == ARM_STATE_AARCH64;
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retval = is_aarch64 ? armv8_read_ttbcr(target) : armv8_read_ttbcr32(target);
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if (retval != ERROR_OK)
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return retval;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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/* retrieve CLIDR */
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retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_CLIDR), &clidr);
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if (retval != ERROR_OK)
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goto done;
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clidr = (clidr & 0x7000000) >> 23;
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LOG_INFO("number of cache level %" PRIx32, (uint32_t)(clidr / 2));
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if ((clidr / 2) > 1) {
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/* FIXME not supported present in cortex A8 and later */
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/* in cortex A7, A15 */
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LOG_ERROR("cache l2 present :not supported");
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}
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/* retrieve selected cache*/
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retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_CSSELR), &cache_selected);
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if (retval != ERROR_OK)
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goto done;
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/* select instruction cache
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* [0] : 1 instruction cache selection , 0 data cache selection */
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retval = dpm->instr_write_data_r0(dpm, armv8_opcode(armv8, WRITE_REG_CSSELR), 1);
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if (retval != ERROR_OK)
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goto done;
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/* read CCSIDR
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* MRC P15,1,<RT>,C0, C0,0 ;on cortex A9 read CCSIDR
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* [2:0] line size 001 eight word per line
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* [27:13] NumSet 0x7f 16KB, 0xff 32Kbytes, 0x1ff 64Kbytes */
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retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_CCSIDR), &cache_i_reg);
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if (retval != ERROR_OK)
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goto done;
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/* select data cache*/
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retval = dpm->instr_write_data_r0(dpm, armv8_opcode(armv8, WRITE_REG_CSSELR), 0);
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if (retval != ERROR_OK)
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goto done;
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retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_CCSIDR), &cache_d_reg);
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if (retval != ERROR_OK)
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goto done;
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/* restore selected cache */
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dpm->instr_write_data_r0(dpm, armv8_opcode(armv8, WRITE_REG_CSSELR), cache_selected);
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if (retval != ERROR_OK)
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goto done;
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dpm->finish(dpm);
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/* put fake type */
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cache->d_u_size.linelen = 16 << (cache_d_reg & 0x7);
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cache->d_u_size.cachesize = (((cache_d_reg >> 13) & 0x7fff)+1)/8;
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cache->d_u_size.nsets = (cache_d_reg >> 13) & 0x7fff;
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cache->d_u_size.associativity = ((cache_d_reg >> 3) & 0x3ff) + 1;
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/* compute info for set way operation on cache */
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cache->d_u_size.index_shift = (cache_d_reg & 0x7) + 4;
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cache->d_u_size.index = (cache_d_reg >> 13) & 0x7fff;
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cache->d_u_size.way = ((cache_d_reg >> 3) & 0x3ff);
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cache->d_u_size.way_shift = cache->d_u_size.way + 1;
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{
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int i = 0;
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while (((cache->d_u_size.way_shift >> i) & 1) != 1)
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i++;
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cache->d_u_size.way_shift = 32-i;
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}
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#if 0
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LOG_INFO("data cache index %d << %d, way %d << %d",
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cache->d_u_size.index, cache->d_u_size.index_shift,
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cache->d_u_size.way,
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cache->d_u_size.way_shift);
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LOG_INFO("data cache %d bytes %d KBytes asso %d ways",
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cache->d_u_size.linelen,
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cache->d_u_size.cachesize,
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cache->d_u_size.associativity);
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#endif
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cache->i_size.linelen = 16 << (cache_i_reg & 0x7);
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cache->i_size.associativity = ((cache_i_reg >> 3) & 0x3ff) + 1;
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cache->i_size.nsets = (cache_i_reg >> 13) & 0x7fff;
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cache->i_size.cachesize = (((cache_i_reg >> 13) & 0x7fff)+1)/8;
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/* compute info for set way operation on cache */
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cache->i_size.index_shift = (cache_i_reg & 0x7) + 4;
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cache->i_size.index = (cache_i_reg >> 13) & 0x7fff;
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cache->i_size.way = ((cache_i_reg >> 3) & 0x3ff);
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cache->i_size.way_shift = cache->i_size.way + 1;
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{
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int i = 0;
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while (((cache->i_size.way_shift >> i) & 1) != 1)
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i++;
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cache->i_size.way_shift = 32-i;
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}
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#if 0
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LOG_INFO("instruction cache index %d << %d, way %d << %d",
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cache->i_size.index, cache->i_size.index_shift,
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cache->i_size.way, cache->i_size.way_shift);
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LOG_INFO("instruction cache %d bytes %d KBytes asso %d ways",
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cache->i_size.linelen,
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cache->i_size.cachesize,
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cache->i_size.associativity);
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#endif
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/* if no l2 cache initialize l1 data cache flush function function */
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if (armv8->armv8_mmu.armv8_cache.flush_all_data_cache == NULL) {
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armv8->armv8_mmu.armv8_cache.display_cache_info =
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armv8_handle_inner_cache_info_command;
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armv8->armv8_mmu.armv8_cache.flush_all_data_cache =
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armv8_flush_all_data;
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}
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armv8->armv8_mmu.armv8_cache.ctype = 0;
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done:
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dpm->finish(dpm);
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armv8_read_mpidr(target);
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return retval;
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}
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int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
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{
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struct arm *arm = &armv8->arm;
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@ -818,7 +591,7 @@ int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
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#endif
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armv8->armv8_mmu.armv8_cache.l2_cache = NULL;
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armv8->armv8_mmu.armv8_cache.ctype = -1;
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armv8->armv8_mmu.armv8_cache.info = -1;
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armv8->armv8_mmu.armv8_cache.flush_all_data_cache = NULL;
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armv8->armv8_mmu.armv8_cache.display_cache_info = NULL;
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return ERROR_OK;
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@ -97,12 +97,22 @@ struct armv8_cachesize {
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uint32_t way_shift;
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};
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struct armv8_cache_common {
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int ctype;
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/* information about one architecture cache at any level */
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struct armv8_arch_cache {
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int ctype; /* cache type, CLIDR encoding */
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struct armv8_cachesize d_u_size; /* data cache */
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struct armv8_cachesize i_size; /* instruction cache */
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};
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struct armv8_cache_common {
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int info;
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int loc;
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uint32_t iminline;
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uint32_t dminline;
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struct armv8_arch_cache arch[6]; /* cache info, L1 - L7 */
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int i_cache_enabled;
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int d_u_cache_enabled;
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/* l2 external unified cache if some */
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void *l2_cache;
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int (*flush_all_data_cache)(struct target *target);
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@ -249,7 +259,8 @@ target_to_armv8(struct target *target)
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#define PAGE_SIZE_4KB_TRBBASE_MASK 0xFFFFFFFFF000
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int armv8_arch_state(struct target *target);
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int armv8_identify_cache(struct target *target);
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int armv8_read_mpidr(struct armv8_common *armv8);
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int armv8_identify_cache(struct armv8_common *armv8);
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int armv8_init_arch_info(struct target *target, struct armv8_common *armv8);
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int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
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target_addr_t *val, int meminfo);
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|
@ -24,6 +24,11 @@
|
|||
#include "armv8_dpm.h"
|
||||
#include "armv8_opcodes.h"
|
||||
|
||||
/* CLIDR cache types */
|
||||
#define CACHE_LEVEL_HAS_UNIFIED_CACHE 0x4
|
||||
#define CACHE_LEVEL_HAS_D_CACHE 0x2
|
||||
#define CACHE_LEVEL_HAS_I_CACHE 0x1
|
||||
|
||||
static int armv8_d_cache_sanity_check(struct armv8_common *armv8)
|
||||
{
|
||||
struct armv8_cache_common *armv8_cache = &armv8->armv8_mmu.armv8_cache;
|
||||
|
|
@ -44,11 +49,72 @@ static int armv8_i_cache_sanity_check(struct armv8_common *armv8)
|
|||
return ERROR_TARGET_INVALID;
|
||||
}
|
||||
|
||||
static int armv8_cache_d_inner_flush_level(struct arm_dpm *dpm, struct armv8_cachesize *size, int cl)
|
||||
{
|
||||
int retval = ERROR_OK;
|
||||
int32_t c_way, c_index = size->index;
|
||||
|
||||
LOG_DEBUG("cl %" PRId32, cl);
|
||||
do {
|
||||
c_way = size->way;
|
||||
do {
|
||||
uint32_t value = (c_index << size->index_shift)
|
||||
| (c_way << size->way_shift) | (cl << 1);
|
||||
/*
|
||||
* DC CISW - Clean and invalidate data cache
|
||||
* line by Set/Way.
|
||||
*/
|
||||
retval = dpm->instr_write_data_r0(dpm,
|
||||
ARMV8_SYS(SYSTEM_DCCISW, 0), value);
|
||||
if (retval != ERROR_OK)
|
||||
goto done;
|
||||
c_way -= 1;
|
||||
} while (c_way >= 0);
|
||||
c_index -= 1;
|
||||
} while (c_index >= 0);
|
||||
|
||||
done:
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int armv8_cache_d_inner_clean_inval_all(struct armv8_common *armv8)
|
||||
{
|
||||
struct armv8_cache_common *cache = &(armv8->armv8_mmu.armv8_cache);
|
||||
struct arm_dpm *dpm = armv8->arm.dpm;
|
||||
int cl;
|
||||
int retval;
|
||||
|
||||
retval = armv8_d_cache_sanity_check(armv8);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
retval = dpm->prepare(dpm);
|
||||
if (retval != ERROR_OK)
|
||||
goto done;
|
||||
|
||||
for (cl = 0; cl < cache->loc; cl++) {
|
||||
/* skip i-only caches */
|
||||
if (cache->arch[cl].ctype < CACHE_LEVEL_HAS_D_CACHE)
|
||||
continue;
|
||||
|
||||
armv8_cache_d_inner_flush_level(dpm, &cache->arch[cl].d_u_size, cl);
|
||||
}
|
||||
|
||||
retval = dpm->finish(dpm);
|
||||
return retval;
|
||||
|
||||
done:
|
||||
LOG_ERROR("clean invalidate failed");
|
||||
dpm->finish(dpm);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
int armv8_cache_d_inner_flush_virt(struct armv8_common *armv8, target_addr_t va, size_t size)
|
||||
{
|
||||
struct arm_dpm *dpm = armv8->arm.dpm;
|
||||
struct armv8_cache_common *armv8_cache = &armv8->armv8_mmu.armv8_cache;
|
||||
uint64_t linelen = armv8_cache->d_u_size.linelen;
|
||||
uint64_t linelen = armv8_cache->dminline;
|
||||
target_addr_t va_line, va_end;
|
||||
int retval;
|
||||
|
||||
|
|
@ -87,7 +153,7 @@ int armv8_cache_i_inner_inval_virt(struct armv8_common *armv8, target_addr_t va,
|
|||
{
|
||||
struct arm_dpm *dpm = armv8->arm.dpm;
|
||||
struct armv8_cache_common *armv8_cache = &armv8->armv8_mmu.armv8_cache;
|
||||
uint64_t linelen = armv8_cache->i_size.linelen;
|
||||
uint64_t linelen = armv8_cache->iminline;
|
||||
target_addr_t va_line, va_end;
|
||||
int retval;
|
||||
|
||||
|
|
@ -120,3 +186,232 @@ done:
|
|||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int armv8_handle_inner_cache_info_command(struct command_context *cmd_ctx,
|
||||
struct armv8_cache_common *armv8_cache)
|
||||
{
|
||||
int cl;
|
||||
|
||||
if (armv8_cache->info == -1) {
|
||||
command_print(cmd_ctx, "cache not yet identified");
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
for (cl = 0; cl < armv8_cache->loc; cl++) {
|
||||
struct armv8_arch_cache *arch = &(armv8_cache->arch[cl]);
|
||||
|
||||
if (arch->ctype & 1) {
|
||||
command_print(cmd_ctx,
|
||||
"L%d I-Cache: linelen %" PRIi32
|
||||
", associativity %" PRIi32
|
||||
", nsets %" PRIi32
|
||||
", cachesize %" PRId32 " KBytes",
|
||||
cl+1,
|
||||
arch->i_size.linelen,
|
||||
arch->i_size.associativity,
|
||||
arch->i_size.nsets,
|
||||
arch->i_size.cachesize);
|
||||
}
|
||||
|
||||
if (arch->ctype >= 2) {
|
||||
command_print(cmd_ctx,
|
||||
"L%d D-Cache: linelen %" PRIi32
|
||||
", associativity %" PRIi32
|
||||
", nsets %" PRIi32
|
||||
", cachesize %" PRId32 " KBytes",
|
||||
cl+1,
|
||||
arch->d_u_size.linelen,
|
||||
arch->d_u_size.associativity,
|
||||
arch->d_u_size.nsets,
|
||||
arch->d_u_size.cachesize);
|
||||
}
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int _armv8_flush_all_data(struct target *target)
|
||||
{
|
||||
return armv8_cache_d_inner_clean_inval_all(target_to_armv8(target));
|
||||
}
|
||||
|
||||
static int armv8_flush_all_data(struct target *target)
|
||||
{
|
||||
int retval = ERROR_FAIL;
|
||||
/* check that armv8_cache is correctly identify */
|
||||
struct armv8_common *armv8 = target_to_armv8(target);
|
||||
if (armv8->armv8_mmu.armv8_cache.info == -1) {
|
||||
LOG_ERROR("trying to flush un-identified cache");
|
||||
return retval;
|
||||
}
|
||||
|
||||
if (target->smp) {
|
||||
/* look if all the other target have been flushed in order to flush level
|
||||
* 2 */
|
||||
struct target_list *head;
|
||||
struct target *curr;
|
||||
head = target->head;
|
||||
while (head != (struct target_list *)NULL) {
|
||||
curr = head->target;
|
||||
if (curr->state == TARGET_HALTED) {
|
||||
LOG_INFO("Wait flushing data l1 on core %" PRId32, curr->coreid);
|
||||
retval = _armv8_flush_all_data(curr);
|
||||
}
|
||||
head = head->next;
|
||||
}
|
||||
} else
|
||||
retval = _armv8_flush_all_data(target);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int get_cache_info(struct arm_dpm *dpm, int cl, int ct, uint32_t *cache_reg)
|
||||
{
|
||||
int retval = ERROR_OK;
|
||||
|
||||
/* select cache level */
|
||||
retval = dpm->instr_write_data_r0(dpm,
|
||||
ARMV8_MSR_GP(SYSTEM_CSSELR, 0),
|
||||
(cl << 1) | (ct == 1 ? 1 : 0));
|
||||
if (retval != ERROR_OK)
|
||||
goto done;
|
||||
|
||||
retval = dpm->instr_read_data_r0(dpm,
|
||||
ARMV8_MRS(SYSTEM_CCSIDR, 0),
|
||||
cache_reg);
|
||||
done:
|
||||
return retval;
|
||||
}
|
||||
|
||||
static struct armv8_cachesize decode_cache_reg(uint32_t cache_reg)
|
||||
{
|
||||
struct armv8_cachesize size;
|
||||
int i = 0;
|
||||
|
||||
size.linelen = 16 << (cache_reg & 0x7);
|
||||
size.associativity = ((cache_reg >> 3) & 0x3ff) + 1;
|
||||
size.nsets = ((cache_reg >> 13) & 0x7fff) + 1;
|
||||
size.cachesize = size.linelen * size.associativity * size.nsets / 1024;
|
||||
|
||||
/* compute info for set way operation on cache */
|
||||
size.index_shift = (cache_reg & 0x7) + 4;
|
||||
size.index = (cache_reg >> 13) & 0x7fff;
|
||||
size.way = ((cache_reg >> 3) & 0x3ff);
|
||||
|
||||
while (((size.way << i) & 0x80000000) == 0)
|
||||
i++;
|
||||
size.way_shift = i;
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
int armv8_identify_cache(struct armv8_common *armv8)
|
||||
{
|
||||
/* read cache descriptor */
|
||||
int retval = ERROR_FAIL;
|
||||
struct arm_dpm *dpm = armv8->arm.dpm;
|
||||
uint32_t csselr, clidr, ctr;
|
||||
uint32_t cache_reg;
|
||||
int cl, ctype;
|
||||
struct armv8_cache_common *cache = &(armv8->armv8_mmu.armv8_cache);
|
||||
|
||||
retval = dpm->prepare(dpm);
|
||||
if (retval != ERROR_OK)
|
||||
goto done;
|
||||
|
||||
/* retrieve CTR */
|
||||
retval = dpm->instr_read_data_r0(dpm, ARMV8_MRS(SYSTEM_CTR, 0), &ctr);
|
||||
if (retval != ERROR_OK)
|
||||
goto done;
|
||||
|
||||
cache->iminline = 4UL << (ctr & 0xf);
|
||||
cache->dminline = 4UL << ((ctr & 0xf0000) >> 16);
|
||||
LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRId32 " ctr.dminline %" PRId32,
|
||||
ctr, cache->iminline, cache->dminline);
|
||||
|
||||
/* retrieve CLIDR */
|
||||
retval = dpm->instr_read_data_r0(dpm, ARMV8_MRS(SYSTEM_CLIDR, 0), &clidr);
|
||||
if (retval != ERROR_OK)
|
||||
goto done;
|
||||
|
||||
cache->loc = (clidr & 0x7000000) >> 24;
|
||||
LOG_DEBUG("Number of cache levels to PoC %" PRId32, cache->loc);
|
||||
|
||||
/* retrieve selected cache for later restore
|
||||
* MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
|
||||
retval = dpm->instr_read_data_r0(dpm, ARMV8_MRS(SYSTEM_CSSELR, 0), &csselr);
|
||||
if (retval != ERROR_OK)
|
||||
goto done;
|
||||
|
||||
/* retrieve all available inner caches */
|
||||
for (cl = 0; cl < cache->loc; clidr >>= 3, cl++) {
|
||||
|
||||
/* isolate cache type at current level */
|
||||
ctype = clidr & 7;
|
||||
|
||||
/* skip reserved values */
|
||||
if (ctype > CACHE_LEVEL_HAS_UNIFIED_CACHE)
|
||||
continue;
|
||||
|
||||
/* separate d or unified d/i cache at this level ? */
|
||||
if (ctype & (CACHE_LEVEL_HAS_UNIFIED_CACHE | CACHE_LEVEL_HAS_D_CACHE)) {
|
||||
/* retrieve d-cache info */
|
||||
retval = get_cache_info(dpm, cl, 0, &cache_reg);
|
||||
if (retval != ERROR_OK)
|
||||
goto done;
|
||||
cache->arch[cl].d_u_size = decode_cache_reg(cache_reg);
|
||||
|
||||
LOG_DEBUG("data/unified cache index %d << %d, way %d << %d",
|
||||
cache->arch[cl].d_u_size.index,
|
||||
cache->arch[cl].d_u_size.index_shift,
|
||||
cache->arch[cl].d_u_size.way,
|
||||
cache->arch[cl].d_u_size.way_shift);
|
||||
|
||||
LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
|
||||
cache->arch[cl].d_u_size.linelen,
|
||||
cache->arch[cl].d_u_size.cachesize,
|
||||
cache->arch[cl].d_u_size.associativity);
|
||||
}
|
||||
|
||||
/* separate i-cache at this level ? */
|
||||
if (ctype & CACHE_LEVEL_HAS_I_CACHE) {
|
||||
/* retrieve i-cache info */
|
||||
retval = get_cache_info(dpm, cl, 1, &cache_reg);
|
||||
if (retval != ERROR_OK)
|
||||
goto done;
|
||||
cache->arch[cl].i_size = decode_cache_reg(cache_reg);
|
||||
|
||||
LOG_DEBUG("instruction cache index %d << %d, way %d << %d",
|
||||
cache->arch[cl].i_size.index,
|
||||
cache->arch[cl].i_size.index_shift,
|
||||
cache->arch[cl].i_size.way,
|
||||
cache->arch[cl].i_size.way_shift);
|
||||
|
||||
LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
|
||||
cache->arch[cl].i_size.linelen,
|
||||
cache->arch[cl].i_size.cachesize,
|
||||
cache->arch[cl].i_size.associativity);
|
||||
}
|
||||
|
||||
cache->arch[cl].ctype = ctype;
|
||||
}
|
||||
|
||||
/* restore selected cache */
|
||||
dpm->instr_write_data_r0(dpm, ARMV8_MSR_GP(SYSTEM_CSSELR, 0), csselr);
|
||||
if (retval != ERROR_OK)
|
||||
goto done;
|
||||
|
||||
armv8->armv8_mmu.armv8_cache.info = 1;
|
||||
|
||||
/* if no l2 cache initialize l1 data cache flush function function */
|
||||
if (armv8->armv8_mmu.armv8_cache.flush_all_data_cache == NULL) {
|
||||
armv8->armv8_mmu.armv8_cache.display_cache_info =
|
||||
armv8_handle_inner_cache_info_command;
|
||||
armv8->armv8_mmu.armv8_cache.flush_all_data_cache =
|
||||
armv8_flush_all_data;
|
||||
}
|
||||
|
||||
done:
|
||||
dpm->finish(dpm);
|
||||
return retval;
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -77,6 +77,7 @@
|
|||
#define SYSTEM_CLIDR 0b1100100000000001
|
||||
#define SYSTEM_CSSELR 0b1101000000000000
|
||||
#define SYSTEM_CTYPE 0b1101100000000001
|
||||
#define SYSTEM_CTR 0b1101100000000001
|
||||
|
||||
#define SYSTEM_DCCISW 0b0100001111110010
|
||||
#define SYSTEM_DCCSW 0b0100001111010010
|
||||
|
|
|
|||
Loading…
Reference in New Issue