parent
6f1a498ab9
commit
b4d38d0997
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@ -34,24 +34,6 @@
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#define DIM(x) (sizeof(x)/sizeof(*x))
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// Constants for legacy SiFive hardware breakpoints.
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#define CSR_BPCONTROL_X (1<<0)
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#define CSR_BPCONTROL_W (1<<1)
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#define CSR_BPCONTROL_R (1<<2)
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#define CSR_BPCONTROL_U (1<<3)
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#define CSR_BPCONTROL_S (1<<4)
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#define CSR_BPCONTROL_H (1<<5)
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#define CSR_BPCONTROL_M (1<<6)
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#define CSR_BPCONTROL_BPMATCH (0xf<<7)
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#define CSR_BPCONTROL_BPACTION (0xff<<11)
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#define DEBUG_ROM_START 0x800
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#define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
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#define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
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#define DEBUG_RAM_START 0x400
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#define SETHALTNOT 0x10c
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#define CSR_DCSR_CAUSE_SWBP 1
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#define CSR_DCSR_CAUSE_TRIGGER 2
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#define CSR_DCSR_CAUSE_DEBUGINT 3
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@ -60,9 +42,6 @@
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/*** JTAG registers. ***/
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#define DBUS 0x11
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#define DMI_OP_START 0
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#define DMI_OP_SIZE 2
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typedef enum {
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DMI_OP_NOP = 0,
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DMI_OP_READ = 1,
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@ -73,9 +52,6 @@ typedef enum {
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DMI_STATUS_FAILED = 2,
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DMI_STATUS_BUSY = 3
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} dmi_status_t;
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#define DMI_DATA_START 2
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#define DMI_DATA_SIZE 32
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#define DMI_ADDRESS_START 34
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typedef enum {
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RE_OK,
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@ -91,17 +67,6 @@ typedef enum slot {
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/*** Debug Bus registers. ***/
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#define DMCONTROL 0x10
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#define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
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#define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
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#define DMCONTROL_BUSERROR (7<<19)
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#define DMCONTROL_SERIAL (3<<16)
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#define DMCONTROL_AUTOINCREMENT (1<<15)
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#define DMCONTROL_ACCESS (7<<12)
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#define DMCONTROL_HARTID (0x3ff<<2)
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#define DMCONTROL_NDRESET (1<<1)
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#define DMCONTROL_FULLRESET 1
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#define CMDERR_NONE 0
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#define CMDERR_BUSY 1
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#define CMDERR_NOT_SUPPORTED 2
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@ -111,7 +76,6 @@ typedef enum slot {
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/*** Info about the core being debugged. ***/
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#define DMI_ADDRESS_UNKNOWN 0xffff
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#define WALL_CLOCK_TIMEOUT 2
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// gdb's register list is defined in riscv_gdb_reg_names gdb/riscv-tdep.c in
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@ -318,15 +282,15 @@ static void scans_add_dmi_write(scans_t *scans, unsigned address,
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struct scan_field *field = scans->field + i;
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uint8_t *out = scans->out + data_offset;
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field->num_bits = info->abits + DMI_OP_SIZE + DMI_DATA_SIZE;
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field->num_bits = info->abits + DTM_DMI_OP_LENGTH + DTM_DMI_DATA_LENGTH;
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// We gain a lot of speed in remote bitbang by not looking at the return
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// value.
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field->in_value = NULL;
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field->out_value = out;
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buf_set_u64(out, DMI_OP_START, DMI_OP_SIZE, DMI_OP_WRITE);
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buf_set_u64(out, DMI_DATA_START, DMI_DATA_SIZE, value);
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buf_set_u64(out, DMI_ADDRESS_START, info->abits, address);
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buf_set_u64(out, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_WRITE);
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buf_set_u64(out, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, value);
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buf_set_u64(out, DTM_DMI_ADDRESS_OFFSET, info->abits, address);
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/* Assume dbus is already selected. */
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jtag_add_dr_scan(scans->target->tap, 1, field, TAP_IDLE);
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@ -468,7 +432,7 @@ static dmi_status_t dmi_scan(struct target *target, uint16_t *address_in,
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uint8_t in[8] = {0};
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uint8_t out[8];
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struct scan_field field = {
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.num_bits = info->abits + DMI_OP_SIZE + DMI_DATA_SIZE,
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.num_bits = info->abits + DTM_DMI_OP_LENGTH + DTM_DMI_DATA_LENGTH,
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.out_value = out,
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};
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@ -478,9 +442,9 @@ static dmi_status_t dmi_scan(struct target *target, uint16_t *address_in,
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assert(info->abits != 0);
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buf_set_u64(out, DMI_OP_START, DMI_OP_SIZE, op);
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buf_set_u64(out, DMI_DATA_START, DMI_DATA_SIZE, data_out);
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buf_set_u64(out, DMI_ADDRESS_START, info->abits, address_out);
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buf_set_u64(out, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, op);
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buf_set_u64(out, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, data_out);
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buf_set_u64(out, DTM_DMI_ADDRESS_OFFSET, info->abits, address_out);
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/* Assume dbus is already selected. */
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jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
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@ -500,16 +464,16 @@ static dmi_status_t dmi_scan(struct target *target, uint16_t *address_in,
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}
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if (data_in) {
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*data_in = buf_get_u64(in, DMI_DATA_START, DMI_DATA_SIZE);
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*data_in = buf_get_u64(in, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH);
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}
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if (address_in) {
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*address_in = buf_get_u32(in, DMI_ADDRESS_START, info->abits);
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*address_in = buf_get_u32(in, DTM_DMI_ADDRESS_OFFSET, info->abits);
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}
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dump_field(&field);
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return buf_get_u32(in, DMI_OP_START, DMI_OP_SIZE);
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return buf_get_u32(in, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH);
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}
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static uint64_t dmi_read(struct target *target, uint16_t address)
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