Added support for STM32L4X option bytes writing.
Enables the programming of Write protection lock bits. - Updated/re-factored with option_read, option_write and option_load commands. Change-Id: I86358c7eb1285c3c0baac1564e46da8ced5fd025 Signed-off-by: Thomas Søhus <tls@ceepro.dk> Reviewed-on: http://openocd.zylin.com/4654 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>bscan_tunnel
Thomas Søhus
Tomas Vanek
parent
4423a58b4d
commit
b2d259f67c
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@ -6596,6 +6596,42 @@ The @var{num} parameter is a value shown by @command{flash banks}.
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Mass erases the entire stm32l4x device.
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The @var{num} parameter is a value shown by @command{flash banks}.
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@end deffn
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@deffn Command {stm32l4x option_read} num reg_offset
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Reads an option byte register from the stm32l4x device.
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The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
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is the register offset of the Option byte to read.
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For example to read the FLASH_OPTR register:
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@example
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stm32l4x option_read 0 0x20
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# Option Register: <0x40022020> = 0xffeff8aa
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@end example
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The above example will read out the FLASH_OPTR register which contains the RDP
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option byte, Watchdog configuration, BOR level etc.
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@end deffn
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@deffn Command {stm32l4x option_write} num reg_offset reg_mask
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Write an option byte register of the stm32l4x device.
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The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
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is the register offset of the Option byte to write, and @var{reg_mask} is the mask
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to apply when writing the register (only bits with a '1' will be touched).
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For example to write the WRP1AR option bytes:
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@example
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stm32l4x option_write 0 0x28 0x00FF0000 0x00FF00FF
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@end example
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The above example will write the WRP1AR option register configuring the Write protection
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Area A for bank 1. The above example set WRP1AR_END=255, WRP1AR_START=0.
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This will effectively write protect all sectors in flash bank 1.
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@end deffn
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@deffn Command {stm32l4x option_load} num
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Forces a re-load of the option byte registers. Will cause a reset of the device.
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The @var{num} parameter is a value shown by @command{flash banks}.
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@end deffn
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@end deffn
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@deffn {Flash Driver} str7x
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@ -57,8 +57,8 @@
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#define STM32_FLASH_CR 0x40022014
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#define STM32_FLASH_OPTR 0x40022020
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#define STM32_FLASH_WRP1AR 0x4002202c
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#define STM32_FLASH_WRP2AR 0x40022030
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#define STM32_FLASH_WRP1BR 0x4002204c
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#define STM32_FLASH_WRP1BR 0x40022030
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#define STM32_FLASH_WRP2AR 0x4002204c
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#define STM32_FLASH_WRP2BR 0x40022050
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/* FLASH_CR register bits */
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@ -70,8 +70,10 @@
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#define FLASH_CR_BKER (1 << 11)
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#define FLASH_MER2 (1 << 15)
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#define FLASH_STRT (1 << 16)
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#define FLASH_OPTSTRT (1 << 17)
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#define FLASH_EOPIE (1 << 24)
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#define FLASH_ERRIE (1 << 25)
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#define FLASH_OBLLAUNCH (1 << 27)
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#define FLASH_OPTLOCK (1 << 30)
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#define FLASH_LOCK (1 << 31)
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@ -102,28 +104,17 @@
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#define OPTKEY1 0x08192A3B
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#define OPTKEY2 0x4C5D6E7F
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#define RDP_LEVEL_0 0xAA
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#define RDP_LEVEL_1 0xBB
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#define RDP_LEVEL_2 0xCC
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/* other registers */
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#define DBGMCU_IDCODE 0xE0042000
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#define FLASH_SIZE_REG 0x1FFF75E0
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struct stm32l4_options {
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uint8_t RDP;
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uint16_t bank_b_start;
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uint8_t user_options;
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uint8_t wpr1a_start;
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uint8_t wpr1a_end;
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uint8_t wpr1b_start;
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uint8_t wpr1b_end;
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uint8_t wpr2a_start;
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uint8_t wpr2a_end;
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uint8_t wpr2b_start;
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uint8_t wpr2b_end;
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/* Fixme: Handle PCROP */
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};
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struct stm32l4_flash_bank {
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struct stm32l4_options option_bytes;
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uint16_t bank2_start;
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int probed;
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};
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@ -265,97 +256,80 @@ static int stm32l4_unlock_option_reg(struct target *target)
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return ERROR_OK;
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}
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static int stm32l4_read_options(struct flash_bank *bank)
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static int stm32l4_read_option(struct flash_bank *bank, uint32_t address, uint32_t* value)
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{
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uint32_t optiondata;
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struct stm32l4_flash_bank *stm32l4_info = NULL;
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struct target *target = bank->target;
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stm32l4_info = bank->driver_priv;
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/* read current option bytes */
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int retval = target_read_u32(target, STM32_FLASH_OPTR, &optiondata);
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if (retval != ERROR_OK)
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return retval;
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stm32l4_info->option_bytes.user_options = (optiondata >> 8) & 0x3ffff;
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stm32l4_info->option_bytes.RDP = optiondata & 0xff;
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retval = target_read_u32(target, STM32_FLASH_WRP1AR, &optiondata);
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if (retval != ERROR_OK)
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return retval;
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stm32l4_info->option_bytes.wpr1a_start = optiondata & 0xff;
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stm32l4_info->option_bytes.wpr1a_end = (optiondata >> 16) & 0xff;
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retval = target_read_u32(target, STM32_FLASH_WRP2AR, &optiondata);
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if (retval != ERROR_OK)
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return retval;
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stm32l4_info->option_bytes.wpr2a_start = optiondata & 0xff;
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stm32l4_info->option_bytes.wpr2a_end = (optiondata >> 16) & 0xff;
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retval = target_read_u32(target, STM32_FLASH_WRP1BR, &optiondata);
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if (retval != ERROR_OK)
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return retval;
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stm32l4_info->option_bytes.wpr1b_start = optiondata & 0xff;
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stm32l4_info->option_bytes.wpr1b_end = (optiondata >> 16) & 0xff;
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retval = target_read_u32(target, STM32_FLASH_WRP2BR, &optiondata);
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if (retval != ERROR_OK)
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return retval;
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stm32l4_info->option_bytes.wpr2b_start = optiondata & 0xff;
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stm32l4_info->option_bytes.wpr2b_end = (optiondata >> 16) & 0xff;
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if (stm32l4_info->option_bytes.RDP != 0xAA)
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LOG_INFO("Device Security Bit Set");
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return ERROR_OK;
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return target_read_u32(target, address, value);
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}
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static int stm32l4_write_options(struct flash_bank *bank)
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static int stm32l4_write_option(struct flash_bank *bank, uint32_t address, uint32_t value, uint32_t mask)
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{
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struct stm32l4_flash_bank *stm32l4_info = NULL;
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struct target *target = bank->target;
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uint32_t optiondata;
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stm32l4_info = bank->driver_priv;
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(void) optiondata;
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(void) stm32l4_info;
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int retval = stm32l4_unlock_option_reg(target);
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int retval = target_read_u32(target, address, &optiondata);
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if (retval != ERROR_OK)
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return retval;
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/* FIXME: Implement Option writing!*/
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return ERROR_OK;
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retval = stm32l4_unlock_reg(target);
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if (retval != ERROR_OK)
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return retval;
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retval = stm32l4_unlock_option_reg(target);
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if (retval != ERROR_OK)
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return retval;
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optiondata = (optiondata & ~mask) | (value & mask);
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retval = target_write_u32(target, address, optiondata);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u32(target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OPTSTRT);
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if (retval != ERROR_OK)
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return retval;
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retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
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if (retval != ERROR_OK)
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return retval;
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return retval;
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}
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static int stm32l4_protect_check(struct flash_bank *bank)
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{
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struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
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uint32_t wrp1ar, wrp1br, wrp2ar, wrp2br;
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stm32l4_read_option(bank, STM32_FLASH_WRP1AR, &wrp1ar);
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stm32l4_read_option(bank, STM32_FLASH_WRP1BR, &wrp1br);
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stm32l4_read_option(bank, STM32_FLASH_WRP2AR, &wrp2ar);
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stm32l4_read_option(bank, STM32_FLASH_WRP2BR, &wrp2br);
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/* read write protection settings */
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int retval = stm32l4_read_options(bank);
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if (retval != ERROR_OK) {
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LOG_DEBUG("unable to read option bytes");
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return retval;
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}
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const uint8_t wrp1a_start = wrp1ar & 0xFF;
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const uint8_t wrp1a_end = (wrp1ar >> 16) & 0xFF;
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const uint8_t wrp1b_start = wrp1br & 0xFF;
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const uint8_t wrp1b_end = (wrp1br >> 16) & 0xFF;
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const uint8_t wrp2a_start = wrp2ar & 0xFF;
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const uint8_t wrp2a_end = (wrp2ar >> 16) & 0xFF;
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const uint8_t wrp2b_start = wrp2br & 0xFF;
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const uint8_t wrp2b_end = (wrp2br >> 16) & 0xFF;
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for (int i = 0; i < bank->num_sectors; i++) {
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if (i < stm32l4_info->option_bytes.bank_b_start) {
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if (((i >= stm32l4_info->option_bytes.wpr1a_start) &&
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(i <= stm32l4_info->option_bytes.wpr1a_end)) ||
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((i >= stm32l4_info->option_bytes.wpr2a_start) &&
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(i <= stm32l4_info->option_bytes.wpr2a_end)))
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if (i < stm32l4_info->bank2_start) {
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if (((i >= wrp1a_start) &&
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(i <= wrp1a_end)) ||
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((i >= wrp1b_start) &&
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(i <= wrp1b_end)))
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bank->sectors[i].is_protected = 1;
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else
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bank->sectors[i].is_protected = 0;
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} else {
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uint8_t snb;
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snb = i - stm32l4_info->option_bytes.bank_b_start + 256;
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if (((snb >= stm32l4_info->option_bytes.wpr1b_start) &&
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(snb <= stm32l4_info->option_bytes.wpr1b_end)) ||
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((snb >= stm32l4_info->option_bytes.wpr2b_start) &&
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(snb <= stm32l4_info->option_bytes.wpr2b_end)))
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snb = i - stm32l4_info->bank2_start + 256;
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if (((snb >= wrp2a_start) &&
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(snb <= wrp2a_end)) ||
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((snb >= wrp2b_start) &&
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(snb <= wrp2b_end)))
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bank->sectors[i].is_protected = 1;
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else
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bank->sectors[i].is_protected = 0;
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@ -398,9 +372,9 @@ static int stm32l4_erase(struct flash_bank *bank, int first, int last)
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uint32_t erase_flags;
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erase_flags = FLASH_PER | FLASH_STRT;
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if (i >= stm32l4_info->option_bytes.bank_b_start) {
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if (i >= stm32l4_info->bank2_start) {
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uint8_t snb;
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snb = (i - stm32l4_info->option_bytes.bank_b_start) + 256;
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snb = (i - stm32l4_info->bank2_start) + 256;
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erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER;
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} else
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erase_flags |= i << FLASH_PAGE_SHIFT;
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@ -434,20 +408,29 @@ static int stm32l4_protect(struct flash_bank *bank, int set, int first, int last
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return ERROR_TARGET_NOT_HALTED;
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}
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/* read protection settings */
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int retval = stm32l4_read_options(bank);
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if (retval != ERROR_OK) {
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LOG_DEBUG("unable to read option bytes");
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return retval;
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int ret = ERROR_OK;
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/* Bank 2 */
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uint32_t reg_value = 0xFF; /* Default to bank un-protected */
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if (last >= stm32l4_info->bank2_start) {
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if (set == 1) {
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uint8_t begin = first > stm32l4_info->bank2_start ? first : 0x00;
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reg_value = ((last & 0xFF) << 16) | begin;
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}
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(void)stm32l4_info;
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/* FIXME: Write First and last in a valid WRPxx_start/end combo*/
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retval = stm32l4_write_options(bank);
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if (retval != ERROR_OK)
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return retval;
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ret = stm32l4_write_option(bank, STM32_FLASH_WRP2AR, reg_value, 0xffffffff);
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}
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/* Bank 1 */
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reg_value = 0xFF; /* Default to bank un-protected */
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if (first < stm32l4_info->bank2_start) {
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if (set == 1) {
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uint8_t end = last >= stm32l4_info->bank2_start ? 0xFF : last;
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reg_value = (end << 16) | (first & 0xFF);
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}
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return ERROR_OK;
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ret = stm32l4_write_option(bank, STM32_FLASH_WRP1AR, reg_value, 0xffffffff);
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}
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return ret;
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}
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/* Count is in halfwords */
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@ -650,9 +633,9 @@ static int stm32l4_probe(struct flash_bank *bank)
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/* only devices with < 1024 kiB may be set to single bank dual banks */
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if ((flash_size_in_kb == 1024) || !(options & OPT_DUALBANK))
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stm32l4_info->option_bytes.bank_b_start = 256;
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stm32l4_info->bank2_start = 256;
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else
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stm32l4_info->option_bytes.bank_b_start = flash_size_in_kb << 9;
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stm32l4_info->bank2_start = flash_size_in_kb << 9;
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/* did we assign flash size? */
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assert((flash_size_in_kb != 0xffff) && flash_size_in_kb);
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@ -747,89 +730,6 @@ static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size)
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return ERROR_OK;
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}
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COMMAND_HANDLER(stm32l4_handle_lock_command)
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{
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struct target *target = NULL;
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struct stm32l4_flash_bank *stm32l4_info = NULL;
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if (CMD_ARGC < 1)
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return ERROR_COMMAND_SYNTAX_ERROR;
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struct flash_bank *bank;
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int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
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if (ERROR_OK != retval)
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return retval;
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stm32l4_info = bank->driver_priv;
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target = bank->target;
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if (target->state != TARGET_HALTED) {
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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if (stm32l4_read_options(bank) != ERROR_OK) {
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command_print(CMD_CTX, "%s failed to read options",
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bank->driver->name);
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return ERROR_OK;
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}
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/* set readout protection */
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stm32l4_info->option_bytes.RDP = 0;
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if (stm32l4_write_options(bank) != ERROR_OK) {
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command_print(CMD_CTX, "%s failed to lock device", bank->driver->name);
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return ERROR_OK;
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}
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command_print(CMD_CTX, "%s locked", bank->driver->name);
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return ERROR_OK;
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}
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COMMAND_HANDLER(stm32l4_handle_unlock_command)
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{
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struct target *target = NULL;
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struct stm32l4_flash_bank *stm32l4_info = NULL;
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if (CMD_ARGC < 1)
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return ERROR_COMMAND_SYNTAX_ERROR;
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struct flash_bank *bank;
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int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
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if (ERROR_OK != retval)
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return retval;
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stm32l4_info = bank->driver_priv;
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target = bank->target;
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if (target->state != TARGET_HALTED) {
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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if (stm32l4_read_options(bank) != ERROR_OK) {
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command_print(CMD_CTX, "%s failed to read options", bank->driver->name);
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return ERROR_OK;
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}
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/* clear readout protection and complementary option bytes
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* this will also force a device unlock if set */
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stm32l4_info->option_bytes.RDP = 0xAA;
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if (stm32l4_write_options(bank) != ERROR_OK) {
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command_print(CMD_CTX, "%s failed to unlock device",
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bank->driver->name);
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return ERROR_OK;
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}
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command_print(CMD_CTX, "%s unlocked.\n"
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"INFO: a reset or power cycle is required "
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"for the new settings to take effect.", bank->driver->name);
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return ERROR_OK;
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}
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static int stm32l4_mass_erase(struct flash_bank *bank, uint32_t action)
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||||
{
|
||||
int retval;
|
||||
|
|
@ -873,7 +773,7 @@ COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
|
|||
uint32_t action;
|
||||
|
||||
if (CMD_ARGC < 1) {
|
||||
command_print(CMD_CTX, "stm32x mass_erase <STM32L4 bank>");
|
||||
command_print(CMD_CTX, "stm32l4x mass_erase <STM32L4 bank>");
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
}
|
||||
|
||||
|
|
@ -889,14 +789,151 @@ COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
|
|||
for (i = 0; i < bank->num_sectors; i++)
|
||||
bank->sectors[i].is_erased = 1;
|
||||
|
||||
command_print(CMD_CTX, "stm32x mass erase complete");
|
||||
command_print(CMD_CTX, "stm32l4x mass erase complete");
|
||||
} else {
|
||||
command_print(CMD_CTX, "stm32x mass erase failed");
|
||||
command_print(CMD_CTX, "stm32l4x mass erase failed");
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
COMMAND_HANDLER(stm32l4_handle_option_read_command)
|
||||
{
|
||||
if (CMD_ARGC < 2) {
|
||||
command_print(CMD_CTX, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
}
|
||||
|
||||
struct flash_bank *bank;
|
||||
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
|
||||
if (ERROR_OK != retval)
|
||||
return retval;
|
||||
|
||||
uint32_t reg_addr = STM32_FLASH_BASE;
|
||||
uint32_t value = 0;
|
||||
|
||||
reg_addr += strtoul(CMD_ARGV[1], NULL, 16);
|
||||
|
||||
retval = stm32l4_read_option(bank, reg_addr, &value);
|
||||
if (ERROR_OK != retval)
|
||||
return retval;
|
||||
|
||||
command_print(CMD_CTX, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
COMMAND_HANDLER(stm32l4_handle_option_write_command)
|
||||
{
|
||||
if (CMD_ARGC < 3) {
|
||||
command_print(CMD_CTX, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
}
|
||||
|
||||
struct flash_bank *bank;
|
||||
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
|
||||
if (ERROR_OK != retval)
|
||||
return retval;
|
||||
|
||||
uint32_t reg_addr = STM32_FLASH_BASE;
|
||||
uint32_t value = 0;
|
||||
uint32_t mask = 0xFFFFFFFF;
|
||||
|
||||
reg_addr += strtoul(CMD_ARGV[1], NULL, 16);
|
||||
value = strtoul(CMD_ARGV[2], NULL, 16);
|
||||
if (CMD_ARGC > 3)
|
||||
mask = strtoul(CMD_ARGV[3], NULL, 16);
|
||||
|
||||
command_print(CMD_CTX, "%s Option written.\n"
|
||||
"INFO: a reset or power cycle is required "
|
||||
"for the new settings to take effect.", bank->driver->name);
|
||||
|
||||
retval = stm32l4_write_option(bank, reg_addr, value, mask);
|
||||
return retval;
|
||||
}
|
||||
|
||||
COMMAND_HANDLER(stm32l4_handle_option_load_command)
|
||||
{
|
||||
if (CMD_ARGC < 1)
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
|
||||
struct flash_bank *bank;
|
||||
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
|
||||
if (ERROR_OK != retval)
|
||||
return retval;
|
||||
|
||||
struct target *target = bank->target;
|
||||
|
||||
retval = stm32l4_unlock_reg(target);
|
||||
if (ERROR_OK != retval)
|
||||
return retval;
|
||||
|
||||
retval = stm32l4_unlock_option_reg(target);
|
||||
if (ERROR_OK != retval)
|
||||
return retval;
|
||||
|
||||
/* Write the OBLLAUNCH bit in CR -> Cause device "POR" and option bytes reload */
|
||||
retval = target_write_u32(target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBLLAUNCH);
|
||||
|
||||
command_print(CMD_CTX, "stm32l4x option load (POR) completed.");
|
||||
return retval;
|
||||
}
|
||||
|
||||
COMMAND_HANDLER(stm32l4_handle_lock_command)
|
||||
{
|
||||
struct target *target = NULL;
|
||||
|
||||
if (CMD_ARGC < 1)
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
|
||||
struct flash_bank *bank;
|
||||
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
|
||||
if (ERROR_OK != retval)
|
||||
return retval;
|
||||
|
||||
target = bank->target;
|
||||
|
||||
if (target->state != TARGET_HALTED) {
|
||||
LOG_ERROR("Target not halted");
|
||||
return ERROR_TARGET_NOT_HALTED;
|
||||
}
|
||||
|
||||
/* set readout protection level 1 by erasing the RDP option byte */
|
||||
if (stm32l4_write_option(bank, STM32_FLASH_OPTR, 0, 0x000000FF) != ERROR_OK) {
|
||||
command_print(CMD_CTX, "%s failed to lock device", bank->driver->name);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
COMMAND_HANDLER(stm32l4_handle_unlock_command)
|
||||
{
|
||||
struct target *target = NULL;
|
||||
|
||||
if (CMD_ARGC < 1)
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
|
||||
struct flash_bank *bank;
|
||||
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
|
||||
if (ERROR_OK != retval)
|
||||
return retval;
|
||||
|
||||
target = bank->target;
|
||||
|
||||
if (target->state != TARGET_HALTED) {
|
||||
LOG_ERROR("Target not halted");
|
||||
return ERROR_TARGET_NOT_HALTED;
|
||||
}
|
||||
|
||||
if (stm32l4_write_option(bank, STM32_FLASH_OPTR, RDP_LEVEL_0, 0x000000FF) != ERROR_OK) {
|
||||
command_print(CMD_CTX, "%s failed to unlock device", bank->driver->name);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static const struct command_registration stm32l4_exec_command_handlers[] = {
|
||||
{
|
||||
.name = "lock",
|
||||
|
|
@ -919,6 +956,27 @@ static const struct command_registration stm32l4_exec_command_handlers[] = {
|
|||
.usage = "bank_id",
|
||||
.help = "Erase entire flash device.",
|
||||
},
|
||||
{
|
||||
.name = "option_read",
|
||||
.handler = stm32l4_handle_option_read_command,
|
||||
.mode = COMMAND_EXEC,
|
||||
.usage = "bank_id reg_offset",
|
||||
.help = "Read & Display device option bytes.",
|
||||
},
|
||||
{
|
||||
.name = "option_write",
|
||||
.handler = stm32l4_handle_option_write_command,
|
||||
.mode = COMMAND_EXEC,
|
||||
.usage = "bank_id reg_offset value mask",
|
||||
.help = "Write device option bit fields with provided value.",
|
||||
},
|
||||
{
|
||||
.name = "option_load",
|
||||
.handler = stm32l4_handle_option_load_command,
|
||||
.mode = COMMAND_EXEC,
|
||||
.usage = "bank_id",
|
||||
.help = "Force re-load of device options (will cause device reset).",
|
||||
},
|
||||
COMMAND_REGISTRATION_DONE
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue