tcl/target/imx6: add yet another SJC tapid

This is for mx6q TO1.1.

Change-Id: Id6af2ed232fc19be9bf49eb6d2df0004c6668698
Reported-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2253
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
__archive__
Paul Fertser 2014-08-15 20:34:35 +04:00 committed by Andreas Fritiofson
parent f8318d1b0d
commit b171c7ab16
1 changed files with 2 additions and 1 deletions

View File

@ -27,10 +27,11 @@ if { [info exists SJC_TAPID] } {
} }
set _SJC_TAPID2 0x2191c01d set _SJC_TAPID2 0x2191c01d
set _SJC_TAPID3 0x2191e01d set _SJC_TAPID3 0x2191e01d
set _SJC_TAPID4 0x1191c01d
jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \ jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
-expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2 \ -expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2 \
-expected-id $_SJC_TAPID3 -expected-id $_SJC_TAPID3 -expected-id $_SJC_TAPID4
# GDB target: Cortex-A9, using DAP, configuring only one core # GDB target: Cortex-A9, using DAP, configuring only one core
# Base addresses of cores: # Base addresses of cores: