Make it all the way through examine().
This includes reading GPRs (although I haven't confirmed the values) and doing some CSR reading/writing to disable triggers that may be left over from a previous setting. Change-Id: I2c627bd002d601e302a40f838087541897c025fd__archive__
Tim Newsome
parent
00925574d5
commit
ae4fda2719
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@ -265,20 +265,6 @@ static unsigned int slot_offset(const struct target *target, slot_t slot)
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assert(0);
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}
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static uint32_t load_slot(const struct target *target, unsigned int dest,
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slot_t slot)
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{
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unsigned int offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
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return load(target, dest, ZERO, offset);
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}
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static uint32_t store_slot(const struct target *target, unsigned int src,
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slot_t slot)
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{
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unsigned int offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
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return store(target, src, ZERO, offset);
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}
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static uint16_t dram_address(unsigned int index)
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{
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if (index < 0x10)
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@ -594,34 +580,6 @@ static void scans_add_write32(scans_t *scans, uint16_t address, uint32_t data,
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assert(scans->next_scan <= scans->scan_count);
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}
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/** Add a 32-bit dbus write for an instruction that jumps to the beginning of
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* debug RAM. */
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static void scans_add_write_jump(scans_t *scans, uint16_t address,
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bool set_interrupt)
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{
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scans_add_write32(scans, address,
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jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*address))),
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set_interrupt);
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}
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/** Add a 32-bit dbus write for an instruction that loads from the indicated
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* slot. */
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static void scans_add_write_load(scans_t *scans, uint16_t address,
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unsigned int reg, slot_t slot, bool set_interrupt)
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{
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scans_add_write32(scans, address, load_slot(scans->target, reg, slot),
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set_interrupt);
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}
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/** Add a 32-bit dbus write for an instruction that stores to the indicated
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* slot. */
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static void scans_add_write_store(scans_t *scans, uint16_t address,
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unsigned int reg, slot_t slot, bool set_interrupt)
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{
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scans_add_write32(scans, address, store_slot(scans->target, reg, slot),
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set_interrupt);
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}
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/** Add a 32-bit dbus read. */
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static void scans_add_read32(scans_t *scans, uint16_t address, bool set_interrupt)
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{
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@ -634,21 +592,6 @@ static void scans_add_read32(scans_t *scans, uint16_t address, bool set_interrup
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scans->next_scan++;
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}
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/** Add one or more scans to read the indicated slot. */
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static void scans_add_read(scans_t *scans, slot_t slot, bool set_interrupt)
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{
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const struct target *target = scans->target;
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switch (xlen(target)) {
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case 32:
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scans_add_read32(scans, slot_offset(target, slot), set_interrupt);
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break;
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case 64:
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scans_add_read32(scans, slot_offset(target, slot), false);
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scans_add_read32(scans, slot_offset(target, slot) + 1, set_interrupt);
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break;
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}
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}
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static uint32_t scans_get_u32(scans_t *scans, unsigned int index,
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unsigned first, unsigned num)
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{
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@ -776,6 +719,13 @@ static void program_set_read(program_t *program, unsigned reg_num)
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program->regno = reg_number_to_no(reg_num);
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}
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static void program_set_write(program_t *program, unsigned reg_num, uint64_t value)
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{
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program->write = true;
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program->regno = reg_number_to_no(reg_num);
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program->write_value = value;
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}
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/*** end of program class ***/
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static uint32_t dram_read32(struct target *target, unsigned int index)
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@ -1124,6 +1074,10 @@ static int execute_program(struct target *target, const program_t *program)
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uint32_t command = 0;
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if (program->write) {
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if (get_field(command, AC_ACCESS_REGISTER_SIZE) > 2) {
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dmi_write(target, DMI_DATA1, program->write_value >> 32);
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}
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dmi_write(target, DMI_DATA0, program->write_value);
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command |= AC_ACCESS_REGISTER_WRITE | AC_ACCESS_REGISTER_POSTEXEC;
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} else {
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command |= AC_ACCESS_REGISTER_PREEXEC;
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@ -1152,9 +1106,9 @@ static int abstract_read_register(struct target *target,
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*value = 0;
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switch (width) {
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case 128:
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LOG_WARNING("Ignoring top 64 bits from 128-bit register read.");
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LOG_ERROR("Ignoring top 64 bits from 128-bit register read.");
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case 64:
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*value |= ((uint64_t) dmi_read(target, DMI_DATA0)) << 32;
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*value |= ((uint64_t) dmi_read(target, DMI_DATA1)) << 32;
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case 32:
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*value |= dmi_read(target, DMI_DATA0);
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break;
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@ -1164,6 +1118,34 @@ static int abstract_read_register(struct target *target,
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return ERROR_OK;
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}
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static int abstract_write_register(struct target *target,
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unsigned reg_number,
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unsigned width,
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uint64_t value)
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{
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uint32_t command = abstract_register_size(width);
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command |= reg_number_to_no(reg_number);
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command |= AC_ACCESS_REGISTER_WRITE;
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switch (width) {
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case 128:
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LOG_ERROR("Ignoring top 64 bits from 128-bit register write.");
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case 64:
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dmi_write(target, DMI_DATA1, value >> 32);
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case 32:
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dmi_write(target, DMI_DATA0, value);
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break;
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}
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int result = execute_abstract_command(target, command);
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if (result != ERROR_OK) {
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return result;
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}
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return ERROR_OK;
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}
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static int read_csr(struct target *target, uint64_t *value, uint32_t csr)
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{
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int result = abstract_read_register(target, csr, xlen(target), value);
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@ -1190,15 +1172,19 @@ static int read_csr(struct target *target, uint64_t *value, uint32_t csr)
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static int write_csr(struct target *target, uint32_t csr, uint64_t value)
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{
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LOG_DEBUG("csr 0x%x <- 0x%" PRIx64, csr, value);
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cache_set_load(target, 0, S0, SLOT0);
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cache_set32(target, 1, csrw(S0, csr));
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cache_set_jump(target, 2);
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cache_set(target, SLOT0, value);
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if (cache_write(target, 4, true) != ERROR_OK) {
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return ERROR_FAIL;
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}
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int result = abstract_write_register(target, csr, xlen(target), value);
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if (result == ERROR_OK)
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return result;
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return ERROR_OK;
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// Fall back to program buffer.
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program_t *program = program_new();
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program_add32(program, csrw(S0, csr));
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program_add32(program, ebreak());
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program_set_write(program, S0, value);
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result = execute_program(target, program);
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program_delete(program);
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return result;
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}
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static int write_gpr(struct target *target, unsigned int gpr, uint64_t value)
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@ -2120,159 +2106,32 @@ static riscv_error_t handle_halt_routine(struct target *target)
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{
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riscv013_info_t *info = get_info(target);
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scans_t *scans = scans_new(target, 256);
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// Read all GPRs as fast as we can, because gdb is going to ask for them
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// anyway. Reading them one at a time is much slower.
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// Write the jump back to address 1.
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scans_add_write_jump(scans, 1, false);
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for (int reg = 1; reg < 32; reg++) {
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if (reg == S0 || reg == S1) {
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continue;
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}
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// Write store instruction.
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scans_add_write_store(scans, 0, reg, SLOT0, true);
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// Read value.
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scans_add_read(scans, SLOT0, false);
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uint64_t value;
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int result = abstract_read_register(target, reg, xlen(target), &value);
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if (result != ERROR_OK)
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return result;
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reg_cache_set(target, reg, value);
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}
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// Write store of s0 at index 1.
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scans_add_write_store(scans, 1, S0, SLOT0, false);
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// Write jump at index 2.
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scans_add_write_jump(scans, 2, false);
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// Read S1 from debug RAM
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scans_add_write_load(scans, 0, S0, SLOT_LAST, true);
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// Read value.
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scans_add_read(scans, SLOT0, false);
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// Read S0 from dscratch
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unsigned int csr[] = {CSR_DSCRATCH, CSR_DPC, CSR_DCSR};
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unsigned int csr[] = {CSR_DPC, CSR_DCSR};
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for (unsigned int i = 0; i < DIM(csr); i++) {
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scans_add_write32(scans, 0, csrr(S0, csr[i]), true);
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scans_add_read(scans, SLOT0, false);
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}
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// Final read to get the last value out.
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scans_add_read32(scans, 4, false);
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int retval = scans_execute(scans);
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if (retval != ERROR_OK) {
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LOG_ERROR("JTAG execute failed: %d", retval);
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goto error;
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}
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unsigned int dmi_busy = 0;
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unsigned int interrupt_set = 0;
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unsigned result = 0;
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uint64_t value = 0;
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reg_cache_set(target, 0, 0);
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// The first scan result is the result from something old we don't care
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// about.
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for (unsigned int i = 1; i < scans->next_scan && dmi_busy == 0; i++) {
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dmi_status_t status = scans_get_u32(scans, i, DMI_OP_START,
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DMI_OP_SIZE);
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uint64_t data = scans_get_u64(scans, i, DMI_DATA_START, DMI_DATA_SIZE);
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uint32_t address = scans_get_u32(scans, i, DMI_ADDRESS_START,
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info->abits);
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switch (status) {
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case DMI_STATUS_SUCCESS:
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break;
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case DMI_STATUS_FAILED:
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LOG_ERROR("Debug access failed. Hardware error?");
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goto error;
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case DMI_STATUS_BUSY:
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dmi_busy++;
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break;
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default:
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LOG_ERROR("Got invalid bus access status: %d", status);
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return ERROR_FAIL;
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}
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if (data & DMCONTROL_INTERRUPT) {
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interrupt_set++;
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break;
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}
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if (address == 4 || address == 5) {
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unsigned int reg;
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switch (result) {
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case 0: reg = 1; break;
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case 1: reg = 2; break;
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case 2: reg = 3; break;
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case 3: reg = 4; break;
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case 4: reg = 5; break;
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case 5: reg = 6; break;
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case 6: reg = 7; break;
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// S0
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// S1
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case 7: reg = 10; break;
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case 8: reg = 11; break;
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case 9: reg = 12; break;
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case 10: reg = 13; break;
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case 11: reg = 14; break;
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case 12: reg = 15; break;
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case 13: reg = 16; break;
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case 14: reg = 17; break;
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case 15: reg = 18; break;
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case 16: reg = 19; break;
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case 17: reg = 20; break;
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case 18: reg = 21; break;
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case 19: reg = 22; break;
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case 20: reg = 23; break;
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case 21: reg = 24; break;
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case 22: reg = 25; break;
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case 23: reg = 26; break;
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case 24: reg = 27; break;
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case 25: reg = 28; break;
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case 26: reg = 29; break;
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case 27: reg = 30; break;
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case 28: reg = 31; break;
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case 29: reg = S1; break;
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case 30: reg = S0; break;
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case 31: reg = CSR_DPC; break;
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case 32: reg = CSR_DCSR; break;
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default:
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assert(0);
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}
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if (xlen(target) == 32) {
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reg_cache_set(target, reg, data & 0xffffffff);
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result++;
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} else if (xlen(target) == 64) {
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if (address == 4) {
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value = data & 0xffffffff;
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} else if (address == 5) {
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reg_cache_set(target, reg, ((data & 0xffffffff) << 32) | value);
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value = 0;
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result++;
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}
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}
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}
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}
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if (dmi_busy) {
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increase_dmi_busy_delay(target);
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return RE_AGAIN;
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}
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if (interrupt_set) {
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increase_interrupt_high_delay(target);
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return RE_AGAIN;
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uint64_t value;
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int reg = csr[i];
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int result = read_csr(target, &value, reg);
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if (result != ERROR_OK)
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return result;
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reg_cache_set(target, reg, value);
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}
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// TODO: get rid of those 2 variables and talk to the cache directly.
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info->dpc = reg_cache_get(target, CSR_DPC);
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info->dcsr = reg_cache_get(target, CSR_DCSR);
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scans = scans_delete(scans);
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cache_invalidate(target);
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return RE_OK;
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error:
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scans = scans_delete(scans);
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return RE_FAIL;
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}
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static int handle_halt(struct target *target, bool announce)
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@ -2289,7 +2148,7 @@ static int handle_halt(struct target *target, bool announce)
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return ERROR_FAIL;
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}
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int cause = get_field(info->dcsr, DCSR_CAUSE);
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int cause = get_field(info->dcsr, CSR_DCSR_CAUSE);
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switch (cause) {
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case DCSR_CAUSE_SWBP:
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target->debug_reason = DBG_REASON_BREAKPOINT;
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@ -2307,6 +2166,8 @@ static int handle_halt(struct target *target, bool announce)
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target->debug_reason = DBG_REASON_SINGLESTEP;
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break;
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case DCSR_CAUSE_HALT:
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target->debug_reason = DBG_REASON_DBGRQ;
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break;
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default:
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LOG_ERROR("Invalid halt cause %d in DCSR (0x%" PRIx64 ")",
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cause, info->dcsr);
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@ -2369,21 +2230,25 @@ static int poll_target(struct target *target, bool announce)
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if (debug_level >= LOG_LVL_DEBUG) {
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debug_level = LOG_LVL_INFO;
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}
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bits_t bits = read_bits(target);
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uint32_t dmcontrol = dmi_read(target, DMI_DMCONTROL);
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debug_level = old_debug_level;
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if (bits.haltnot && bits.interrupt) {
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target->state = TARGET_DEBUG_RUNNING;
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LOG_DEBUG("debug running");
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} else if (bits.haltnot && !bits.interrupt) {
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if (target->state != TARGET_HALTED) {
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return handle_halt(target, announce);
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}
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} else if (!bits.haltnot && bits.interrupt) {
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// Target is halting. There is no state for that, so don't change anything.
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LOG_DEBUG("halting");
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} else if (!bits.haltnot && !bits.interrupt) {
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target->state = TARGET_RUNNING;
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switch (get_field(dmcontrol, DMI_DMCONTROL_HARTSTATUS)) {
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case 0:
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if (target->state != TARGET_HALTED) {
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return handle_halt(target, announce);
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}
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break;
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case 1:
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target->state = TARGET_RUNNING;
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break;
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case 2:
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// Could be unavailable for other reasons.
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target->state = TARGET_RESET;
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break;
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case 3:
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LOG_ERROR("Hart disappeared!");
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return ERROR_FAIL;
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}
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return ERROR_OK;
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