Configs for ARM corelink SSE-200 target and Musca A board

This patch adds configuration files for ARM CoreLink SSE-200 SoCs. Also
adds configuration file for SSE-200 based Musca A board. Flash programming
support for Musca A QSPI flash is still not functional. This configuration
will be updated once that support lands into OpenOCD.

Please refer to ARM documentation for more information about SSE-200 and
Musca A.

Change-Id: Id3783c34d6e2609d659ef91c0bf7252c39439874
Signed-off-by: Omair Javaid <omair.javaid@linaro.org>
Reviewed-on: http://openocd.zylin.com/5006
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
bscan_optimization
Omair Javaid 2019-03-31 01:35:43 +05:00 committed by Matthias Welwarsky
parent bc94ca241a
commit ae449bb5f9
2 changed files with 115 additions and 0 deletions

44
tcl/board/arm_musca_a.cfg Normal file
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#
# Configuration script for ARM Musca-A development board
#
# For now we do not support Musca A flash programming using OpenOCD. However, a
# work area is configured for flash programming speed up.
#
# GDB considers all memory as RAM unless target supplies a memory map.
# OpenOCD will only send memory map if flash banks are configured. Otherwise,
# configure GDB after connection by issuing following commands:
# (gdb) mem 0x10200000 0x109FFFFF ro
# (gdb) mem 0x00200000 0x009FFFFF ro
# (gdb) set mem inaccessible-by-default off
# ARM Musca A board supports both JTAG and SWD transports.
source [find target/swj-dp.tcl]
# set a safe JTAG clock speed, can be overridden
adapter_khz 1000
global _CHIPNAME
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME MUSCA_A
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x6ba00477
}
# Enable CPU1 debugging as a separate GDB target
set _ENABLE_CPU1 1
# Musca A1 has 32KB SRAM banks. Override default work-area-size to 8KB per CPU
set WORKAREASIZE_CPU0 0x2000
set WORKAREASIZE_CPU1 0x2000
# Set SRAM bank 1 to be used for work area. Override here if needed.
set WORKAREAADDR_CPU0 0x30008000
set WORKAREAADDR_CPU1 0x3000A000
source [find target/arm_corelink_sse200.cfg]

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#
# Configuration script for Arm CoreLink SSE-200 Subsystem based IoT SoCs.
#
global TARGET
set TARGET $_CHIPNAME
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
#
# SRAM on ARM CoreLink SSE-200 can be 4 banks of 8/16/32/64 KB
# We will configure work area assuming 8-KB bank size in SRAM bank 1.
# Also SRAM start addresses defaults to secure mode alias.
# These values can be overridden as per board configuration
#
global _WORKAREASIZE_CPU0
if { [info exists WORKAREASIZE_CPU0] } {
set _WORKAREASIZE_CPU0 $WORKAREASIZE_CPU0
} else {
set _WORKAREASIZE_CPU0 0x1000
}
global _WORKAREAADDR_CPU0
if { [info exists WORKAREAADDR_CPU0] } {
set _WORKAREAADDR_CPU0 $WORKAREAADDR_CPU0
} else {
set _WORKAREAADDR_CPU0 0x30008000
}
#
# Target configuration for Cortex M33 Core 0 on ARM CoreLink SSE-200
# Core 0 is the boot core and will always be configured.
#
target create ${TARGET}.CPU0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
${TARGET}.CPU0 configure -work-area-phys $_WORKAREAADDR_CPU0 -work-area-size $_WORKAREASIZE_CPU0 -work-area-backup 0
${TARGET}.CPU0 cortex_m reset_config sysresetreq
#
# Target configuration for Cortex M33 Core 1 on ARM CoreLink SSE-200
# Core 1 is optional and locked at boot until core 0 unlocks it.
#
if { $_ENABLE_CPU1 } {
global _WORKAREASIZE_CPU1
if { [info exists WORKAREASIZE_CPU1] } {
set _WORKAREASIZE_CPU1 $WORKAREASIZE_CPU1
} else {
set _WORKAREASIZE_CPU1 0x1000
}
global _WORKAREAADDR_CPU1
if { [info exists WORKAREAADDR_CPU1] } {
set _WORKAREAADDR_CPU1 $WORKAREAADDR_CPU1
} else {
set _WORKAREAADDR_CPU1 0x30009000
}
target create ${TARGET}.CPU1 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
${TARGET}.CPU1 configure -work-area-phys $_WORKAREAADDR_CPU1 -work-area-size $_WORKAREASIZE_CPU1 -work-area-backup 0
${TARGET}.CPU1 cortex_m reset_config vectreset
}
# Make sure the default target is the boot core
targets ${TARGET}.CPU0