niietcm4: support for NIIET's Cortex-M4 microcontrollers
This adds docs, example config, flash driver. Driver is only supports K1921VK01T model for now. Change-Id: I135259bb055dd2df1a17de99f066e2b24eae1b0f Signed-off-by: Bogdan Kolbov <kolbov@niiet.ru> Reviewed-on: http://openocd.zylin.com/3011 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>__archive__
Bogdan Kolbov
Freddie Chopin
parent
7a8915ff64
commit
ae2142d5a2
2
README
2
README
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@ -128,7 +128,7 @@ Flash drivers
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ADUC702x, AT91SAM, AVR, CFI, DSP5680xx, EFM32, EM357, FM3, Kinetis,
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LPC8xx/LPC1xxx/LPC2xxx/LPC541xx, LPC2900, LPCSPIFI, Marvell QSPI,
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Milandr, NuMicro, PIC32mx, PSoC4, SiM3x, Stellaris, STM32, STMSMI,
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Milandr, NIIET, NuMicro, PIC32mx, PSoC4, SiM3x, Stellaris, STM32, STMSMI,
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STR7x, STR9x, nRF51; NAND controllers of AT91SAM9, LPC3180, LPC32xx,
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i.MX31, MXC, NUC910, Orion/Kirkwood, S3C24xx, S3C6400, XMC4xxx.
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@ -0,0 +1,112 @@
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/***************************************************************************
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* Copyright (C) 2015 by Bogdan Kolbov *
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* kolbov@niiet.ru *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc. *
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***************************************************************************/
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.text
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.syntax unified
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.cpu cortex-m4
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.thumb
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.thumb_func
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/* K1921VK01T has 128-bitwidth flash, so it`s able to load 4x32-bit words at the time.
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* And only after all words loaded we can start write
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*/
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/* Registers addresses */
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#define FLASH_FMA 0x00 /* Address reg */
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#define FLASH_FMD1 0x04 /* Data1 reg */
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#define FLASH_FMC 0x08 /* Command reg */
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#define FLASH_FCIS 0x0C /* Operation Status reg */
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#define FLASH_FCIC 0x14 /* Operation Status Clear reg */
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#define FLASH_FMD2 0x50 /* Data2 reg */
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#define FLASH_FMD3 0x54 /* Data3 reg */
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#define FLASH_FMD4 0x58 /* Data4 reg*/
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/* Params:
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* r0 - write cmd (in), status (out)
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* r1 - count
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* r2 - workarea start
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* r3 - workarea end
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* r4 - target address
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* Clobbered:
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* r5 - rp
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* r6 - wp, tmp
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* r7 - flash base
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*/
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ldr r7, =#0xA001C000 /* Flash reg base*/
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wait_fifo:
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ldr r6, [r2, #0] /* read wp */
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cmp r6, #0 /* abort if wp == 0 */
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beq exit
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ldr r5, [r2, #4] /* read rp */
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cmp r5, r6 /* wait until rp != wp */
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beq wait_fifo
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load_data:
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ldr r6, [r5] /* read data1 */
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str r6, [r7, #FLASH_FMD1]
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adds r5, #4
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ldr r6, [r5] /* read data2 */
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str r6, [r7, #FLASH_FMD2]
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adds r5, #4
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ldr r6, [r5] /* read data3 */
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str r6, [r7, #FLASH_FMD3]
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adds r5, #4
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ldr r6, [r5] /* read data4 */
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str r6, [r7, #FLASH_FMD4]
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adds r5, #4
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start_write:
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str r4, [r7, #FLASH_FMA] /* set addr */
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adds r4, #16
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str r0, [r7, #FLASH_FMC] /* write cmd */
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busy:
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ldr r6, [r7, #FLASH_FCIS] /* wait until flag set */
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cmp r6, #0x0
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beq busy
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cmp r6, #2 /* check the error bit */
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beq error
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movs r6, #1 /* clear flags */
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str r6, [r7, #FLASH_FCIC]
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cmp r5, r3 /* wrap rp at end of buffer */
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bcc no_wrap
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mov r5, r2
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adds r5, #8
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no_wrap:
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str r5, [r2, #4] /* store rp */
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subs r1, r1, #1 /* decrement 16-byte block count */
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cmp r1, #0
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beq exit /* loop if not done */
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b wait_fifo
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error:
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movs r0, #0
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str r0, [r2, #4] /* set rp = 0 on error */
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exit:
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mov r0, r6 /* return status in r0 */
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bkpt #0
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@ -5380,6 +5380,66 @@ if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
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@end example
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@end deffn
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@deffn {Flash Driver} niietcm4
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This drivers handles the integrated NOR flash on NIIET Cortex-M4
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based controllers. Flash size and sector layout are auto-configured by the driver.
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Main flash memory is called "Bootflash" and has main region and info region.
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Info region is NOT memory mapped by default,
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but it can replace first part of main region if needed.
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Full erase, single and block writes are supported for both main and info regions.
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There is additional not memory mapped flash called "Userflash", which
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also have division into regions: main and info.
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Purpose of userflash - to store system and user settings.
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Driver has special commands to perform operations with this memmory.
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@example
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flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
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@end example
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Some niietcm4-specific commands are defined:
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@deffn Command {niietcm4 uflash_read_byte} bank ('main'|'info') address
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Read byte from main or info userflash region.
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@end deffn
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@deffn Command {niietcm4 uflash_write_byte} bank ('main'|'info') address value
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Write byte to main or info userflash region.
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@end deffn
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@deffn Command {niietcm4 uflash_full_erase} bank
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Erase all userflash including info region.
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@end deffn
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@deffn Command {niietcm4 uflash_erase} bank ('main'|'info') first_sector last_sector
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Erase sectors of main or info userflash region, starting at sector first up to and including last.
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@end deffn
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@deffn Command {niietcm4 uflash_protect_check} bank ('main'|'info')
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Check sectors protect.
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@end deffn
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@deffn Command {niietcm4 uflash_protect} bank ('main'|'info') first_sector last_sector ('on'|'off')
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Protect sectors of main or info userflash region, starting at sector first up to and including last.
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@end deffn
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@deffn Command {niietcm4 bflash_info_remap} bank ('on'|'off')
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Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).
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@end deffn
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@deffn Command {niietcm4 extmem_cfg} bank ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh') pin_num ('func1'|'func3')
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Configure external memory interface for boot.
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@end deffn
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@deffn Command {niietcm4 service_mode_erase} bank
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Perform emergency erase of all flash (bootflash and userflash).
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@end deffn
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@deffn Command {niietcm4 driver_info} bank
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Show information about flash driver.
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@end deffn
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@end deffn
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@deffn {Flash Driver} nrf51
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All members of the nRF51 microcontroller families from Nordic Semiconductor
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include internal flash and use ARM Cortex-M0 core.
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@ -50,7 +50,9 @@ NOR_DRIVERS = \
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mrvlqspi.c \
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psoc4.c \
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sim3x.c \
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xmc4xxx.c
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xmc4xxx.c \
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niietcm4.c
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noinst_HEADERS = \
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core.h \
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@ -63,6 +63,7 @@ extern struct flash_driver psoc4_flash;
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extern struct flash_driver sim3x_flash;
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extern struct flash_driver jtagspi_flash;
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extern struct flash_driver xmc4xxx_flash;
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extern struct flash_driver niietcm4_flash;
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/**
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* The list of built-in flash drivers.
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@ -110,6 +111,7 @@ static struct flash_driver *flash_drivers[] = {
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&sim3x_flash,
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&jtagspi_flash,
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&xmc4xxx_flash,
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&niietcm4_flash,
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NULL,
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};
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,55 @@
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# K1921VK01T
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# http://niiet.ru/chips/nis?id=354
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME k1921vk01t
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}
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x10000
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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set _CPUTAPID 0x410fc241
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} {
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# SWD IDCODE
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set _CPUTAPID 0x2ba01477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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flash bank $_CHIPNAME.flash niietcm4 0 0 0 0 $_TARGETNAME
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adapter_khz 2000
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adapter_nsrst_delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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