diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 946a78e02..c9254508a 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -933,23 +933,40 @@ static const struct {
 	{ ARM_ID, 0x924, "Cortex-M3 ETM",    "(Embedded Trace)", },
 	{ ARM_ID, 0x925, "Cortex-M4 ETM",    "(Embedded Trace)", },
 	{ ARM_ID, 0x930, "Cortex-R4 ETM",    "(Embedded Trace)", },
+	{ ARM_ID, 0x931, "Cortex-R5 ETM",    "(Embedded Trace)", },
 	{ ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
-	{ ARM_ID, 0x950, "CoreSight Component", "(unidentified Cortex-A9 component)", },
-	{ ARM_ID, 0x955, "CoreSight Component", "(unidentified Cortex-A5 component)", },
+	{ ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
+	{ ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
+	{ ARM_ID, 0x95a, "Cortex-A72 ETM",   "(Embedded Trace)", },
+	{ ARM_ID, 0x95b, "Cortex-A17 PTM",   "(Program Trace Macrocell)", },
+	{ ARM_ID, 0x95d, "Cortex-A53 ETM",   "(Embedded Trace)", },
+	{ ARM_ID, 0x95e, "Cortex-A57 ETM",   "(Embedded Trace)", },
 	{ ARM_ID, 0x95f, "Cortex-A15 PTM",   "(Program Trace Macrocell)", },
 	{ ARM_ID, 0x961, "CoreSight TMC",    "(Trace Memory Controller)", },
 	{ ARM_ID, 0x962, "CoreSight STM",    "(System Trace Macrocell)", },
 	{ ARM_ID, 0x9a0, "CoreSight PMU",    "(Performance Monitoring Unit)", },
 	{ ARM_ID, 0x9a1, "Cortex-M4 TPIU",   "(Trace Port Interface Unit)", },
-	{ ARM_ID, 0x9a5, "Cortex-A5 ETM",    "(Embedded Trace)", },
+	{ ARM_ID, 0x9a5, "Cortex-A5 PMU",    "(Performance Monitor Unit)", },
 	{ ARM_ID, 0x9a7, "Cortex-A7 PMU",    "(Performance Monitor Unit)", },
+	{ ARM_ID, 0x9a8, "Cortex-A53 CTI",    "(Cross Trigger)", },
+	{ ARM_ID, 0x9ae, "Cortex-A17 PMU",    "(Performance Monitor Unit)", },
 	{ ARM_ID, 0x9af, "Cortex-A15 PMU",   "(Performance Monitor Unit)", },
+	{ ARM_ID, 0x9b7, "Cortex-R7 PMU",    "(Performance Monitoring Unit)", },
+	{ ARM_ID, 0x9d3, "Cortex-A53 PMU",    "(Performance Monitor Unit)", },
+	{ ARM_ID, 0x9d7, "Cortex-A57 PMU",    "(Performance Monitor Unit)", },
+	{ ARM_ID, 0x9d8, "Cortex-A72 PMU",    "(Performance Monitor Unit)", },
 	{ ARM_ID, 0xc05, "Cortex-A5 Debug",  "(Debug Unit)", },
 	{ ARM_ID, 0xc07, "Cortex-A7 Debug",  "(Debug Unit)", },
 	{ ARM_ID, 0xc08, "Cortex-A8 Debug",  "(Debug Unit)", },
 	{ ARM_ID, 0xc09, "Cortex-A9 Debug",  "(Debug Unit)", },
+	{ ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
 	{ ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
 	{ ARM_ID, 0xc14, "Cortex-R4 Debug",  "(Debug Unit)", },
+	{ ARM_ID, 0xc15, "Cortex-R5 Debug",  "(Debug Unit)", },
+	{ ARM_ID, 0xc17, "Cortex-R7 Debug",  "(Debug Unit)", },
+	{ ARM_ID, 0xd03, "Cortex-A53 Debug",  "(Debug Unit)", },
+	{ ARM_ID, 0xd07, "Cortex-A57 Debug",  "(Debug Unit)", },
+	{ ARM_ID, 0xd08, "Cortex-A72 Debug",  "(Debug Unit)", },
 	{ 0x0E5,  0x000, "SHARC+/Blackfin+", "", },
 	/* legacy comment: 0x113: what? */
 	{ ANY_ID,  0x120, "TI SDTI",         "(System Debug Trace Interface)", }, /* from OMAP3 memmap */