ARM920: remove exports and forward decls
Unneeded exports cause confusion about the module interfaces. Make most functions static. Add a short header comment. The forward decls are just code clutter; remove them, by moving their references after definitions. This is another file which never needed even one internal forward declaration. This saved almost 900 bytes of code on x86_32; it seems the compiler can leverage its knowledge that these functions are not called from the outside world... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>__archive__
David Brownell
parent
36b4ac90e4
commit
aab023570b
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@ -26,73 +26,33 @@
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#include "target_type.h"
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/*
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* For information about the ARM920T, see ARM DDI 0151C especially
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* Chapter 9 about debug support, which shows how to manipulate each
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* of the different scan chains:
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*
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* 0 ... ARM920 signals, e.g. to rest of SOC (unused here)
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* 1 ... debugging; watchpoint and breakpoint status, etc; also
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* MMU and cache access in conjunction with scan chain 15
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* 2 ... EmbeddedICE
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* 3 ... external boundary scan (SoC-specific, unused here)
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* 4 ... access to cache tag RAM
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* 6 ... ETM9
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* 15 ... access coprocessor 15, "physical" or "interpreted" modes
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* "interpreted" works with a few actual MRC/MCR instructions
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* "physical" provides register-like behaviors.
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*
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* The ARM922T is similar, but with smaller caches (8K each, vs 16K).
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*/
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#if 0
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#define _DEBUG_INSTRUCTION_EXECUTION_
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#endif
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/* cli handling */
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int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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int arm920t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
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int arm920t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
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int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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/* forward declarations */
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int arm920t_target_create(struct target_s *target, Jim_Interp *interp);
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int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
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#define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
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static int arm920t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value);
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static int arm920t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value);
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target_type_t arm920t_target =
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{
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.name = "arm920t",
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.poll = arm7_9_poll,
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.arch_state = arm920t_arch_state,
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.target_request_data = arm7_9_target_request_data,
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.halt = arm7_9_halt,
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.resume = arm7_9_resume,
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.step = arm7_9_step,
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.assert_reset = arm7_9_assert_reset,
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.deassert_reset = arm7_9_deassert_reset,
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.soft_reset_halt = arm920t_soft_reset_halt,
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.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
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.read_memory = arm920t_read_memory,
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.write_memory = arm920t_write_memory,
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.read_phys_memory = arm920t_read_phys_memory,
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.write_phys_memory = arm920t_write_phys_memory,
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.bulk_write_memory = arm7_9_bulk_write_memory,
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.checksum_memory = arm7_9_checksum_memory,
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.blank_check_memory = arm7_9_blank_check_memory,
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.run_algorithm = armv4_5_run_algorithm,
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.add_breakpoint = arm7_9_add_breakpoint,
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.remove_breakpoint = arm7_9_remove_breakpoint,
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.add_watchpoint = arm7_9_add_watchpoint,
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.remove_watchpoint = arm7_9_remove_watchpoint,
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.register_commands = arm920t_register_commands,
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.target_create = arm920t_target_create,
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.init_target = arm920t_init_target,
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.examine = arm9tdmi_examine,
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.mrc = arm920t_mrc,
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.mcr = arm920t_mcr,
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};
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int arm920t_read_cp15_physical(target_t *target, int reg_addr, uint32_t *value)
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static int arm920t_read_cp15_physical(target_t *target,
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int reg_addr, uint32_t *value)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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@ -134,7 +94,7 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, uint32_t *value)
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jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
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#ifdef _DEBUG_INSTRUCTION_EXECUTION_
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#ifdef _DEBUG_INSTRUCTION_EXECUTION_
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jtag_execute_queue();
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LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
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#endif
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@ -142,7 +102,8 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, uint32_t *value)
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return ERROR_OK;
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}
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int arm920t_write_cp15_physical(target_t *target, int reg_addr, uint32_t value)
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static int arm920t_write_cp15_physical(target_t *target,
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int reg_addr, uint32_t value)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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@ -188,7 +149,8 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, uint32_t value)
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return ERROR_OK;
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}
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int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode, uint32_t arm_opcode)
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static int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode,
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uint32_t arm_opcode)
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{
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int retval;
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armv4_5_common_t *armv4_5 = target->arch_info;
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@ -243,7 +205,8 @@ int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode, uint32_t arm_op
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return ERROR_OK;
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}
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int arm920t_read_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t address, uint32_t *value)
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static int arm920t_read_cp15_interpreted(target_t *target,
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uint32_t cp15_opcode, uint32_t address, uint32_t *value)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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uint32_t* regs_p[1];
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@ -286,7 +249,9 @@ int arm920t_read_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32
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return ERROR_OK;
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}
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int arm920t_write_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t value, uint32_t address)
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static
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int arm920t_write_cp15_interpreted(target_t *target,
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uint32_t cp15_opcode, uint32_t value, uint32_t address)
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{
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uint32_t cp15c15 = 0x0;
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armv4_5_common_t *armv4_5 = target->arch_info;
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@ -324,6 +289,7 @@ int arm920t_write_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint3
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return ERROR_OK;
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}
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// EXPORTED to FA256
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uint32_t arm920t_get_ttb(target_t *target)
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{
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int retval;
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@ -335,6 +301,7 @@ uint32_t arm920t_get_ttb(target_t *target)
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return ttb;
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}
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// EXPORTED to FA256
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void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
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{
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uint32_t cp15_control;
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@ -355,6 +322,7 @@ void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_
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arm920t_write_cp15_physical(target, 0x2, cp15_control);
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}
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// EXPORTED to FA256
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void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
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{
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uint32_t cp15_control;
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@ -375,6 +343,7 @@ void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_c
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arm920t_write_cp15_physical(target, 0x2, cp15_control);
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}
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// EXPORTED to FA256
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void arm920t_post_debug_entry(target_t *target)
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{
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uint32_t cp15c15;
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@ -421,6 +390,7 @@ void arm920t_post_debug_entry(target_t *target)
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}
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}
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// EXPORTED to FA256
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void arm920t_pre_restore_context(target_t *target)
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{
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uint32_t cp15c15;
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@ -446,7 +416,9 @@ void arm920t_pre_restore_context(target_t *target)
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}
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}
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int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm920t_common_t **arm920t_p)
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static int arm920t_get_arch_pointers(target_t *target,
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armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p,
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arm9tdmi_common_t **arm9tdmi_p, arm920t_common_t **arm920t_p)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9;
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@ -484,6 +456,7 @@ int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, ar
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return ERROR_OK;
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}
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/** Logs summary of ARM920 state for a halted target. */
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int arm920t_arch_state(struct target_s *target)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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@ -517,6 +490,7 @@ int arm920t_arch_state(struct target_s *target)
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return ERROR_OK;
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}
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/** Reads a buffer, in the specified word size, with current MMU settings. */
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int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
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{
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int retval;
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@ -527,27 +501,34 @@ int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size
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}
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int arm920t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
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static int arm920t_read_phys_memory(struct target_s *target,
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uint32_t address, uint32_t size,
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uint32_t count, uint8_t *buffer)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
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arm920t_common_t *arm920t = arm9tdmi->arch_info;
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return armv4_5_mmu_read_physical(target, &arm920t->armv4_5_mmu, address, size, count, buffer);
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return armv4_5_mmu_read_physical(target, &arm920t->armv4_5_mmu,
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address, size, count, buffer);
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}
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int arm920t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
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static int arm920t_write_phys_memory(struct target_s *target,
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uint32_t address, uint32_t size,
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uint32_t count, uint8_t *buffer)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
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arm920t_common_t *arm920t = arm9tdmi->arch_info;
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return armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, address, size, count, buffer);
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return armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu,
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address, size, count, buffer);
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}
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/** Writes a buffer, in the specified word size, with current MMU settings. */
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int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
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{
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int retval;
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@ -584,6 +565,7 @@ int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t siz
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return retval;
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}
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// EXPORTED to FA256
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int arm920t_soft_reset_halt(struct target_s *target)
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{
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int retval = ERROR_OK;
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@ -656,13 +638,6 @@ int arm920t_soft_reset_halt(struct target_s *target)
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return ERROR_OK;
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}
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int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
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{
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arm9tdmi_init_target(cmd_ctx, target);
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return ERROR_OK;
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}
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int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap_t *tap)
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{
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arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
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@ -699,36 +674,15 @@ int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap
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return ERROR_OK;
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}
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int arm920t_target_create(struct target_s *target, Jim_Interp *interp)
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static int arm920t_target_create(struct target_s *target, Jim_Interp *interp)
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{
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arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t));
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arm920t_init_arch_info(target, arm920t, target->tap);
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return ERROR_OK;
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return arm920t_init_arch_info(target, arm920t, target->tap);
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}
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int arm920t_register_commands(struct command_context_s *cmd_ctx)
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{
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int retval;
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command_t *arm920t_cmd;
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retval = arm9tdmi_register_commands(cmd_ctx);
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arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", NULL, COMMAND_ANY, "arm920t specific commands");
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register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
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register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
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register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
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register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content");
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register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content");
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return retval;
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}
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int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
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static int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx,
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char *cmd, char **args, int argc)
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{
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int retval = ERROR_OK;
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target_t *target = get_current_target(cmd_ctx);
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@ -980,7 +934,8 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
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return ERROR_OK;
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}
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int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
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static int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx,
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char *cmd, char **args, int argc)
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{
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int retval = ERROR_OK;
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target_t *target = get_current_target(cmd_ctx);
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@ -1268,7 +1223,9 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
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return ERROR_OK;
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}
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int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
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static int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx,
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char *cmd, char **args, int argc)
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{
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int retval;
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target_t *target = get_current_target(cmd_ctx);
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@ -1329,7 +1286,8 @@ int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
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return ERROR_OK;
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}
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int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
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static int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx,
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char *cmd, char **args, int argc)
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{
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int retval;
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target_t *target = get_current_target(cmd_ctx);
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@ -1403,7 +1361,8 @@ int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, c
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return ERROR_OK;
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}
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int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
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static int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx,
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char *cmd, char **args, int argc)
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{
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target_t *target = get_current_target(cmd_ctx);
|
||||
armv4_5_common_t *armv4_5;
|
||||
|
|
@ -1442,3 +1401,78 @@ static int arm920t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2,
|
|||
|
||||
return arm920t_write_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value);
|
||||
}
|
||||
|
||||
/** Registers commands to access coprocessor, cache, and MMU resources. */
|
||||
int arm920t_register_commands(struct command_context_s *cmd_ctx)
|
||||
{
|
||||
int retval;
|
||||
command_t *arm920t_cmd;
|
||||
|
||||
retval = arm9tdmi_register_commands(cmd_ctx);
|
||||
|
||||
arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t",
|
||||
NULL, COMMAND_ANY,
|
||||
"arm920t specific commands");
|
||||
|
||||
register_command(cmd_ctx, arm920t_cmd, "cp15",
|
||||
arm920t_handle_cp15_command, COMMAND_EXEC,
|
||||
"display/modify cp15 register <num> [value]");
|
||||
register_command(cmd_ctx, arm920t_cmd, "cp15i",
|
||||
arm920t_handle_cp15i_command, COMMAND_EXEC,
|
||||
"display/modify cp15 (interpreted access) "
|
||||
"<opcode> [value] [address]");
|
||||
register_command(cmd_ctx, arm920t_cmd, "cache_info",
|
||||
arm920t_handle_cache_info_command, COMMAND_EXEC,
|
||||
"display information about target caches");
|
||||
register_command(cmd_ctx, arm920t_cmd, "read_cache",
|
||||
arm920t_handle_read_cache_command, COMMAND_EXEC,
|
||||
"display I/D cache content");
|
||||
register_command(cmd_ctx, arm920t_cmd, "read_mmu",
|
||||
arm920t_handle_read_mmu_command, COMMAND_EXEC,
|
||||
"display I/D mmu content");
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/** Holds methods for ARM920 targets. */
|
||||
target_type_t arm920t_target =
|
||||
{
|
||||
.name = "arm920t",
|
||||
|
||||
.poll = arm7_9_poll,
|
||||
.arch_state = arm920t_arch_state,
|
||||
|
||||
.target_request_data = arm7_9_target_request_data,
|
||||
|
||||
.halt = arm7_9_halt,
|
||||
.resume = arm7_9_resume,
|
||||
.step = arm7_9_step,
|
||||
|
||||
.assert_reset = arm7_9_assert_reset,
|
||||
.deassert_reset = arm7_9_deassert_reset,
|
||||
.soft_reset_halt = arm920t_soft_reset_halt,
|
||||
|
||||
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
|
||||
|
||||
.read_memory = arm920t_read_memory,
|
||||
.write_memory = arm920t_write_memory,
|
||||
.read_phys_memory = arm920t_read_phys_memory,
|
||||
.write_phys_memory = arm920t_write_phys_memory,
|
||||
.bulk_write_memory = arm7_9_bulk_write_memory,
|
||||
.checksum_memory = arm7_9_checksum_memory,
|
||||
.blank_check_memory = arm7_9_blank_check_memory,
|
||||
|
||||
.run_algorithm = armv4_5_run_algorithm,
|
||||
|
||||
.add_breakpoint = arm7_9_add_breakpoint,
|
||||
.remove_breakpoint = arm7_9_remove_breakpoint,
|
||||
.add_watchpoint = arm7_9_add_watchpoint,
|
||||
.remove_watchpoint = arm7_9_remove_watchpoint,
|
||||
|
||||
.register_commands = arm920t_register_commands,
|
||||
.target_create = arm920t_target_create,
|
||||
.init_target = arm9tdmi_init_target,
|
||||
.examine = arm9tdmi_examine,
|
||||
.mrc = arm920t_mrc,
|
||||
.mcr = arm920t_mcr,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -53,13 +53,17 @@ typedef struct arm920t_tlb_entry_s
|
|||
|
||||
int arm920t_arch_state(struct target_s *target);
|
||||
int arm920t_soft_reset_halt(struct target_s *target);
|
||||
int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
|
||||
int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
|
||||
int arm920t_read_memory(struct target_s *target,
|
||||
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
|
||||
int arm920t_write_memory(struct target_s *target,
|
||||
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
|
||||
void arm920t_post_debug_entry(target_t *target);
|
||||
void arm920t_pre_restore_context(target_t *target);
|
||||
uint32_t arm920t_get_ttb(target_t *target);
|
||||
void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache);
|
||||
void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache);
|
||||
uint32_t arm920t_get_ttb(target_t *target);
|
||||
void arm920t_disable_mmu_caches(target_t *target,
|
||||
int mmu, int d_u_cache, int i_cache);
|
||||
void arm920t_enable_mmu_caches(target_t *target,
|
||||
int mmu, int d_u_cache, int i_cache);
|
||||
int arm920t_register_commands(struct command_context_s *cmd_ctx);
|
||||
|
||||
#endif /* ARM920T_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue