Whitespace cleanup from David Brownell <david-b@pacbell.net>
git-svn-id: svn://svn.berlios.de/openocd/trunk@1802 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
kc8apf
parent
41826d5bd9
commit
a931baa619
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@ -61,13 +61,13 @@ nand_flash_controller_t lpc3180_nand_controller =
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static int lpc3180_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device)
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{
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lpc3180_nand_controller_t *lpc3180_info;
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if (argc < 3)
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{
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LOG_WARNING("incomplete 'lpc3180' nand flash configuration");
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return ERROR_FLASH_BANK_INVALID;
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}
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lpc3180_info = malloc(sizeof(lpc3180_nand_controller_t));
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device->controller_priv = lpc3180_info;
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@ -81,22 +81,22 @@ static int lpc3180_nand_device_command(struct command_context_s *cmd_ctx, char *
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lpc3180_info->osc_freq = strtoul(args[2], NULL, 0);
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if ((lpc3180_info->osc_freq < 1000) || (lpc3180_info->osc_freq > 20000))
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{
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LOG_WARNING("LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i", lpc3180_info->osc_freq);
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LOG_WARNING("LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i", lpc3180_info->osc_freq);
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}
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lpc3180_info->selected_controller = LPC3180_NO_CONTROLLER;
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lpc3180_info->sw_write_protection = 0;
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lpc3180_info->sw_wp_lower_bound = 0x0;
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lpc3180_info->sw_wp_upper_bound = 0x0;
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return ERROR_OK;
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}
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static int lpc3180_register_commands(struct command_context_s *cmd_ctx)
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{
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command_t *lpc3180_cmd = register_command(cmd_ctx, NULL, "lpc3180", NULL, COMMAND_ANY, "commands specific to the LPC3180 NAND flash controllers");
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register_command(cmd_ctx, lpc3180_cmd, "select", handle_lpc3180_select_command, COMMAND_EXEC, "select <'mlc'|'slc'> controller (default is mlc)");
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return ERROR_OK;
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}
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@ -112,20 +112,20 @@ static int lpc3180_pll(int fclkin, u32 pll_ctrl)
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if (!lock)
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LOG_WARNING("PLL is not locked");
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if (!bypass && direct) /* direct mode */
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return (m * fclkin) / n;
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if (bypass && !direct) /* bypass mode */
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return fclkin / (2 * p);
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if (bypass & direct) /* direct bypass mode */
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return fclkin;
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if (feedback) /* integer mode */
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return m * (fclkin / n);
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else /* non-integer mode */
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return (m / (2 * p)) * (fclkin / n);
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return (m / (2 * p)) * (fclkin / n);
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}
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static float lpc3180_cycle_time(lpc3180_nand_controller_t *lpc3180_info)
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@ -136,20 +136,20 @@ static float lpc3180_cycle_time(lpc3180_nand_controller_t *lpc3180_info)
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int hclk;
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int hclk_pll;
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float cycle;
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/* calculate timings */
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/* determine current SYSCLK (13'MHz or main oscillator) */
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/* determine current SYSCLK (13'MHz or main oscillator) */
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target_read_u32(target, 0x40004050, &sysclk_ctrl);
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if ((sysclk_ctrl & 1) == 0)
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sysclk = lpc3180_info->osc_freq;
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else
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sysclk = 13000;
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/* determine selected HCLK source */
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target_read_u32(target, 0x40004044, &pwr_ctrl);
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if ((pwr_ctrl & (1 << 2)) == 0) /* DIRECT RUN mode */
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{
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hclk = sysclk;
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@ -160,21 +160,21 @@ static float lpc3180_cycle_time(lpc3180_nand_controller_t *lpc3180_info)
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hclk_pll = lpc3180_pll(sysclk, hclkpll_ctrl);
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target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
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if (pwr_ctrl & (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */
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{
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hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
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}
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else /* HCLK uses HCLK_PLL */
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{
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hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
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hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
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}
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}
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LOG_DEBUG("LPC3180 HCLK currently clocked at %i kHz", hclk);
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cycle = (1.0 / hclk) * 1000000.0;
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return cycle;
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}
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@ -185,20 +185,20 @@ static int lpc3180_init(struct nand_device_s *device)
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int bus_width = (device->bus_width) ? (device->bus_width) : 8;
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int address_cycles = (device->address_cycles) ? (device->address_cycles) : 3;
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int page_size = (device->page_size) ? (device->page_size) : 512;
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if (target->state != TARGET_HALTED)
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{
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LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
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return ERROR_NAND_OPERATION_FAILED;
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}
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/* sanitize arguments */
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if ((bus_width != 8) && (bus_width != 16))
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{
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LOG_ERROR("LPC3180 only supports 8 or 16 bit bus width, not %i", bus_width);
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return ERROR_NAND_OPERATION_NOT_SUPPORTED;
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}
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/* The LPC3180 only brings out 8 bit NAND data bus, but the controller
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* would support 16 bit, too, so we just warn about this for now
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*/
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@ -206,44 +206,44 @@ static int lpc3180_init(struct nand_device_s *device)
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{
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LOG_WARNING("LPC3180 only supports 8 bit bus width");
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}
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/* inform calling code about selected bus width */
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device->bus_width = bus_width;
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if ((address_cycles != 3) && (address_cycles != 4))
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{
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LOG_ERROR("LPC3180 only supports 3 or 4 address cycles, not %i", address_cycles);
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return ERROR_NAND_OPERATION_NOT_SUPPORTED;
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}
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if ((page_size != 512) && (page_size != 2048))
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{
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LOG_ERROR("LPC3180 only supports 512 or 2048 byte pages, not %i", page_size);
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return ERROR_NAND_OPERATION_NOT_SUPPORTED;
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}
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/* select MLC controller if none is currently selected */
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if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
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{
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LOG_DEBUG("no LPC3180 NAND flash controller selected, using default 'mlc'");
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lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
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}
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if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
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{
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u32 mlc_icr_value = 0x0;
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float cycle;
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int twp, twh, trp, treh, trhz, trbwb, tcea;
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/* FLASHCLK_CTRL = 0x22 (enable clock for MLC flash controller) */
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target_write_u32(target, 0x400040c8, 0x22);
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/* MLC_CEH = 0x0 (Force nCE assert) */
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target_write_u32(target, 0x200b804c, 0x0);
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/* MLC_LOCK = 0xa25e (unlock protected registers) */
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target_write_u32(target, 0x200b8044, 0xa25e);
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/* MLC_ICR = configuration */
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if (lpc3180_info->sw_write_protection)
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mlc_icr_value |= 0x8;
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@ -254,10 +254,10 @@ static int lpc3180_init(struct nand_device_s *device)
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if (bus_width == 16)
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mlc_icr_value |= 0x1;
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target_write_u32(target, 0x200b8030, mlc_icr_value);
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/* calculate NAND controller timings */
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cycle = lpc3180_cycle_time(lpc3180_info);
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twp = ((40 / cycle) + 1);
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twh = ((20 / cycle) + 1);
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trp = ((30 / cycle) + 1);
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@ -265,14 +265,14 @@ static int lpc3180_init(struct nand_device_s *device)
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trhz = ((30 / cycle) + 1);
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trbwb = ((100 / cycle) + 1);
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tcea = ((45 / cycle) + 1);
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/* MLC_LOCK = 0xa25e (unlock protected registers) */
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target_write_u32(target, 0x200b8044, 0xa25e);
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/* MLC_TIME_REG */
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target_write_u32(target, 0x200b8034, (twp & 0xf) | ((twh & 0xf) << 4) |
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((trp & 0xf) << 8) | ((treh & 0xf) << 12) | ((trhz & 0x7) << 16) |
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((trbwb & 0x1f) << 19) | ((tcea & 0x3) << 24));
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target_write_u32(target, 0x200b8034, (twp & 0xf) | ((twh & 0xf) << 4) |
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((trp & 0xf) << 8) | ((treh & 0xf) << 12) | ((trhz & 0x7) << 16) |
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((trbwb & 0x1f) << 19) | ((tcea & 0x3) << 24));
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lpc3180_reset(device);
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}
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@ -281,30 +281,30 @@ static int lpc3180_init(struct nand_device_s *device)
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float cycle;
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int r_setup, r_hold, r_width, r_rdy;
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int w_setup, w_hold, w_width, w_rdy;
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/* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */
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target_write_u32(target, 0x400040c8, 0x05);
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/* SLC_CFG = 0x (Force nCE assert, ECC enabled, WIDTH = bus_width) */
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target_write_u32(target, 0x20020014, 0x28 | (bus_width == 16) ? 1 : 0);
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/* calculate NAND controller timings */
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cycle = lpc3180_cycle_time(lpc3180_info);
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r_setup = w_setup = 0;
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r_hold = w_hold = 10 / cycle;
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r_width = 30 / cycle;
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w_width = 40 / cycle;
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r_rdy = w_rdy = 100 / cycle;
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/* SLC_TAC: SLC timing arcs register */
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target_write_u32(target, 0x2002002c, (r_setup & 0xf) | ((r_hold & 0xf) << 4) |
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((r_width & 0xf) << 8) | ((r_rdy & 0xf) << 12) | ((w_setup & 0xf) << 16) |
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((w_hold & 0xf) << 20) | ((w_width & 0xf) << 24) | ((w_rdy & 0xf) << 28));
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((w_hold & 0xf) << 20) | ((w_width & 0xf) << 24) | ((w_rdy & 0xf) << 28));
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lpc3180_reset(device);
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}
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return ERROR_OK;
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}
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@ -312,13 +312,13 @@ static int lpc3180_reset(struct nand_device_s *device)
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{
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lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
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target_t *target = lpc3180_info->target;
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if (target->state != TARGET_HALTED)
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{
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LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
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return ERROR_NAND_OPERATION_FAILED;
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}
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if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
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{
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LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
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@ -339,14 +339,14 @@ static int lpc3180_reset(struct nand_device_s *device)
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{
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/* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
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target_write_u32(target, 0x20020010, 0x6);
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if (!lpc3180_controller_ready(device, 100))
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{
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LOG_ERROR("LPC3180 NAND controller timed out after reset");
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return ERROR_NAND_OPERATION_TIMEOUT;
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}
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}
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return ERROR_OK;
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}
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@ -354,13 +354,13 @@ static int lpc3180_command(struct nand_device_s *device, u8 command)
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{
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lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
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target_t *target = lpc3180_info->target;
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if (target->state != TARGET_HALTED)
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{
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LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
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return ERROR_NAND_OPERATION_FAILED;
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}
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if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
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{
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LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
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@ -375,8 +375,8 @@ static int lpc3180_command(struct nand_device_s *device, u8 command)
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{
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/* SLC_CMD = command */
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target_write_u32(target, 0x20020008, command);
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}
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}
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return ERROR_OK;
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}
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@ -384,13 +384,13 @@ static int lpc3180_address(struct nand_device_s *device, u8 address)
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{
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lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
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target_t *target = lpc3180_info->target;
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if (target->state != TARGET_HALTED)
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{
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LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
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return ERROR_NAND_OPERATION_FAILED;
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}
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if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
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{
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LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
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@ -406,7 +406,7 @@ static int lpc3180_address(struct nand_device_s *device, u8 address)
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/* SLC_ADDR = address */
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target_write_u32(target, 0x20020004, address);
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}
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return ERROR_OK;
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}
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@ -414,13 +414,13 @@ static int lpc3180_write_data(struct nand_device_s *device, u16 data)
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{
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lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
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target_t *target = lpc3180_info->target;
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if (target->state != TARGET_HALTED)
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{
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LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
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return ERROR_NAND_OPERATION_FAILED;
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}
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if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
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{
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LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
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@ -436,7 +436,7 @@ static int lpc3180_write_data(struct nand_device_s *device, u16 data)
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/* SLC_DATA = data */
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target_write_u32(target, 0x20020000, data);
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}
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return ERROR_OK;
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}
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@ -444,13 +444,13 @@ static int lpc3180_read_data(struct nand_device_s *device, void *data)
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{
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lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
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target_t *target = lpc3180_info->target;
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if (target->state != TARGET_HALTED)
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{
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LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
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return ERROR_NAND_OPERATION_FAILED;
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}
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if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
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{
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LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
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@ -481,7 +481,7 @@ static int lpc3180_read_data(struct nand_device_s *device, void *data)
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/* data = SLC_DATA, must use 32-bit access */
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target_read_u32(target, 0x20020000, &data32);
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if (device->bus_width == 8)
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{
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u8 *data8 = data;
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@ -497,8 +497,8 @@ static int lpc3180_read_data(struct nand_device_s *device, void *data)
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LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
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return ERROR_NAND_OPERATION_FAILED;
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}
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}
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}
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return ERROR_OK;
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}
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@ -508,13 +508,13 @@ static int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data,
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target_t *target = lpc3180_info->target;
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int retval;
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u8 status;
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if (target->state != TARGET_HALTED)
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{
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LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
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return ERROR_NAND_OPERATION_FAILED;
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}
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if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
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{
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LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
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@ -525,30 +525,30 @@ static int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data,
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u8 *page_buffer;
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u8 *oob_buffer;
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int quarter, num_quarters;
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|
||||
|
||||
if (!data && oob)
|
||||
{
|
||||
LOG_ERROR("LPC3180 MLC controller can't write OOB data only");
|
||||
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
|
||||
if (oob && (oob_size > 6))
|
||||
{
|
||||
LOG_ERROR("LPC3180 MLC controller can't write more than 6 bytes of OOB data");
|
||||
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
|
||||
if (data_size > (u32)device->page_size)
|
||||
{
|
||||
LOG_ERROR("data size exceeds page size");
|
||||
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
|
||||
/* MLC_CMD = sequential input */
|
||||
target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
|
||||
|
||||
page_buffer = malloc(512);
|
||||
oob_buffer = malloc(6);
|
||||
oob_buffer = malloc(6);
|
||||
|
||||
if (device->page_size == 512)
|
||||
{
|
||||
|
|
@ -558,7 +558,7 @@ static int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data,
|
|||
/* MLC_ADDR = row */
|
||||
target_write_u32(target, 0x200b8004, page & 0xff);
|
||||
target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
|
||||
|
||||
|
||||
if (device->address_cycles == 4)
|
||||
target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
|
||||
}
|
||||
|
|
@ -572,17 +572,17 @@ static int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data,
|
|||
target_write_u32(target, 0x200b8004, page & 0xff);
|
||||
target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
|
||||
}
|
||||
|
||||
|
||||
/* when using the MLC controller, we have to treat a large page device
|
||||
* as being made out of four quarters, each the size of a small page device
|
||||
*/
|
||||
num_quarters = (device->page_size == 2048) ? 4 : 1;
|
||||
|
||||
|
||||
for (quarter = 0; quarter < num_quarters; quarter++)
|
||||
{
|
||||
int thisrun_data_size = (data_size > 512) ? 512 : data_size;
|
||||
int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
|
||||
|
||||
|
||||
memset(page_buffer, 0xff, 512);
|
||||
if (data)
|
||||
{
|
||||
|
|
@ -590,7 +590,7 @@ static int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data,
|
|||
data_size -= thisrun_data_size;
|
||||
data += thisrun_data_size;
|
||||
}
|
||||
|
||||
|
||||
memset(oob_buffer, 0xff, (device->page_size == 512) ? 6 : 24);
|
||||
if (oob)
|
||||
{
|
||||
|
|
@ -598,38 +598,38 @@ static int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data,
|
|||
oob_size -= thisrun_oob_size;
|
||||
oob += thisrun_oob_size;
|
||||
}
|
||||
|
||||
|
||||
/* write MLC_ECC_ENC_REG to start encode cycle */
|
||||
target_write_u32(target, 0x200b8008, 0x0);
|
||||
|
||||
|
||||
target->type->write_memory(target, 0x200a8000, 4, 128, page_buffer + (quarter * 512));
|
||||
target->type->write_memory(target, 0x200a8000, 1, 6, oob_buffer + (quarter * 6));
|
||||
|
||||
|
||||
/* write MLC_ECC_AUTO_ENC_REG to start auto encode */
|
||||
target_write_u32(target, 0x200b8010, 0x0);
|
||||
|
||||
|
||||
if (!lpc3180_controller_ready(device, 1000))
|
||||
{
|
||||
LOG_ERROR("timeout while waiting for completion of auto encode cycle");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* MLC_CMD = auto program command */
|
||||
target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
|
||||
|
||||
|
||||
if ((retval = nand_read_status(device, &status)) != ERROR_OK)
|
||||
{
|
||||
LOG_ERROR("couldn't read status");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
|
||||
if (status & NAND_STATUS_FAIL)
|
||||
{
|
||||
LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
|
||||
free(page_buffer);
|
||||
free(oob_buffer);
|
||||
}
|
||||
|
|
@ -637,7 +637,7 @@ static int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data,
|
|||
{
|
||||
return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
|
||||
}
|
||||
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
|
|
@ -645,13 +645,13 @@ static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u
|
|||
{
|
||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||
target_t *target = lpc3180_info->target;
|
||||
|
||||
|
||||
if (target->state != TARGET_HALTED)
|
||||
{
|
||||
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
|
||||
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
|
||||
{
|
||||
LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
|
||||
|
|
@ -672,13 +672,13 @@ static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u
|
|||
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
if (data_size > (u32)device->page_size)
|
||||
{
|
||||
LOG_ERROR("data size exceeds page size");
|
||||
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
|
||||
if (device->page_size == 2048)
|
||||
{
|
||||
page_buffer = malloc(2048);
|
||||
|
|
@ -689,10 +689,10 @@ static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u
|
|||
page_buffer = malloc(512);
|
||||
oob_buffer = malloc(16);
|
||||
}
|
||||
|
||||
|
||||
if (!data && oob)
|
||||
{
|
||||
/* MLC_CMD = Read OOB
|
||||
/* MLC_CMD = Read OOB
|
||||
* we can use the READOOB command on both small and large page devices,
|
||||
* as the controller translates the 0x50 command to a 0x0 with appropriate
|
||||
* positioning of the serial buffer read pointer
|
||||
|
|
@ -704,7 +704,7 @@ static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u
|
|||
/* MLC_CMD = Read0 */
|
||||
target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
|
||||
}
|
||||
|
||||
|
||||
if (device->page_size == 512)
|
||||
{
|
||||
/* small page device */
|
||||
|
|
@ -714,7 +714,7 @@ static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u
|
|||
/* MLC_ADDR = row */
|
||||
target_write_u32(target, 0x200b8004, page & 0xff);
|
||||
target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
|
||||
|
||||
|
||||
if (device->address_cycles == 4)
|
||||
target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
|
||||
}
|
||||
|
|
@ -728,24 +728,24 @@ static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u
|
|||
/* MLC_ADDR = row */
|
||||
target_write_u32(target, 0x200b8004, page & 0xff);
|
||||
target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
|
||||
|
||||
|
||||
/* MLC_CMD = Read Start */
|
||||
target_write_u32(target, 0x200b8000, NAND_CMD_READSTART);
|
||||
}
|
||||
|
||||
|
||||
while (page_bytes_done < (u32)device->page_size)
|
||||
{
|
||||
/* MLC_ECC_AUTO_DEC_REG = dummy */
|
||||
target_write_u32(target, 0x200b8014, 0xaa55aa55);
|
||||
|
||||
|
||||
if (!lpc3180_controller_ready(device, 1000))
|
||||
{
|
||||
LOG_ERROR("timeout while waiting for completion of auto decode cycle");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
|
||||
target_read_u32(target, 0x200b8048, &mlc_isr);
|
||||
|
||||
|
||||
if (mlc_isr & 0x8)
|
||||
{
|
||||
if (mlc_isr & 0x40)
|
||||
|
|
@ -753,15 +753,15 @@ static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u
|
|||
LOG_ERROR("uncorrectable error detected: 0x%2.2x", mlc_isr);
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
|
||||
LOG_WARNING("%i symbol error detected and corrected", ((mlc_isr & 0x30) >> 4) + 1);
|
||||
}
|
||||
|
||||
|
||||
if (data)
|
||||
{
|
||||
target->type->read_memory(target, 0x200a8000, 4, 128, page_buffer + page_bytes_done);
|
||||
}
|
||||
|
||||
|
||||
if (oob)
|
||||
{
|
||||
target->type->read_memory(target, 0x200a8000, 4, 4, oob_buffer + oob_bytes_done);
|
||||
|
|
@ -770,13 +770,13 @@ static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u
|
|||
page_bytes_done += 512;
|
||||
oob_bytes_done += 16;
|
||||
}
|
||||
|
||||
|
||||
if (data)
|
||||
memcpy(data, page_buffer, data_size);
|
||||
|
||||
|
||||
if (oob)
|
||||
memcpy(oob, oob_buffer, oob_size);
|
||||
|
||||
|
||||
free(page_buffer);
|
||||
free(oob_buffer);
|
||||
}
|
||||
|
|
@ -784,7 +784,7 @@ static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u
|
|||
{
|
||||
return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
|
||||
}
|
||||
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
|
|
@ -793,20 +793,20 @@ static int lpc3180_controller_ready(struct nand_device_s *device, int timeout)
|
|||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||
target_t *target = lpc3180_info->target;
|
||||
u8 status = 0x0;
|
||||
|
||||
|
||||
if (target->state != TARGET_HALTED)
|
||||
{
|
||||
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
|
||||
do
|
||||
{
|
||||
if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
|
||||
{
|
||||
/* Read MLC_ISR, wait for controller to become ready */
|
||||
target_read_u8(target, 0x200b8048, &status);
|
||||
|
||||
|
||||
if (status & 2)
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -818,7 +818,7 @@ static int lpc3180_controller_ready(struct nand_device_s *device, int timeout)
|
|||
|
||||
alive_sleep(1);
|
||||
} while (timeout-- > 0);
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -826,65 +826,65 @@ static int lpc3180_nand_ready(struct nand_device_s *device, int timeout)
|
|||
{
|
||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||
target_t *target = lpc3180_info->target;
|
||||
|
||||
|
||||
if (target->state != TARGET_HALTED)
|
||||
{
|
||||
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
|
||||
do
|
||||
{
|
||||
if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
|
||||
{
|
||||
{
|
||||
u8 status = 0x0;
|
||||
|
||||
|
||||
/* Read MLC_ISR, wait for NAND flash device to become ready */
|
||||
target_read_u8(target, 0x200b8048, &status);
|
||||
|
||||
|
||||
if (status & 1)
|
||||
return 1;
|
||||
}
|
||||
else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
|
||||
{
|
||||
u32 status = 0x0;
|
||||
|
||||
|
||||
/* Read SLC_STAT and check READY bit */
|
||||
target_read_u32(target, 0x20020018, &status);
|
||||
|
||||
|
||||
if (status & 1)
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
alive_sleep(1);
|
||||
} while (timeout-- > 0);
|
||||
|
||||
return 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int handle_lpc3180_select_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||
{
|
||||
nand_device_t *device = NULL;
|
||||
lpc3180_nand_controller_t *lpc3180_info = NULL;
|
||||
char *selected[] =
|
||||
char *selected[] =
|
||||
{
|
||||
"no", "mlc", "slc"
|
||||
};
|
||||
|
||||
|
||||
if ((argc < 1) || (argc > 2))
|
||||
{
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
}
|
||||
|
||||
|
||||
device = get_nand_device_by_num(strtoul(args[0], NULL, 0));
|
||||
if (!device)
|
||||
{
|
||||
command_print(cmd_ctx, "nand device '#%s' is out of bounds", args[0]);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
|
||||
lpc3180_info = device->controller_priv;
|
||||
|
||||
|
||||
if (argc == 2)
|
||||
{
|
||||
if (strcmp(args[1], "mlc") == 0)
|
||||
|
|
@ -900,8 +900,8 @@ static int handle_lpc3180_select_command(struct command_context_s *cmd_ctx, char
|
|||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
command_print(cmd_ctx, "%s controller selected", selected[lpc3180_info->selected_controller]);
|
||||
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
|
|
|||
320
src/flash/nand.c
320
src/flash/nand.c
File diff suppressed because it is too large
Load Diff
|
|
@ -99,7 +99,7 @@ enum
|
|||
|
||||
typedef struct nand_manufacturer_s
|
||||
{
|
||||
int id;
|
||||
int id;
|
||||
char *name;
|
||||
} nand_manufacturer_t;
|
||||
|
||||
|
|
@ -115,43 +115,43 @@ typedef struct nand_info_s
|
|||
|
||||
/* Option constants for bizarre disfunctionality and real features
|
||||
*/
|
||||
enum {
|
||||
enum {
|
||||
/* Chip can not auto increment pages */
|
||||
NAND_NO_AUTOINCR = 0x00000001,
|
||||
|
||||
|
||||
/* Buswitdh is 16 bit */
|
||||
NAND_BUSWIDTH_16 = 0x00000002,
|
||||
|
||||
|
||||
/* Device supports partial programming without padding */
|
||||
NAND_NO_PADDING = 0x00000004,
|
||||
|
||||
|
||||
/* Chip has cache program function */
|
||||
NAND_CACHEPRG = 0x00000008,
|
||||
|
||||
|
||||
/* Chip has copy back function */
|
||||
NAND_COPYBACK = 0x00000010,
|
||||
|
||||
|
||||
/* AND Chip which has 4 banks and a confusing page / block
|
||||
* assignment. See Renesas datasheet for further information */
|
||||
NAND_IS_AND = 0x00000020,
|
||||
|
||||
|
||||
/* Chip has a array of 4 pages which can be read without
|
||||
* additional ready /busy waits */
|
||||
NAND_4PAGE_ARRAY = 0x00000040,
|
||||
|
||||
|
||||
/* Chip requires that BBT is periodically rewritten to prevent
|
||||
* bits from adjacent blocks from 'leaking' in altering data.
|
||||
* This happens with the Renesas AG-AND chips, possibly others. */
|
||||
BBT_AUTO_REFRESH = 0x00000080,
|
||||
|
||||
|
||||
/* Chip does not require ready check on read. True
|
||||
* for all large page devices, as they do not support
|
||||
* autoincrement.*/
|
||||
NAND_NO_READRDY = 0x00000100,
|
||||
|
||||
|
||||
/* Options valid for Samsung large page devices */
|
||||
NAND_SAMSUNG_LP_OPTIONS = (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK),
|
||||
|
||||
|
||||
/* Options for new chips with large page size. The pagesize and the
|
||||
* erasesize is determined from the extended id bytes
|
||||
*/
|
||||
|
|
@ -175,7 +175,7 @@ enum
|
|||
NAND_CMD_READID = 0x90,
|
||||
NAND_CMD_ERASE2 = 0xd0,
|
||||
NAND_CMD_RESET = 0xff,
|
||||
|
||||
|
||||
/* Extended commands for large page devices */
|
||||
NAND_CMD_READSTART = 0x30,
|
||||
NAND_CMD_RNDOUTSTART = 0xE0,
|
||||
|
|
@ -198,7 +198,7 @@ enum oob_formats
|
|||
NAND_OOB_NONE = 0x0, /* no OOB data at all */
|
||||
NAND_OOB_RAW = 0x1, /* raw OOB data (16 bytes for 512b page sizes, 64 bytes for 2048b page sizes) */
|
||||
NAND_OOB_ONLY = 0x2, /* only OOB data */
|
||||
NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */
|
||||
NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */
|
||||
NAND_OOB_HW_ECC = 0x20, /* when writing, use HW ECC (as opposed to no ECC) */
|
||||
NAND_OOB_SW_ECC_KW = 0x40, /* when writing, use Marvell's Kirkwood bootrom format */
|
||||
NAND_OOB_JFFS2 = 0x100, /* when writing, use JFFS2 OOB layout */
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@ static int s3c2410_nand_device_command(struct command_context_s *cmd_ctx, char *
|
|||
struct nand_device_s *device)
|
||||
{
|
||||
s3c24xx_nand_controller_t *info;
|
||||
|
||||
|
||||
info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device);
|
||||
if (info == NULL) {
|
||||
return ERROR_NAND_DEVICE_INVALID;
|
||||
|
|
@ -70,7 +70,7 @@ static int s3c2410_nand_device_command(struct command_context_s *cmd_ctx, char *
|
|||
info->addr = S3C2410_NFADDR;
|
||||
info->data = S3C2410_NFDATA;
|
||||
info->nfstat = S3C2410_NFSTAT;
|
||||
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
|
|
@ -79,7 +79,7 @@ static int s3c2410_init(struct nand_device_s *device)
|
|||
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
|
||||
target_t *target = s3c24xx_info->target;
|
||||
|
||||
target_write_u32(target, S3C2410_NFCONF,
|
||||
target_write_u32(target, S3C2410_NFCONF,
|
||||
S3C2410_NFCONF_EN | S3C2410_NFCONF_TACLS(3) |
|
||||
S3C2410_NFCONF_TWRPH0(5) | S3C2410_NFCONF_TWRPH1(3));
|
||||
|
||||
|
|
@ -95,7 +95,7 @@ static int s3c2410_write_data(struct nand_device_s *device, u16 data)
|
|||
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
|
||||
target_write_u32(target, S3C2410_NFDATA, data);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
|
@ -104,13 +104,13 @@ static int s3c2410_read_data(struct nand_device_s *device, void *data)
|
|||
{
|
||||
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
|
||||
target_t *target = s3c24xx_info->target;
|
||||
|
||||
|
||||
if (target->state != TARGET_HALTED) {
|
||||
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
target_read_u8(target, S3C2410_NFDATA, data);
|
||||
target_read_u8(target, S3C2410_NFDATA, data);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
|
|
@ -124,14 +124,14 @@ static int s3c2410_nand_ready(struct nand_device_s *device, int timeout)
|
|||
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
|
||||
do {
|
||||
target_read_u8(target, S3C2410_NFSTAT, &status);
|
||||
|
||||
|
||||
if (status & S3C2410_NFSTAT_BUSY)
|
||||
return 1;
|
||||
|
||||
alive_sleep(1);
|
||||
alive_sleep(1);
|
||||
} while (timeout-- > 0);
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@ static int s3c2412_nand_device_command(struct command_context_s *cmd_ctx, char *
|
|||
info->addr = S3C2440_NFADDR;
|
||||
info->data = S3C2440_NFDATA;
|
||||
info->nfstat = S3C2412_NFSTAT;
|
||||
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@ static int s3c2440_nand_device_command(struct command_context_s *cmd_ctx, char *
|
|||
struct nand_device_s *device)
|
||||
{
|
||||
s3c24xx_nand_controller_t *info;
|
||||
|
||||
|
||||
info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device);
|
||||
if (info == NULL) {
|
||||
return ERROR_NAND_DEVICE_INVALID;
|
||||
|
|
@ -70,7 +70,7 @@ static int s3c2440_nand_device_command(struct command_context_s *cmd_ctx, char *
|
|||
info->addr = S3C2440_NFADDR;
|
||||
info->data = S3C2440_NFDATA;
|
||||
info->nfstat = S3C2440_NFSTAT;
|
||||
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
|
|
@ -100,10 +100,10 @@ int s3c2440_nand_ready(struct nand_device_s *device, int timeout)
|
|||
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
do {
|
||||
|
||||
do {
|
||||
target_read_u8(target, s3c24xx_info->nfstat, &status);
|
||||
|
||||
|
||||
if (status & S3C2440_NFSTAT_READY)
|
||||
return 1;
|
||||
|
||||
|
|
@ -130,7 +130,7 @@ int s3c2440_read_block_data(struct nand_device_s *device, u8 *data, int data_siz
|
|||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
while (data_size >= 4) {
|
||||
while (data_size >= 4) {
|
||||
target_read_u32(target, nfdata, &tmp);
|
||||
|
||||
data[0] = tmp;
|
||||
|
|
@ -164,7 +164,7 @@ int s3c2440_write_block_data(struct nand_device_s *device, u8 *data, int data_si
|
|||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
while (data_size >= 4) {
|
||||
while (data_size >= 4) {
|
||||
tmp = le_to_h_u32(data);
|
||||
target_write_u32(target, nfdata, tmp);
|
||||
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ static int s3c2443_nand_device_command(struct command_context_s *cmd_ctx, char *
|
|||
struct nand_device_s *device)
|
||||
{
|
||||
s3c24xx_nand_controller_t *info;
|
||||
|
||||
|
||||
info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device);
|
||||
if (info == NULL) {
|
||||
return ERROR_NAND_DEVICE_INVALID;
|
||||
|
|
@ -69,7 +69,7 @@ static int s3c2443_nand_device_command(struct command_context_s *cmd_ctx, char *
|
|||
info->addr = S3C2440_NFADDR;
|
||||
info->data = S3C2440_NFDATA;
|
||||
info->nfstat = S3C2412_NFSTAT;
|
||||
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ s3c24xx_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
|
|||
struct nand_device_s *device)
|
||||
{
|
||||
s3c24xx_nand_controller_t *s3c24xx_info;
|
||||
|
||||
|
||||
s3c24xx_info = malloc(sizeof(s3c24xx_nand_controller_t));
|
||||
if (s3c24xx_info == NULL) {
|
||||
LOG_ERROR("no memory for nand controller\n");
|
||||
|
|
@ -69,9 +69,9 @@ int s3c24xx_reset(struct nand_device_s *device)
|
|||
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
|
||||
target_write_u32(target, s3c24xx_info->cmd, 0xff);
|
||||
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
|
|
@ -79,7 +79,7 @@ int s3c24xx_command(struct nand_device_s *device, u8 command)
|
|||
{
|
||||
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
|
||||
target_t *target = s3c24xx_info->target;
|
||||
|
||||
|
||||
if (target->state != TARGET_HALTED) {
|
||||
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
|
|
@ -94,12 +94,12 @@ int s3c24xx_address(struct nand_device_s *device, u8 address)
|
|||
{
|
||||
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
|
||||
target_t *target = s3c24xx_info->target;
|
||||
|
||||
|
||||
if (target->state != TARGET_HALTED) {
|
||||
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
|
||||
target_write_u16(target, s3c24xx_info->addr, address);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
|
@ -113,7 +113,7 @@ int s3c24xx_write_data(struct nand_device_s *device, u16 data)
|
|||
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
|
||||
target_write_u8(target, s3c24xx_info->data, data);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
|
@ -122,7 +122,7 @@ int s3c24xx_read_data(struct nand_device_s *device, void *data)
|
|||
{
|
||||
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
|
||||
target_t *target = s3c24xx_info->target;
|
||||
|
||||
|
||||
if (target->state != TARGET_HALTED) {
|
||||
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
|
|
|
|||
|
|
@ -30,12 +30,12 @@
|
|||
typedef struct s3c24xx_nand_controller_s
|
||||
{
|
||||
struct target_s *target;
|
||||
|
||||
|
||||
/* register addresses */
|
||||
u32 cmd;
|
||||
u32 addr;
|
||||
u32 data;
|
||||
u32 nfstat;
|
||||
u32 nfstat;
|
||||
} s3c24xx_nand_controller_t;
|
||||
|
||||
/* Default to using the un-translated NAND register based address */
|
||||
|
|
|
|||
|
|
@ -47,7 +47,6 @@ typedef struct stellaris_flash_bank_s
|
|||
u32 rcc;
|
||||
u8 mck_valid;
|
||||
u32 mck_freq;
|
||||
|
||||
} stellaris_flash_bank_t;
|
||||
|
||||
/* STELLARIS control registers */
|
||||
|
|
@ -66,7 +65,7 @@ typedef struct stellaris_flash_bank_s
|
|||
|
||||
#define FMPRE 0x130
|
||||
#define FMPPE 0x134
|
||||
#define USECRL 0x140
|
||||
#define USECRL 0x140
|
||||
|
||||
#define FLASH_CONTROL_BASE 0x400FD000
|
||||
#define FLASH_FMA (FLASH_CONTROL_BASE|0x000)
|
||||
|
|
@ -87,7 +86,7 @@ typedef struct stellaris_flash_bank_s
|
|||
#define FMC_COMT (1<<3)
|
||||
#define FMC_MERASE (1<<2)
|
||||
#define FMC_ERASE (1<<1)
|
||||
#define FMC_WRITE (1<<0)
|
||||
#define FMC_WRITE (1<<0)
|
||||
|
||||
/* STELLARIS constants */
|
||||
|
||||
|
|
|
|||
|
|
@ -66,17 +66,17 @@ typedef struct stm32x_flash_bank_s
|
|||
|
||||
#define FLASH_PG (1<<0)
|
||||
#define FLASH_PER (1<<1)
|
||||
#define FLASH_MER (1<<2)
|
||||
#define FLASH_MER (1<<2)
|
||||
#define FLASH_OPTPG (1<<4)
|
||||
#define FLASH_OPTER (1<<5)
|
||||
#define FLASH_STRT (1<<6)
|
||||
#define FLASH_LOCK (1<<7)
|
||||
#define FLASH_OPTWRE (1<<9)
|
||||
|
||||
/* FLASH_SR regsiter bits */
|
||||
/* FLASH_SR register bits */
|
||||
|
||||
#define FLASH_BSY (1<<0)
|
||||
#define FLASH_PGERR (1<<2)
|
||||
#define FLASH_PGERR (1<<2)
|
||||
#define FLASH_WRPRTERR (1<<4)
|
||||
#define FLASH_EOP (1<<5)
|
||||
|
||||
|
|
|
|||
|
|
@ -59,14 +59,14 @@ enum str7x_status_codes
|
|||
#define FLASH_AR 0x00000010
|
||||
#define FLASH_ER 0x00000014
|
||||
#define FLASH_NVWPAR 0x0000DFB0
|
||||
#define FLASH_NVAPR0 0x0000DFB8
|
||||
#define FLASH_NVAPR1 0x0000DFBC
|
||||
#define FLASH_NVAPR0 0x0000DFB8
|
||||
#define FLASH_NVAPR1 0x0000DFBC
|
||||
|
||||
/* FLASH_CR0 register bits */
|
||||
|
||||
#define FLASH_WMS 0x80000000
|
||||
#define FLASH_SUSP 0x40000000
|
||||
#define FLASH_WPG 0x20000000
|
||||
#define FLASH_WPG 0x20000000
|
||||
#define FLASH_DWPG 0x10000000
|
||||
#define FLASH_SER 0x08000000
|
||||
#define FLASH_SPR 0x01000000
|
||||
|
|
@ -76,7 +76,7 @@ enum str7x_status_codes
|
|||
#define FLASH_BSYA1 0x00000004
|
||||
#define FLASH_BSYA0 0x00000002
|
||||
|
||||
/* FLASH_CR1 regsiter bits */
|
||||
/* FLASH_CR1 register bits */
|
||||
|
||||
#define FLASH_B1S 0x02000000
|
||||
#define FLASH_B0S 0x01000000
|
||||
|
|
|
|||
Loading…
Reference in New Issue