ARM11: switch to new "arm" base type
This will enable reusing many common ARM utilities, in particular the ETM and ETB support. The ARM11 support can still be much simplified after this patch, though. Note: none of those common utilities kick in yet... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>__archive__
David Brownell
parent
04b514707f
commit
a7f5cdf999
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@ -689,9 +689,7 @@ static int arm11_poll(struct target *target)
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{
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FNC_INFO;
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int retval;
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struct arm11_common * arm11 = target->arch_info;
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struct arm11_common *arm11 = target_to_arm11(target);
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uint32_t dscr;
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CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
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@ -732,7 +730,7 @@ static int arm11_poll(struct target *target)
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/* architecture specific status reply */
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static int arm11_arch_state(struct target *target)
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{
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struct arm11_common * arm11 = target->arch_info;
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struct arm11_common *arm11 = target_to_arm11(target);
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LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
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Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
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@ -755,8 +753,7 @@ static int arm11_target_request_data(struct target *target,
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static int arm11_halt(struct target *target)
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{
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FNC_INFO;
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struct arm11_common * arm11 = target->arch_info;
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struct arm11_common *arm11 = target_to_arm11(target);
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LOG_DEBUG("target->state: %s",
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target_state_name(target));
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@ -825,7 +822,7 @@ static int arm11_resume(struct target *target, int current,
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// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
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// current, address, handle_breakpoints, debug_execution);
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struct arm11_common * arm11 = target->arch_info;
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struct arm11_common *arm11 = target_to_arm11(target);
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LOG_DEBUG("target->state: %s",
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target_state_name(target));
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@ -1044,7 +1041,7 @@ static int arm11_step(struct target *target, int current,
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return ERROR_TARGET_NOT_HALTED;
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}
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struct arm11_common * arm11 = target->arch_info;
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struct arm11_common *arm11 = target_to_arm11(target);
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if (!current)
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R(PC) = address;
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@ -1190,8 +1187,8 @@ static int arm11_assert_reset(struct target *target)
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{
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FNC_INFO;
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int retval;
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struct arm11_common *arm11 = target_to_arm11(target);
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struct arm11_common * arm11 = target->arch_info;
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retval = arm11_check_init(arm11, NULL);
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if (retval != ERROR_OK)
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return retval;
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@ -1265,8 +1262,7 @@ static int arm11_get_gdb_reg_list(struct target *target,
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struct reg **reg_list[], int *reg_list_size)
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{
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FNC_INFO;
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struct arm11_common * arm11 = target->arch_info;
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struct arm11_common *arm11 = target_to_arm11(target);
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*reg_list_size = ARM11_GDB_REGISTER_COUNT;
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*reg_list = malloc(sizeof(struct reg*) * ARM11_GDB_REGISTER_COUNT);
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@ -1314,7 +1310,7 @@ static int arm11_read_memory_inner(struct target *target,
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LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
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struct arm11_common * arm11 = target->arch_info;
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struct arm11_common *arm11 = target_to_arm11(target);
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retval = arm11_run_instr_data_prepare(arm11);
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if (retval != ERROR_OK)
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@ -1410,7 +1406,7 @@ static int arm11_write_memory_inner(struct target *target,
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LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
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struct arm11_common * arm11 = target->arch_info;
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struct arm11_common *arm11 = target_to_arm11(target);
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retval = arm11_run_instr_data_prepare(arm11);
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if (retval != ERROR_OK)
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@ -1572,8 +1568,7 @@ static int arm11_add_breakpoint(struct target *target,
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struct breakpoint *breakpoint)
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{
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FNC_INFO;
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struct arm11_common * arm11 = target->arch_info;
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struct arm11_common *arm11 = target_to_arm11(target);
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#if 0
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if (breakpoint->type == BKPT_SOFT)
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@ -1604,8 +1599,7 @@ static int arm11_remove_breakpoint(struct target *target,
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struct breakpoint *breakpoint)
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{
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FNC_INFO;
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struct arm11_common * arm11 = target->arch_info;
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struct arm11_common *arm11 = target_to_arm11(target);
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arm11->free_brps++;
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@ -1636,7 +1630,7 @@ static int arm11_run_algorithm(struct target *target,
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uint32_t entry_point, uint32_t exit_point,
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int timeout_ms, void *arch_info)
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{
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struct arm11_common *arm11 = target->arch_info;
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struct arm11_common *arm11 = target_to_arm11(target);
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// enum armv4_5_state core_state = arm11->core_state;
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// enum armv4_5_mode core_mode = arm11->core_mode;
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uint32_t context[16];
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@ -1813,7 +1807,13 @@ static int arm11_target_create(struct target *target, Jim_Interp *interp)
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return ERROR_COMMAND_SYNTAX_ERROR;
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}
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target->arch_info = arm11;
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armv4_5_init_arch_info(target, &arm11->arm);
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arm11->jtag_info.tap = target->tap;
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arm11->jtag_info.scann_size = 5;
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arm11->jtag_info.scann_instr = ARM11_SCAN_N;
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/* cur_scan_chain == 0 */
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arm11->jtag_info.intest_instr = ARM11_INTEST;
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return ERROR_OK;
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}
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@ -1831,8 +1831,7 @@ static int arm11_examine(struct target *target)
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int retval;
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FNC_INFO;
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struct arm11_common * arm11 = target->arch_info;
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struct arm11_common *arm11 = target_to_arm11(target);
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/* check IDCODE */
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@ -1865,11 +1864,9 @@ static int arm11_examine(struct target *target)
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case 0x07B56000: LOG_INFO("found ARM1156"); break;
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case 0x07B76000: LOG_INFO("found ARM1176"); break;
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default:
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{
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LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
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return ERROR_FAIL;
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}
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}
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arm11->debug_version = (arm11->didr >> 16) & 0x0F;
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@ -1923,8 +1920,8 @@ static int arm11_get_reg(struct reg *reg)
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/** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
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#if 0
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struct arm11_common *arm11 = target->arch_info;
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const struct arm11_reg_defs * arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
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struct arm11_common *arm11 = target_to_arm11(target);
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const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
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#endif
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return ERROR_OK;
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@ -1935,9 +1932,9 @@ static int arm11_set_reg(struct reg *reg, uint8_t *buf)
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{
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FNC_INFO;
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struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target;
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struct arm11_common *arm11 = target->arch_info;
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// const struct arm11_reg_defs * arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
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struct target *target = ((struct arm11_reg_state *)reg->arch_info)->target;
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struct arm11_common *arm11 = target_to_arm11(target);
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// const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
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arm11->reg_values[((struct arm11_reg_state *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
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reg->valid = 1;
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@ -1948,7 +1945,7 @@ static int arm11_set_reg(struct reg *reg, uint8_t *buf)
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static int arm11_build_reg_cache(struct target *target)
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{
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struct arm11_common *arm11 = target->arch_info;
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struct arm11_common *arm11 = target_to_arm11(target);
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NEW(struct reg_cache, cache, 1);
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NEW(struct reg, reg_list, ARM11_REGCACHE_COUNT);
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@ -2107,14 +2104,13 @@ static int arm11_mrc_inner(struct target *target, int cpnum,
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uint32_t *value, bool read)
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{
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int retval;
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struct arm11_common *arm11 = target_to_arm11(target);
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if (target->state != TARGET_HALTED)
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{
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LOG_ERROR("Target not halted");
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return ERROR_FAIL;
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}
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struct arm11_common * arm11 = target->arch_info;
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uint32_t instr = 0xEE000010 |
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(cpnum << 8) |
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@ -23,9 +23,7 @@
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#ifndef ARM11_H
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#define ARM11_H
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#include "target.h"
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#include "register.h"
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#include "jtag.h"
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#include "armv4_5.h"
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#define asizeof(x) (sizeof(x) / sizeof((x)[0]))
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@ -80,6 +78,7 @@ enum arm11_debug_version
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struct arm11_common
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{
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struct arm arm;
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struct target * target; /**< Reference back to the owner */
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/** \name Processor type detection */
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@ -117,8 +116,15 @@ struct arm11_common
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// GA
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struct reg_cache *core_cache;
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struct arm_jtag jtag_info;
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};
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static inline struct arm11_common *target_to_arm11(struct target *target)
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{
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return container_of(target->arch_info, struct arm11_common,
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arm);
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}
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/**
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* ARM11 DBGTAP instructions
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@ -178,6 +178,8 @@ int arm11_add_debug_SCAN_N(struct arm11_common * arm11, uint8_t chain, tap_state
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arm11_in_handler_SCAN_N(tmp);
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arm11->jtag_info.cur_scan_chain = chain;
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return jtag_execute_queue();
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}
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