Tcl and doc: update to match new 'arm mcr ...' etc
Make them match the C code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>__archive__
David Brownell
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48edd58c39
commit
a65e75ea34
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NEWS
2
NEWS
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@ -15,6 +15,8 @@ Target Layer:
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- recognize TrustZone "Secure Monitor" mode
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- "arm regs" command output changed
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- register names use "sp" not "r13"
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- add top-level "mcr" and "mrc" commands, replacing
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various core-specific operations
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ARM11
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- Preliminary ETM and ETB hookup
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- accelerated "flash erase_check"
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@ -1524,7 +1524,7 @@ proc setc15 @{regs value@} @{
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echo [format "set p15 0x%04x, 0x%08x" $regs $value]
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mcr 15 [expr ($regs>>12)&0x7] \
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arm mcr 15 [expr ($regs>>12)&0x7] \
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[expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
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[expr ($regs>>8)&0x7] $value
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@}
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@ -5609,6 +5609,24 @@ with a handful of exceptions.
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ThumbEE disassembly currently has no explicit support.
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@end deffn
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@deffn Command {arm mcr} pX op1 CRn CRm op2 value
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Write @var{value} to a coprocessor @var{pX} register
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passing parameters @var{CRn},
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@var{CRm}, opcodes @var{opc1} and @var{opc2},
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and using the MCR instruction.
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(Parameter sequence matches the ARM instruction, but omits
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an ARM register.)
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@end deffn
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@deffn Command {arm mrc} pX coproc op1 CRn CRm op2
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Read a coprocessor @var{pX} register passing parameters @var{CRn},
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@var{CRm}, opcodes @var{opc1} and @var{opc2},
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and the MRC instruction.
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Returns the result so it can be manipulated by Jim scripts.
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(Parameter sequence matches the ARM instruction, but omits
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an ARM register.)
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@end deffn
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@deffn Command {arm reg}
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Display a table of all banked core registers, fetching the current value from every
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core mode if necessary.
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@ -19,13 +19,13 @@ proc csb732_init { } {
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# We assume the interpreter latency is enough.
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# Allow access to all coprocessors
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mcr 15 0 15 1 0 0x2001
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arm mcr 15 0 15 1 0 0x2001
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# Disable MMU, caches, write buffer
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mcr 15 0 1 0 0 0x78
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arm mcr 15 0 1 0 0 0x78
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# Grant manager access to all domains
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mcr 15 0 3 0 0 0xFFFFFFFF
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arm mcr 15 0 3 0 0 0xFFFFFFFF
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# Set ARM clock to 532 MHz, AHB to 133 MHz
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mww 0x53F80004 0x1000
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@ -182,7 +182,7 @@ proc dm355evm_init {} {
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########################
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# turn on icache - set I bit in cp15 register c1
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mcr 15 0 0 1 0 0x00051078
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arm mcr 15 0 0 1 0 0x00051078
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}
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# NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
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@ -29,7 +29,7 @@ proc openrd_init { } {
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jtag_reset 0 0
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wait_halt
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mcr 15 0 0 1 0 0x00052078
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arm mcr 15 0 0 1 0 0x00052078
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mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
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mww 0xD0001404 0x37543000 # Dunit Control Low Register
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@ -29,7 +29,7 @@ proc sheevaplug_init { } {
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jtag_reset 0 0
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wait_halt
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mcr 15 0 0 1 0 0x00052078
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arm mcr 15 0 0 1 0 0x00052078
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mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
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mww 0xD0001404 0x39543000 # Dunit Control Low Register
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@ -436,22 +436,22 @@ proc initC100 {} {
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# */
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# mov r0, #0
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# mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
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mcr 15 0 7 7 0 0x0
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arm mcr 15 0 7 7 0 0x0
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# mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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mcr 15 0 8 7 0 0x0
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arm mcr 15 0 8 7 0 0x0
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# /*
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# * disable MMU stuff and caches
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# */
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# mrc p15, 0, r0, c1, c0, 0
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mrc 15 0 1 0 0
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arm mrc 15 0 1 0 0
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# bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
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# bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
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# orr r0, r0, #0x00000002 @ set bit 2 (A) Align
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# orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
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# orr r0, r0, #0x00400000 @ set bit 22 (U)
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# mcr p15, 0, r0, c1, c0, 0
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mcr 15 0 1 0 0 0x401002
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arm mcr 15 0 1 0 0 0x401002
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# This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c
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# APB init
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# // Setting APB Bus Wait states to 1, set post write
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@ -10,7 +10,7 @@ proc setc15 {regs value} {
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echo [format "set p15 0x%04x, 0x%08x" $regs $value]
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mcr 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value
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arm mcr 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value
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}
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