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aarch64: implement mmu on/off for aarch32 

add decoding of aarch32 core modes (register layout is compatible)

Change-Id: I34c3146a7b1f836d3006be2b76b036da055b3d3e
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4374
Tested-by: jenkins
Reviewed-by: Forest Crossman <cyrozap@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
compliance_dev
Matthias Welwarsky 2018-01-22 12:28:37 +01:00 committed by Matthias Welwarsky
parent 64f1f7b1c1
commit a640f139ba
1 changed files with 9 additions and 1 deletions
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10
src/target/aarch64.c
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@ -161,8 +161,16 @@ static int aarch64_mmu_modify(struct target *target, int enable)
case ARMV8_64_EL3T:
instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL3, 0);
break;
case ARM_MODE_SVC:
case ARM_MODE_ABT:
case ARM_MODE_FIQ:
case ARM_MODE_IRQ:
instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
break;
default:
LOG_DEBUG("unknown cpu state 0x%x" PRIx32, armv8->arm.core_state);
LOG_DEBUG("unknown cpu state 0x%" PRIx32, armv8->arm.core_mode);
break;
}