From e12f5575ef408fc83b66851b8c2ed05503509a49 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Mon, 22 May 2017 22:02:01 -0700
Subject: [PATCH] riscv-v11: Don't perform unexpected operation in cache_write

---
 src/target/riscv/riscv-011.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c
index 8663082b2..6ed3ba12b 100644
--- a/src/target/riscv/riscv-011.c
+++ b/src/target/riscv/riscv-011.c
@@ -872,7 +872,7 @@ static int cache_write(struct target *target, unsigned int address, bool run)
 
 	if (last == info->dramsize) {
 		// Nothing needs to be written to RAM.
-		dbus_write(target, DMCONTROL, DMCONTROL_HALTNOT | DMCONTROL_INTERRUPT);
+	        dbus_write(target, DMCONTROL, DMCONTROL_HALTNOT | (run ? DMCONTROL_INTERRUPT : 0));
 
 	} else {
 		for (unsigned int i = 0; i < info->dramsize; i++) {