Add LPC8Nxx and NHS3xx support.
Change-Id: I0bdbca8dd9b234aca355230af7269463c9f70bd1 Signed-off-by: Jean-Christian de Rivaz <jcamdr70@gmail.com> Reviewed-on: http://openocd.zylin.com/4515 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>log_output
Jean-Christian de Rivaz
Tomas Vanek
parent
fdaa8711ae
commit
a15c11d7d0
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@ -5900,8 +5900,8 @@ Command disables watchdog timer.
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@deffn {Flash Driver} lpc2000
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This is the driver to support internal flash of all members of the
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LPC11(x)00 and LPC1300 microcontroller families and most members of
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the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000 and LPC54100
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microcontroller families from NXP.
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the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000, LPC54100,
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LPC8Nxx and NHS31xx microcontroller families from NXP.
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@quotation Note
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There are LPC2000 devices which are not supported by the @var{lpc2000}
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@ -5926,7 +5926,7 @@ LPC43x[2357])
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@option{lpc54100} (LPC541xx)
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@option{lpc4000} (LPC40xx)
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or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
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LPC8xx, LPC13xx, LPC17xx and LPC40xx
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LPC8xx, LPC13xx, LPC17xx, LPC40xx, LPC8Nxx and NHS31xx
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@item @var{clock_kHz} ... the frequency, in kiloHertz,
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at which the core is running
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@item @option{calc_checksum} ... optional (but you probably want to provide this!),
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@ -12,6 +12,9 @@
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* by Nemui Trinomius *
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* nemuisan_kawausogasuki@live.jp *
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* *
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* LPC8N04/HNS31xx support Copyright (C) 2018 *
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* by Jean-Christian de Rivaz jcdr [at] innodelec [dot] ch *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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@ -38,7 +41,7 @@
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/**
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* @file
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* flash programming support for NXP LPC8xx,LPC1xxx,LPC4xxx,LP5410x and LPC2xxx devices.
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* flash programming support for NXP LPC8xx,LPC1xxx,LPC4xxx,LP5410x,LPC2xxx and NHS31xx devices.
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*
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* @todo Provide a way to update CCLK after declaring the flash bank. The value which is correct after chip reset will
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* rarely still work right after the clocks switch to use the PLL (e.g. 4MHz --> 100 MHz).
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@ -77,6 +80,8 @@
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* lpc800:
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* - 810 | 1 | 2 (tested with LPC810/LPC811/LPC812)
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* - 822 | 4 (tested with LPC824)
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* - 8N04
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* - NHS31xx (tested with NHS3100)
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*
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* lpc1100:
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* - 11xx
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@ -111,6 +116,8 @@
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* - 408x
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* - 81x
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* - 82x
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* - 8N04
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* - NHS31xx
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*/
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/* Part IDs for autodetection */
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@ -257,6 +264,11 @@
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#define LPC824_201 0x00008241
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#define LPC824_201_1 0x00008242
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#define LPC8N04 0x00008A04
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#define NHS3100 0x4e310020
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#define NHS3152 0x4e315220
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#define NHS3153 0x4e315320 /* Only specified in Rev.1 of the datasheet */
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#define IAP_CODE_LEN 0x34
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#define LPC11xx_REG_SECTORS 24
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@ -526,6 +538,10 @@ static int lpc2000_build_sector_list(struct flash_bank *bank)
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case 16 * 1024:
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bank->num_sectors = 16;
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break;
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case 30 * 1024:
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lpc2000_info->cmd51_max_buffer = 1024; /* For LPC8N04 and NHS31xx, have 8kB of SRAM */
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bank->num_sectors = 30; /* There have only 30kB of writable Flash out of 32kB */
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break;
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case 32 * 1024:
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lpc2000_info->cmd51_max_buffer = 1024; /* For LPC824, has 8kB of SRAM */
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bank->num_sectors = 32;
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@ -1452,6 +1468,14 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank)
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bank->size = 32 * 1024;
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break;
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case LPC8N04:
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case NHS3100:
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case NHS3152:
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case NHS3153:
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lpc2000_info->variant = lpc800;
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bank->size = 30 * 1024;
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break;
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default:
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LOG_ERROR("BUG: unknown Part ID encountered: 0x%" PRIx32, part_id);
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exit(-1);
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@ -0,0 +1,81 @@
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# NXP LPC8Nxx NHS31xx Cortex-M0+ with 8kB SRAM
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# Copyright (C) 2018 by Jean-Christian de Rivaz
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# Based on NXP proposal https://community.nxp.com/message/1011149
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# Many thanks to Dries Moors from NXP support.
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# SWD only transport
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME lpc8nxx
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id 0
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
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if {![using_hla]} {
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# If srst is not fitted use SYSRESETREQ to perform a soft reset
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cortex_m reset_config sysresetreq
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}
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adapter_nsrst_delay 100
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$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x1ff0 -work-area-backup 0
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flash bank $_CHIPNAME.flash lpc2000 0x0 0x7800 0 0 $_TARGETNAME lpc800 500
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echo "*********************************************************************************"
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echo "* !!!!! IMPORTANT NOTICE FOR LPC8Nxx and NHS31xx CHIPS !!!!!"
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echo "* When this IC is in power-off or peep power down mode, the SWD HW block is also"
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echo "* unpowered. These modes can be entered by firmware. The default firmware image"
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echo "* (flashed in production) makes use of this. Best is to avoid these power modes"
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echo "* during development, and only later add them when the functionality is complete."
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echo "* Hardware reset or NFC field are the only ways to connect in case the SWD is"
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echo "* powered off. OpenOCD can do a hardware reset if you wire the adapter SRST"
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echo "* signal to the chip RESETN pin and add the following in your configuration:"
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echo "* reset_config srst_only; flash init; catch init; reset"
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echo "* But if the actual firmware immediately set the power down mode after reset,"
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echo "* OpenOCD might be not fast enough to halt the CPU before the SWD lost power. In"
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echo "* that case the only solution is to apply a NFC field to keep the SWD powered."
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echo "*********************************************************************************"
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# Using soft-reset 'reset_config none' is strongly discouraged.
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# RESETN sets the system clock to 500 kHz. Unlike soft-reset does not.
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# Set the system clock to 500 kHz before reset to simulate the functionality of hw reset.
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#
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proc set_sysclk_500khz {} {
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set SYSCLKCTRL 0x40048020
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set SYSCLKUEN 0x40048024
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mww $SYSCLKUEN 0
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mmw $SYSCLKCTRL 0x8 0xe
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mww $SYSCLKUEN 1
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echo "Notice: sysclock set to 500kHz."
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}
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# Do not remap the ARM interrupt vectors to anything but the beginning ot the flash.
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# Table System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
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# Bit Symbol Value Description
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# 0 map - interrupt vector remap. 0 after boot.
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# 0 interrupt vector reside in Flash
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# 1 interrupt vector reside in SRAM
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# 5:1 offset - system memory remap offset. 00000b after boot.
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# 00000b interrupt vectors in flash or remapped to SRAM but no offset
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# 00001b -
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# 00111b interrupt vectors offset in flash or SRAM to 1K word segment
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# 01000b -
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# 11111b interrupt vectors offset in flash to 1K word segment 8 to 31
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# 31:6 reserved
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#
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proc set_no_remap {} {
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mww 0x40048000 0x00
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echo "Notice: interrupt vector set to no remap."
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}
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$_TARGETNAME configure -event reset-init {
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set_sysclk_500khz
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set_no_remap
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}
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@ -0,0 +1,4 @@
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# NXP NHS31xx Cortex-M0+ with 8kB SRAM
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set CHIPNAME nhs31xx
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source [find target/lpc8nxx.cfg]
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