more xscale cleanup (mostly removing JTAG hooks)
Streamline/shrink some needless JTAG stuff: - Use #defines for the JTAG instructions; they can't ever change - Remove an unused (!) shadow of tap->ir_length - Stop using a copy of target->tap - Don't bother saving the variant after sanity checking ir_length Also, make target_create() work as on other targets: build the register cache later, making init_target() no longer be a NOP. Handle malloc failure; remove a comment that was obsoleted by the not-so-new target syntax. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>__archive__
David Brownell
parent
026559068d
commit
9f6c23f479
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@ -202,23 +202,23 @@ static int xscale_read_dcsr(target_t *target)
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uint8_t field2_check_mask = 0x1;
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jtag_set_end_state(TAP_DRPAUSE);
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xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
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xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR);
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buf_set_u32(&field0, 1, 1, xscale->hold_rst);
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buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
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fields[0].tap = xscale->jtag_info.tap;
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fields[0].tap = target->tap;
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fields[0].num_bits = 3;
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fields[0].out_value = &field0;
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uint8_t tmp;
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fields[0].in_value = &tmp;
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fields[1].tap = xscale->jtag_info.tap;
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fields[1].tap = target->tap;
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fields[1].num_bits = 32;
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fields[1].out_value = NULL;
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fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
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fields[2].tap = xscale->jtag_info.tap;
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fields[2].tap = target->tap;
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fields[2].num_bits = 1;
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fields[2].out_value = &field2;
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uint8_t tmp2;
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@ -267,12 +267,8 @@ static int xscale_receive(target_t *target, uint32_t *buffer, int num_words)
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return ERROR_INVALID_ARGUMENTS;
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int retval = ERROR_OK;
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armv4_5_common_t *armv4_5 = target->arch_info;
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xscale_common_t *xscale = armv4_5->arch_info;
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tap_state_t path[3];
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scan_field_t fields[3];
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uint8_t *field0 = malloc(num_words * 1);
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uint8_t field0_check_value = 0x2;
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uint8_t field0_check_mask = 0x6;
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@ -288,20 +284,20 @@ static int xscale_receive(target_t *target, uint32_t *buffer, int num_words)
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path[1] = TAP_DRCAPTURE;
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path[2] = TAP_DRSHIFT;
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fields[0].tap = xscale->jtag_info.tap;
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fields[0].tap = target->tap;
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fields[0].num_bits = 3;
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fields[0].out_value = NULL;
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fields[0].in_value = NULL;
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fields[0].check_value = &field0_check_value;
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fields[0].check_mask = &field0_check_mask;
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fields[1].tap = xscale->jtag_info.tap;
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fields[1].tap = target->tap;
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fields[1].num_bits = 32;
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fields[1].out_value = NULL;
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fields[1].check_value = NULL;
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fields[1].check_mask = NULL;
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fields[2].tap = xscale->jtag_info.tap;
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fields[2].tap = target->tap;
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fields[2].num_bits = 1;
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fields[2].out_value = NULL;
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fields[2].in_value = NULL;
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@ -309,7 +305,7 @@ static int xscale_receive(target_t *target, uint32_t *buffer, int num_words)
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fields[2].check_mask = &field2_check_mask;
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jtag_set_end_state(TAP_IDLE);
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xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
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xscale_jtag_set_instr(target->tap, XSCALE_DBGTX);
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jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
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/* repeat until all words have been collected */
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@ -394,7 +390,7 @@ static int xscale_read_tx(target_t *target, int consume)
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jtag_set_end_state(TAP_IDLE);
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xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
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xscale_jtag_set_instr(target->tap, XSCALE_DBGTX);
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path[0] = TAP_DRSELECT;
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path[1] = TAP_DRCAPTURE;
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@ -407,17 +403,17 @@ static int xscale_read_tx(target_t *target, int consume)
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noconsume_path[4] = TAP_DREXIT2;
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noconsume_path[5] = TAP_DRSHIFT;
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fields[0].tap = xscale->jtag_info.tap;
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fields[0].tap = target->tap;
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fields[0].num_bits = 3;
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fields[0].out_value = NULL;
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fields[0].in_value = &field0_in;
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fields[1].tap = xscale->jtag_info.tap;
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fields[1].tap = target->tap;
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fields[1].num_bits = 32;
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fields[1].out_value = NULL;
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fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
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fields[2].tap = xscale->jtag_info.tap;
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fields[2].tap = target->tap;
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fields[2].num_bits = 1;
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fields[2].out_value = NULL;
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uint8_t tmp;
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@ -496,19 +492,19 @@ static int xscale_write_rx(target_t *target)
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jtag_set_end_state(TAP_IDLE);
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xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx);
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xscale_jtag_set_instr(target->tap, XSCALE_DBGRX);
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fields[0].tap = xscale->jtag_info.tap;
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fields[0].tap = target->tap;
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fields[0].num_bits = 3;
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fields[0].out_value = &field0_out;
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fields[0].in_value = &field0_in;
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fields[1].tap = xscale->jtag_info.tap;
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fields[1].tap = target->tap;
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fields[1].num_bits = 32;
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fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
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fields[1].in_value = NULL;
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fields[2].tap = xscale->jtag_info.tap;
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fields[2].tap = target->tap;
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fields[2].num_bits = 1;
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fields[2].out_value = &field2;
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uint8_t tmp;
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@ -567,18 +563,14 @@ static int xscale_write_rx(target_t *target)
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/* send count elements of size byte to the debug handler */
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static int xscale_send(target_t *target, uint8_t *buffer, int count, int size)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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xscale_common_t *xscale = armv4_5->arch_info;
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uint32_t t[3];
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int bits[3];
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int retval;
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int done_count = 0;
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jtag_set_end_state(TAP_IDLE);
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xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx);
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xscale_jtag_set_instr(target->tap, XSCALE_DBGRX);
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bits[0]=3;
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t[0]=0;
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@ -615,7 +607,7 @@ static int xscale_send(target_t *target, uint8_t *buffer, int count, int size)
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LOG_ERROR("BUG: size neither 4, 2 nor 1");
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exit(-1);
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}
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jtag_add_dr_out(xscale->jtag_info.tap,
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jtag_add_dr_out(target->tap,
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3,
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bits,
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t,
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@ -663,23 +655,23 @@ static int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
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xscale->external_debug_break = ext_dbg_brk;
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jtag_set_end_state(TAP_IDLE);
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xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
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xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR);
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buf_set_u32(&field0, 1, 1, xscale->hold_rst);
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buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
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fields[0].tap = xscale->jtag_info.tap;
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fields[0].tap = target->tap;
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fields[0].num_bits = 3;
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fields[0].out_value = &field0;
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uint8_t tmp;
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fields[0].in_value = &tmp;
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fields[1].tap = xscale->jtag_info.tap;
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fields[1].tap = target->tap;
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fields[1].num_bits = 32;
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fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
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fields[1].in_value = NULL;
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fields[2].tap = xscale->jtag_info.tap;
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fields[2].tap = target->tap;
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fields[2].num_bits = 1;
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fields[2].out_value = &field2;
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uint8_t tmp2;
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@ -716,19 +708,16 @@ static unsigned int parity (unsigned int v)
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static int xscale_load_ic(target_t *target, uint32_t va, uint32_t buffer[8])
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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xscale_common_t *xscale = armv4_5->arch_info;
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uint8_t packet[4];
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uint8_t cmd;
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int word;
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scan_field_t fields[2];
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LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
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/* LDIC into IR */
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jtag_set_end_state(TAP_IDLE);
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xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic);
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xscale_jtag_set_instr(target->tap, XSCALE_LDIC);
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/* CMD is b011 to load a cacheline into the Mini ICache.
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* Loading into the main ICache is deprecated, and unused.
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@ -739,12 +728,12 @@ static int xscale_load_ic(target_t *target, uint32_t va, uint32_t buffer[8])
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/* virtual address of desired cache line */
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buf_set_u32(packet, 0, 27, va >> 5);
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fields[0].tap = xscale->jtag_info.tap;
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fields[0].tap = target->tap;
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fields[0].num_bits = 6;
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fields[0].out_value = &cmd;
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fields[0].in_value = NULL;
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fields[1].tap = xscale->jtag_info.tap;
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fields[1].tap = target->tap;
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fields[1].num_bits = 27;
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fields[1].out_value = packet;
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fields[1].in_value = NULL;
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@ -774,15 +763,12 @@ static int xscale_load_ic(target_t *target, uint32_t va, uint32_t buffer[8])
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static int xscale_invalidate_ic_line(target_t *target, uint32_t va)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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xscale_common_t *xscale = armv4_5->arch_info;
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uint8_t packet[4];
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uint8_t cmd;
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scan_field_t fields[2];
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jtag_set_end_state(TAP_IDLE);
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xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
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xscale_jtag_set_instr(target->tap, XSCALE_LDIC);
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/* CMD for invalidate IC line b000, bits [6:4] b000 */
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buf_set_u32(&cmd, 0, 6, 0x0);
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@ -790,12 +776,12 @@ static int xscale_invalidate_ic_line(target_t *target, uint32_t va)
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/* virtual address of desired cache line */
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buf_set_u32(packet, 0, 27, va >> 5);
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fields[0].tap = xscale->jtag_info.tap;
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fields[0].tap = target->tap;
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fields[0].num_bits = 6;
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fields[0].out_value = &cmd;
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fields[0].in_value = NULL;
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fields[1].tap = xscale->jtag_info.tap;
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fields[1].tap = target->tap;
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fields[1].num_bits = 27;
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fields[1].out_value = packet;
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fields[1].in_value = NULL;
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@ -1539,7 +1525,7 @@ static int xscale_assert_reset(target_t *target)
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* end up in T-L-R, which would reset JTAG
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*/
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jtag_set_end_state(TAP_IDLE);
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xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
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xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR);
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/* set Hold reset, Halt mode and Trap Reset */
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buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
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@ -1547,7 +1533,7 @@ static int xscale_assert_reset(target_t *target)
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xscale_write_dcsr(target, 1, 0);
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/* select BYPASS, because having DCSR selected caused problems on the PXA27x */
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xscale_jtag_set_instr(xscale->jtag_info.tap, 0x7f);
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xscale_jtag_set_instr(target->tap, 0x7f);
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jtag_execute_queue();
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/* assert reset */
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@ -2948,6 +2934,7 @@ static void xscale_build_reg_cache(target_t *target)
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static int xscale_init_target(struct command_context_s *cmd_ctx,
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struct target_s *target)
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{
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xscale_build_reg_cache(target);
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return ERROR_OK;
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}
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@ -2970,29 +2957,28 @@ static int xscale_init_arch_info(target_t *target,
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xscale->arch_info = NULL;
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xscale->common_magic = XSCALE_COMMON_MAGIC;
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/* remember the variant (PXA25x, PXA27x, IXP42x, ...) */
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xscale->variant = strdup(variant);
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/* we don't really *need* variant info ... */
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if (variant) {
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int ir_length = 0;
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/* prepare JTAG information for the new target */
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xscale->jtag_info.tap = tap;
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if (strcmp(variant, "pxa250") == 0
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|| strcmp(variant, "pxa255") == 0
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|| strcmp(variant, "pxa26x") == 0)
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ir_length = 5;
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else if (strcmp(variant, "pxa27x") == 0
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|| strcmp(variant, "ixp42x") == 0
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|| strcmp(variant, "ixp45x") == 0
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|| strcmp(variant, "ixp46x") == 0)
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ir_length = 7;
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else
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LOG_WARNING("%s: unrecognized variant %s",
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tap->dotted_name, variant);
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xscale->jtag_info.dbgrx = 0x02;
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xscale->jtag_info.dbgtx = 0x10;
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xscale->jtag_info.dcsr = 0x09;
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xscale->jtag_info.ldic = 0x07;
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if ((strcmp(xscale->variant, "pxa250") == 0) ||
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(strcmp(xscale->variant, "pxa255") == 0) ||
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(strcmp(xscale->variant, "pxa26x") == 0))
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{
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xscale->jtag_info.ir_length = 5;
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if (ir_length && ir_length != tap->ir_length) {
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LOG_WARNING("%s: IR length for %s is %d; fixing",
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tap->dotted_name, variant, ir_length);
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tap->ir_length = ir_length;
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}
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else if ((strcmp(xscale->variant, "pxa27x") == 0) ||
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(strcmp(xscale->variant, "ixp42x") == 0) ||
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(strcmp(xscale->variant, "ixp45x") == 0) ||
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(strcmp(xscale->variant, "ixp46x") == 0))
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{
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xscale->jtag_info.ir_length = 7;
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}
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/* the debug handler isn't installed (and thus not running) at this time */
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@ -3066,15 +3052,16 @@ static int xscale_init_arch_info(target_t *target,
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return ERROR_OK;
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}
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/* target xscale <endianess> <startup_mode> <chain_pos> <variant> */
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static int xscale_target_create(struct target_s *target, Jim_Interp *interp)
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{
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xscale_common_t *xscale = calloc(1,sizeof(xscale_common_t));
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xscale_common_t *xscale;
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xscale_init_arch_info(target, xscale, target->tap, target->variant);
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xscale_build_reg_cache(target);
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xscale = calloc(1, sizeof(*xscale));
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if (!xscale)
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return ERROR_FAIL;
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return ERROR_OK;
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return xscale_init_arch_info(target, xscale, target->tap,
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target->variant);
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}
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static int
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@ -29,18 +29,13 @@
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#define XSCALE_COMMON_MAGIC 0x58534341
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typedef struct xscale_jtag_s
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{
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/* position in JTAG scan chain */
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jtag_tap_t *tap;
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/* IR length and instructions */
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int ir_length;
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uint32_t dbgrx;
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uint32_t dbgtx;
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uint32_t ldic;
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uint32_t dcsr;
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} xscale_jtag_t;
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/* These four JTAG instructions are architecturally defined.
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* Lengths are core-specific; originally 5 bits, later 7.
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*/
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#define XSCALE_DBGRX 0x02
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#define XSCALE_DBGTX 0x10
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#define XSCALE_LDIC 0x07
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#define XSCALE_SELDCSR 0x09
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enum xscale_debug_reason
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{
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@ -90,11 +85,6 @@ typedef struct xscale_common_s
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/* XScale registers (CP15, DBG) */
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reg_cache_t *reg_cache;
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/* pxa250, pxa255, pxa27x, ixp42x, ... */
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char *variant;
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xscale_jtag_t jtag_info;
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/* current state of the debug handler */
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int handler_installed;
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int handler_running;
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Reference in New Issue