parent
4e2e730abe
commit
9f4cac5a38
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@ -706,7 +706,7 @@ static int init_target(struct command_context *cmd_ctx,
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LOG_DEBUG("init");
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riscv_info_t *generic_info = (riscv_info_t *) target->arch_info;
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riscv_info_init(generic_info);
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riscv_info_init(target, generic_info);
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generic_info->get_register = &riscv013_get_register;
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generic_info->set_register = &riscv013_set_register;
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generic_info->select_current_hart = &riscv013_select_current_hart;
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@ -872,11 +872,12 @@ struct target_type riscv_target =
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/*** RISC-V Interface ***/
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void riscv_info_init(riscv_info_t *r)
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void riscv_info_init(struct target *target, riscv_info_t *r)
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{
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memset(r, 0, sizeof(*r));
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r->dtm_version = 1;
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r->registers_initialized = false;
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r->current_hartid = target->coreid;
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for (size_t h = 0; h < RISCV_MAX_HARTS; ++h) {
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r->xlen[h] = -1;
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@ -1068,10 +1069,7 @@ void riscv_invalidate_register_cache(struct target *target)
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int riscv_current_hartid(const struct target *target)
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{
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RISCV_INFO(r);
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if (riscv_rtos_enabled(target))
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return r->current_hartid;
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else
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return target->coreid;
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return r->current_hartid;
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}
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void riscv_set_all_rtos_harts(struct target *target)
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@ -134,7 +134,7 @@ int riscv_openocd_deassert_reset(struct target *target);
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/*** RISC-V Interface ***/
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/* Initializes the shared RISC-V structure. */
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void riscv_info_init(riscv_info_t *r);
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void riscv_info_init(struct target *target, riscv_info_t *r);
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/* Run control, possibly for multiple harts. The _all_harts versions resume
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* all the enabled harts, which when running in RTOS mode is all the harts on
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