Paulius Zaleckas <paulius.zaleckas@gmail.com>:
This is minimal patch to support FA526 ARMv4 compatible core. Since it is very similar to ARM920T I tried to reuse as much code as possible. CPU and board configs will follow soon. git-svn-id: svn://svn.berlios.de/openocd/trunk@2292 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
zwelch
parent
13e592f9f6
commit
9eb3181cc8
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@ -2572,6 +2572,7 @@ SRST, to avoid a issue with clearing the debug registers.
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This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
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This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
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be detected and the normal reset behaviour used.
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be detected and the normal reset behaviour used.
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@end itemize
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@end itemize
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@item @code{fa526} -- resembles arm920 (w/o Thumb)
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@item @code{feroceon} -- resembles arm926
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@item @code{feroceon} -- resembles arm926
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@item @code{mips_m4k} -- a MIPS core. This supports one variant:
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@item @code{mips_m4k} -- a MIPS core. This supports one variant:
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@itemize @minus
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@itemize @minus
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@ -31,6 +31,7 @@ libtarget_la_SOURCES = \
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arm_disassembler.c \
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arm_disassembler.c \
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arm966e.c \
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arm966e.c \
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arm926ejs.c \
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arm926ejs.c \
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fa526.c \
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feroceon.c \
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feroceon.c \
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etb.c \
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etb.c \
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xscale.c \
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xscale.c \
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@ -31,8 +31,6 @@
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#endif
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#endif
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/* cli handling */
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/* cli handling */
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int arm920t_register_commands(struct command_context_s *cmd_ctx);
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int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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int arm920t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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int arm920t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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@ -47,10 +45,6 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
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int arm920t_target_create(struct target_s *target, Jim_Interp *interp);
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int arm920t_target_create(struct target_s *target, Jim_Interp *interp);
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int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
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int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
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int arm920t_quit(void);
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int arm920t_quit(void);
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int arm920t_arch_state(struct target_s *target);
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int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
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int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
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int arm920t_soft_reset_halt(struct target_s *target);
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#define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
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#define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
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@ -51,4 +51,15 @@ typedef struct arm920t_tlb_entry_s
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uint32_t ram2;
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uint32_t ram2;
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} arm920t_tlb_entry_t;
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} arm920t_tlb_entry_t;
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int arm920t_arch_state(struct target_s *target);
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int arm920t_soft_reset_halt(struct target_s *target);
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int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
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int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
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void arm920t_post_debug_entry(target_t *target);
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void arm920t_pre_restore_context(target_t *target);
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uint32_t arm920t_get_ttb(target_t *target);
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void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache);
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void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache);
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int arm920t_register_commands(struct command_context_s *cmd_ctx);
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#endif /* ARM920T_H */
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#endif /* ARM920T_H */
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@ -63,4 +63,17 @@ extern int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, in
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extern void arm9tdmi_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16]);
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extern void arm9tdmi_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16]);
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extern void arm9tdmi_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16]);
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extern void arm9tdmi_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16]);
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extern int arm9tdmi_examine_debug_reason(target_t *target);
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extern void arm9tdmi_load_word_regs(target_t *target, uint32_t mask);
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extern void arm9tdmi_load_hword_reg(target_t *target, int num);
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extern void arm9tdmi_load_byte_reg(target_t *target, int num);
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extern void arm9tdmi_store_word_regs(target_t *target, uint32_t mask);
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extern void arm9tdmi_store_hword_reg(target_t *target, int num);
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extern void arm9tdmi_store_byte_reg(target_t *target, int num);
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extern void arm9tdmi_branch_resume(target_t *target);
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extern void arm9tdmi_enable_single_step(target_t *target, uint32_t next_pc);
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extern void arm9tdmi_disable_single_step(target_t *target);
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#endif /* ARM9TDMI_H */
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#endif /* ARM9TDMI_H */
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@ -0,0 +1,430 @@
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/***************************************************************************
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* Copyright (C) 2009 by Paulius Zaleckas *
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* paulius.zaleckas@gmail.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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/*
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* FA526 is very similar to ARM920T with following differences:
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*
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* - execution pipeline is 6 steps
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* - Unified TLB
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* - has Branch Target Buffer
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* - does not support reading of I/D cache contents
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "arm920t.h"
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#include "target_type.h"
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int fa526_target_create(struct target_s *target, Jim_Interp *interp);
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int fa526_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
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int fa526_quit(void);
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target_type_t fa526_target =
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{
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.name = "fa526",
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.poll = arm7_9_poll,
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.arch_state = arm920t_arch_state,
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.target_request_data = arm7_9_target_request_data,
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.halt = arm7_9_halt,
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.resume = arm7_9_resume,
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.step = arm7_9_step,
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.assert_reset = arm7_9_assert_reset,
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.deassert_reset = arm7_9_deassert_reset,
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.soft_reset_halt = arm920t_soft_reset_halt,
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.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
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.read_memory = arm920t_read_memory,
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.write_memory = arm920t_write_memory,
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.bulk_write_memory = arm7_9_bulk_write_memory,
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.checksum_memory = arm7_9_checksum_memory,
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.blank_check_memory = arm7_9_blank_check_memory,
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.run_algorithm = armv4_5_run_algorithm,
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.add_breakpoint = arm7_9_add_breakpoint,
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.remove_breakpoint = arm7_9_remove_breakpoint,
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.add_watchpoint = arm7_9_add_watchpoint,
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.remove_watchpoint = arm7_9_remove_watchpoint,
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.register_commands = arm920t_register_commands,
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.target_create = fa526_target_create,
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.init_target = fa526_init_target,
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.examine = arm9tdmi_examine,
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.quit = fa526_quit
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};
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void fa526_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
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{
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LOG_ERROR("%s: there is no Thumb state on FA526", __func__);
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}
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void fa526_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16])
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{
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int i;
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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arm_jtag_t *jtag_info = &arm7_9->jtag_info;
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/* STMIA r0-15, [r0] at debug speed
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* register values will start to appear on 4th DCLK
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*/
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arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
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/* fetch NOP, STM in DECODE stage */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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/* fetch NOP, STM in SHIFT stage */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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/* fetch NOP, STM in EXECUTE stage (1st cycle) */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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for (i = 0; i <= 15; i++)
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{
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if (mask & (1 << i))
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/* nothing fetched, STM in MEMORY (i'th cycle) */
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arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
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}
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}
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void fa526_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size)
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{
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int i;
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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arm_jtag_t *jtag_info = &arm7_9->jtag_info;
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int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
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uint32_t *buf_u32 = buffer;
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uint16_t *buf_u16 = buffer;
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uint8_t *buf_u8 = buffer;
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/* STMIA r0-15, [r0] at debug speed
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* register values will start to appear on 4th DCLK
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*/
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arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
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/* fetch NOP, STM in DECODE stage */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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/* fetch NOP, STM in SHIFT stage */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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/* fetch NOP, STM in EXECUTE stage (1st cycle) */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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for (i = 0; i <= 15; i++)
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{
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if (mask & (1 << i))
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/* nothing fetched, STM in MEMORY (i'th cycle) */
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switch (size)
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{
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case 4:
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arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
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break;
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case 2:
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arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
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break;
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case 1:
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arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
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break;
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}
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}
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}
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void fa526_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
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{
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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arm_jtag_t *jtag_info = &arm7_9->jtag_info;
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/* MRS r0, cpsr */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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/* STR r0, [r15] */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
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/* fetch NOP, STR in DECODE stage */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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/* fetch NOP, STR in SHIFT stage */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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/* fetch NOP, STR in EXECUTE stage (1st cycle) */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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/* nothing fetched, STR in MEMORY */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
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}
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void fa526_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
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{
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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arm_jtag_t *jtag_info = &arm7_9->jtag_info;
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LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
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/* MSR1 fetched */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
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/* MSR2 fetched, MSR1 in DECODE */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
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/* MSR3 fetched, MSR1 in SHIFT, MSR2 in DECODE */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
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/* MSR4 fetched, MSR1 in EXECUTE (1), MSR2 in SHIFT, MSR3 in DECODE */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
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/* nothing fetched, MSR1 in EXECUTE (2) */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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/* nothing fetched, MSR1 in EXECUTE (3) */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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/* nothing fetched, MSR2 in EXECUTE (1), MSR3 in SHIFT, MSR4 in DECODE */
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||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
/* nothing fetched, MSR2 in EXECUTE (2) */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
/* nothing fetched, MSR2 in EXECUTE (3) */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
/* NOP fetched, MSR3 in EXECUTE (1), MSR4 in SHIFT */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
/* nothing fetched, MSR3 in EXECUTE (2) */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
/* nothing fetched, MSR3 in EXECUTE (3) */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
/* NOP fetched, MSR4 in EXECUTE (1) */
|
||||||
|
/* last MSR writes flags, which takes only one cycle */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
void fa526_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr)
|
||||||
|
{
|
||||||
|
/* get pointers to arch-specific information */
|
||||||
|
armv4_5_common_t *armv4_5 = target->arch_info;
|
||||||
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
|
||||||
|
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
|
||||||
|
|
||||||
|
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
|
||||||
|
|
||||||
|
/* MSR fetched */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
|
||||||
|
/* NOP fetched, MSR in DECODE */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
/* NOP fetched, MSR in SHIFT */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
/* NOP fetched, MSR in EXECUTE (1) */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
|
||||||
|
/* rot == 4 writes flags, which takes only one cycle */
|
||||||
|
if (rot != 4)
|
||||||
|
{
|
||||||
|
/* nothing fetched, MSR in EXECUTE (2) */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
/* nothing fetched, MSR in EXECUTE (3) */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void fa526_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16])
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
/* get pointers to arch-specific information */
|
||||||
|
armv4_5_common_t *armv4_5 = target->arch_info;
|
||||||
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
|
||||||
|
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
|
||||||
|
|
||||||
|
/* LDMIA r0-15, [r0] at debug speed
|
||||||
|
* register values will start to appear on 4th DCLK
|
||||||
|
*/
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
|
||||||
|
|
||||||
|
/* fetch NOP, LDM in DECODE stage */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
/* fetch NOP, LDM in SHIFT stage */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
/* fetch NOP, LDM in EXECUTE stage (1st cycle) */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
|
||||||
|
for (i = 0; i <= 15; i++)
|
||||||
|
{
|
||||||
|
if (mask & (1 << i))
|
||||||
|
/* nothing fetched, LDM still in EXECUTE (1+i cycle) */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
|
||||||
|
}
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
void fa526_write_pc(target_t *target, uint32_t pc)
|
||||||
|
{
|
||||||
|
/* get pointers to arch-specific information */
|
||||||
|
armv4_5_common_t *armv4_5 = target->arch_info;
|
||||||
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
|
||||||
|
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
|
||||||
|
|
||||||
|
/* LDMIA r0-15, [r0] at debug speed
|
||||||
|
* register values will start to appear on 4th DCLK
|
||||||
|
*/
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
|
||||||
|
|
||||||
|
/* fetch NOP, LDM in DECODE stage */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
/* fetch NOP, LDM in SHIFT stage */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
/* fetch NOP, LDM in EXECUTE stage (1st cycle) */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
/* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
|
||||||
|
/* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
/* fetch NOP, LDM in EXECUTE stage (4th cycle) */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
/* fetch NOP, LDM in EXECUTE stage (5th cycle) */
|
||||||
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
void fa526_branch_resume_thumb(target_t *target)
|
||||||
|
{
|
||||||
|
LOG_ERROR("%s: there is no Thumb state on FA526", __func__);
|
||||||
|
}
|
||||||
|
|
||||||
|
int fa526_init_arch_info_2(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap)
|
||||||
|
{
|
||||||
|
armv4_5_common_t *armv4_5;
|
||||||
|
arm7_9_common_t *arm7_9;
|
||||||
|
|
||||||
|
arm7_9 = &arm9tdmi->arm7_9_common;
|
||||||
|
armv4_5 = &arm7_9->armv4_5_common;
|
||||||
|
|
||||||
|
/* prepare JTAG information for the new target */
|
||||||
|
arm7_9->jtag_info.tap = tap;
|
||||||
|
arm7_9->jtag_info.scann_size = 5;
|
||||||
|
|
||||||
|
/* register arch-specific functions */
|
||||||
|
arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
|
||||||
|
arm7_9->change_to_arm = fa526_change_to_arm;
|
||||||
|
arm7_9->read_core_regs = fa526_read_core_regs;
|
||||||
|
arm7_9->read_core_regs_target_buffer = fa526_read_core_regs_target_buffer;
|
||||||
|
arm7_9->read_xpsr = fa526_read_xpsr;
|
||||||
|
|
||||||
|
arm7_9->write_xpsr = fa526_write_xpsr;
|
||||||
|
arm7_9->write_xpsr_im8 = fa526_write_xpsr_im8;
|
||||||
|
arm7_9->write_core_regs = fa526_write_core_regs;
|
||||||
|
|
||||||
|
arm7_9->load_word_regs = arm9tdmi_load_word_regs;
|
||||||
|
arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
|
||||||
|
arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
|
||||||
|
|
||||||
|
arm7_9->store_word_regs = arm9tdmi_store_word_regs;
|
||||||
|
arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
|
||||||
|
arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
|
||||||
|
|
||||||
|
arm7_9->write_pc = fa526_write_pc;
|
||||||
|
arm7_9->branch_resume = arm9tdmi_branch_resume;
|
||||||
|
arm7_9->branch_resume_thumb = fa526_branch_resume_thumb;
|
||||||
|
|
||||||
|
arm7_9->enable_single_step = arm9tdmi_enable_single_step;
|
||||||
|
arm7_9->disable_single_step = arm9tdmi_disable_single_step;
|
||||||
|
|
||||||
|
arm7_9->pre_debug_entry = NULL;
|
||||||
|
arm7_9->post_debug_entry = NULL;
|
||||||
|
|
||||||
|
arm7_9->pre_restore_context = NULL;
|
||||||
|
arm7_9->post_restore_context = NULL;
|
||||||
|
|
||||||
|
/* initialize arch-specific breakpoint handling */
|
||||||
|
arm7_9->arm_bkpt = 0xdeeedeee;
|
||||||
|
arm7_9->thumb_bkpt = 0xdeee;
|
||||||
|
|
||||||
|
arm7_9->dbgreq_adjust_pc = 3;
|
||||||
|
arm7_9->arch_info = arm9tdmi;
|
||||||
|
|
||||||
|
arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
|
||||||
|
arm9tdmi->arch_info = NULL;
|
||||||
|
|
||||||
|
arm7_9_init_arch_info(target, arm7_9);
|
||||||
|
|
||||||
|
/* override use of DBGRQ, this is safe on ARM9TDMI */
|
||||||
|
arm7_9->use_dbgrq = 1;
|
||||||
|
|
||||||
|
/* all ARM9s have the vector catch register */
|
||||||
|
arm7_9->has_vector_catch = 1;
|
||||||
|
|
||||||
|
return ERROR_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
int fa526_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap_t *tap)
|
||||||
|
{
|
||||||
|
arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
|
||||||
|
arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
|
||||||
|
|
||||||
|
/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
|
||||||
|
*/
|
||||||
|
fa526_init_arch_info_2(target, arm9tdmi, tap);
|
||||||
|
|
||||||
|
arm9tdmi->arch_info = arm920t;
|
||||||
|
arm920t->common_magic = ARM920T_COMMON_MAGIC;
|
||||||
|
|
||||||
|
arm7_9->post_debug_entry = arm920t_post_debug_entry;
|
||||||
|
arm7_9->pre_restore_context = arm920t_pre_restore_context;
|
||||||
|
|
||||||
|
arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
|
||||||
|
arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
|
||||||
|
arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
|
||||||
|
arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
|
||||||
|
arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
|
||||||
|
arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
|
||||||
|
arm920t->armv4_5_mmu.has_tiny_pages = 1;
|
||||||
|
arm920t->armv4_5_mmu.mmu_enabled = 0;
|
||||||
|
|
||||||
|
/* disabling linefills leads to lockups, so keep them enabled for now
|
||||||
|
* this doesn't affect correctness, but might affect timing issues, if
|
||||||
|
* important data is evicted from the cache during the debug session
|
||||||
|
* */
|
||||||
|
arm920t->preserve_cache = 0;
|
||||||
|
|
||||||
|
/* override hw single-step capability from ARM9TDMI */
|
||||||
|
arm7_9->has_single_step = 1;
|
||||||
|
|
||||||
|
return ERROR_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
int fa526_target_create(struct target_s *target, Jim_Interp *interp)
|
||||||
|
{
|
||||||
|
arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t));
|
||||||
|
|
||||||
|
fa526_init_arch_info(target, arm920t, target->tap);
|
||||||
|
|
||||||
|
return ERROR_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
int fa526_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
|
||||||
|
{
|
||||||
|
arm9tdmi_init_target(cmd_ctx, target);
|
||||||
|
return ERROR_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
int fa526_quit(void)
|
||||||
|
{
|
||||||
|
return ERROR_OK;
|
||||||
|
}
|
||||||
|
|
@ -82,6 +82,7 @@ extern target_type_t arm9tdmi_target;
|
||||||
extern target_type_t arm920t_target;
|
extern target_type_t arm920t_target;
|
||||||
extern target_type_t arm966e_target;
|
extern target_type_t arm966e_target;
|
||||||
extern target_type_t arm926ejs_target;
|
extern target_type_t arm926ejs_target;
|
||||||
|
extern target_type_t fa526_target;
|
||||||
extern target_type_t feroceon_target;
|
extern target_type_t feroceon_target;
|
||||||
extern target_type_t xscale_target;
|
extern target_type_t xscale_target;
|
||||||
extern target_type_t cortexm3_target;
|
extern target_type_t cortexm3_target;
|
||||||
|
|
@ -98,6 +99,7 @@ target_type_t *target_types[] =
|
||||||
&arm720t_target,
|
&arm720t_target,
|
||||||
&arm966e_target,
|
&arm966e_target,
|
||||||
&arm926ejs_target,
|
&arm926ejs_target,
|
||||||
|
&fa526_target,
|
||||||
&feroceon_target,
|
&feroceon_target,
|
||||||
&xscale_target,
|
&xscale_target,
|
||||||
&cortexm3_target,
|
&cortexm3_target,
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue