partial support for 568013 and 568037, target integration.
Rodrigo L. Rosa
Øyvind Harboe
parent
6349a47ebc
commit
9d4aec6bda
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@ -33,7 +33,8 @@ libtarget_la_SOURCES = \
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$(MIPS32_SRC) \
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avrt.c \
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dsp563xx.c \
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dsp563xx_once.c
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dsp563xx_once.c \
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dsp5680xx.c
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TARGET_CORE_SRC = \
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algorithm.c \
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@ -134,6 +135,7 @@ noinst_HEADERS = \
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avrt.h \
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dsp563xx.h \
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dsp563xx_once.h \
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dsp5680xx.h \
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breakpoints.h \
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cortex_m3.h \
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cortex_a.h \
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,216 @@
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/***************************************************************************
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* Copyright (C) 2011 by Rodrigo L. Rosa *
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* rodrigorosa.LG@gmail.com *
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* *
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* Based on dsp563xx_once.h written by Mathias Kuester *
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* mkdorg@users.sourceforge.net *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef DSP5680XX_H
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#define DSP5680XX_H
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#include <jtag/jtag.h>
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#define S_FILE_DATA_OFFSET 0x200000
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//----------------------------------------------------------------
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// JTAG
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//----------------------------------------------------------------
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#define DSP5680XX_JTAG_CORE_TAP_IRLEN 4
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#define DSP5680XX_JTAG_MASTER_TAP_IRLEN 8
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#define JTAG_STATUS_MASK 0x03
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#define JTAG_STATUS_NORMAL 0x01
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#define JTAG_STATUS_STOPWAIT 0x05
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#define JTAG_STATUS_BUSY 0x09
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#define JTAG_STATUS_DEBUG 0x0D
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#define JTAG_STATUS_DEAD 0x0f
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#define JTAG_INSTR_EXTEST 0x0
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#define JTAG_INSTR_SAMPLE_PRELOAD 0x1
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#define JTAG_INSTR_IDCODE 0x2
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#define JTAG_INSTR_EXTEST_PULLUP 0x3
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#define JTAG_INSTR_HIGHZ 0x4
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#define JTAG_INSTR_CLAMP 0x5
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#define JTAG_INSTR_ENABLE_ONCE 0x6
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#define JTAG_INSTR_DEBUG_REQUEST 0x7
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#define JTAG_INSTR_BYPASS 0xF
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// Master TAP instructions from MC56F8000RM.pdf
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//----------------------------------------------------------------
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#define MASTER_TAP_CMD_BYPASS 0xFF
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#define MASTER_TAP_CMD_IDCODE 0x02
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#define MASTER_TAP_CMD_TLM_SEL 0x05
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#define MASTER_TAP_CMD_FLASH_ERASE 0x08
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// EOnCE control register info
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//----------------------------------------------------------------
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#define DSP5680XX_ONCE_OCR_EX (1<<5)
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/* EX Bit Definition
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0 Remain in the Debug Processing State
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1 Leave the Debug Processing State */
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#define DSP5680XX_ONCE_OCR_GO (1<<6)
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/* GO Bit Definition
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0 Inactive—No Action Taken
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1 Execute Controller Instruction */
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#define DSP5680XX_ONCE_OCR_RW (1<<7)
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/* RW Bit Definition
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0 Write To the Register Specified by the RS[4:0] Bits
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1 ReadFrom the Register Specified by the RS[4:0] Bits */
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// EOnCE Status Register
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//----------------------------------------------------------------
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#define DSP5680XX_ONCE_OSCR_OS1 (1<<5)
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#define DSP5680XX_ONCE_OSCR_OS0 (1<<4)
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// EOnCE Core Status - Describes the operating status of the core controller
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//----------------------------------------------------------------
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#define DSP5680XX_ONCE_OSCR_NORMAL_M (0)
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//00 - Normal - Controller Core Executing Instructions or in Reset
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#define DSP5680XX_ONCE_OSCR_STOPWAIT_M (DSP5680XX_ONCE_OSCR_OS0)
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//01 - Stop/Wait - Controller Core in Stop or Wait Mode
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#define DSP5680XX_ONCE_OSCR_BUSY_M (DSP5680XX_ONCE_OSCR_OS1)
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//10 - Busy - Controller is Performing External or Peripheral Access (Wait States)
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#define DSP5680XX_ONCE_OSCR_DEBUG_M (DSP5680XX_ONCE_OSCR_OS0|DSP5680XX_ONCE_OSCR_OS1)
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//11 - Debug - Controller Core Halted and in Debug Mode
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#define EONCE_STAT_MASK 0x30
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// Register Select Encoding (eonce_rev.1.0_0208081.pdf@14)
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//----------------------------------------------------------------
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#define DSP5680XX_ONCE_NOREG 0x00 /* No register selected */
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#define DSP5680XX_ONCE_OCR 0x01 /* OnCE Debug Control Register */
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#define DSP5680XX_ONCE_OCNTR 0x02 /* OnCE Breakpoint and Trace Counter */
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#define DSP5680XX_ONCE_OSR 0x03 /* EOnCE status register */
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#define DSP5680XX_ONCE_OBAR 0x04 /* OnCE Breakpoint Address Register */
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#define DSP5680XX_ONCE_OBASE 0x05 /* EOnCE Peripheral Base Address register */
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#define DSP5680XX_ONCE_OTXRXSR 0x06 /* EOnCE TXRX Status and Control Register (OTXRXSR) */
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#define DSP5680XX_ONCE_OTX 0x07 /* EOnCE Transmit register (OTX) */
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#define DSP5680XX_ONCE_OPDBR 0x08 /* EOnCE Program Data Bus Register (OPDBR) */
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#define DSP5680XX_ONCE_OTX1 0x09 /* EOnCE Upper Transmit register (OTX1) */
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#define DSP5680XX_ONCE_OPABFR 0x0A /* OnCE Program Address Register—Fetch cycle */
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#define DSP5680XX_ONCE_ORX 0x0B /* EOnCE Receive register (ORX) */
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#define DSP5680XX_ONCE_OCNTR_C 0x0C /* Clear OCNTR */
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#define DSP5680XX_ONCE_ORX1 0x0D /* EOnCE Upper Receive register (ORX1) */
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#define DSP5680XX_ONCE_OTBCR 0x0E /* EOnCE Trace Buffer Control Reg (OTBCR) */
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#define DSP5680XX_ONCE_OPABER 0x10 /* OnCE Program Address Register—Execute cycle */
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#define DSP5680XX_ONCE_OPFIFO 0x11 /* OnCE Program address FIFO */
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#define DSP5680XX_ONCE_OBAR1 0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */
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#define DSP5680XX_ONCE_OPABDR 0x13 /* OnCE Program Address Register—Decode cycle (OPABDR) */
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// HFM (flash module) Commands (ref:MC56F801xRM.pdf@159)
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//----------------------------------------------------------------
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#define HFM_ERASE_VERIFY 0x05
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#define HFM_CALCULATE_DATA_SIGNATURE 0x06
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#define HFM_WORD_PROGRAM 0x20
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#define HFM_PAGE_ERASE 0x40
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#define HFM_MASS_ERASE 0x41
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#define HFM_CALCULATE_IFR_BLOCK_SIGNATURE 0x66
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// Flashing (ref:MC56F801xRM.pdf@159)
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//----------------------------------------------------------------
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#define HFM_BASE_ADDR 0x0F400 // In x: mem. (write to S_FILE_DATA_OFFSET+HFM_BASE_ADDR to get data into x: mem.)
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// The following are register addresses, not memory addresses (though all registers are memory mapped)
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#define HFM_CLK_DIV 0x00 // r/w
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#define HFM_CNFG 0x01 // r/w
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#define HFM_SECHI 0x03 // r
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#define HFM_SECLO 0x04 // r
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#define HFM_PROT 0x10 // r/w
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#define HFM_PROTB 0x11 // r/w
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#define HFM_USTAT 0x13 // r/w
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#define HFM_CMD 0x14 // r/w
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#define HFM_DATA 0x18 // r
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#define HFM_OPT1 0x1B // r
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#define HFM_TSTSIG 0x1D // r
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#define HFM_EXEC_COMPLETE 0x40
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// User status register (USTAT) masks (MC56F80XXRM.pdf@6.7.5)
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#define HFM_USTAT_MASK_BLANK 0x4
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#define HFM_USTAT_MASK_PVIOL_ACCER 0x30
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#define HFM_CLK_DEFAULT 0x29
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#define HFM_FLASH_BASE_ADDR 0x0
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#define HFM_SIZE 0x8000 // This is not true for 56F8013, but it is necessary to get the byte/word addressing workaround to actually work.
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#define HFM_SIZE_REAL 0x2000
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#define HFM_SECTOR_SIZE 0x8000 // 512 bytes pages.
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#define HFM_SECTOR_COUNT 1
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#define HFM_LOCK_FLASH 0xE70A
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#define HFM_LOCK_ADDR_L 0x1FF7
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#define HFM_LOCK_ADDR_H 0x1FF8
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// Writing HFM_LOCK_FLASH to HFM_LOCK_ADDR_L and HFM_LOCK_ADDR_H will enable security on flash after the next reset.
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// Register Memory Map (eonce_rev.1.0_0208081.pdf@16)
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//----------------------------------------------------------------
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#define MC568013_EONCE_OBASE_ADDR 0xFF
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// The following are relative to EONCE_OBASE_ADDR (EONCE_OBASE_ADDR<<16 + ...)
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#define MC568013_EONCE_TX_RX_ADDR 0xFFFE //
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#define MC568013_EONCE_TX1_RX1_HIGH_ADDR 0xFFFF // Relative to EONCE_OBASE_ADDR
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#define MC568013_EONCE_OCR 0xFFA0 // Relative to EONCE_OBASE_ADDR
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// SIM addresses & commands (MC56F80xx.h from freescale)
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//----------------------------------------------------------------
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#define MC568013_SIM_BASE_ADDR 0xF140
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#define MC56803x_2x_SIM_BASE_ADDR 0xF100
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#define SIM_CMD_RESET 0x10
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//----------------------------------------------------------------
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struct dsp5680xx_common
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{
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//TODO
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};
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static inline struct dsp5680xx_common *target_to_dsp5680xx(struct target *target)
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{
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return target->arch_info;
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}
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struct context
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{
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uint32_t stored_pc;
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}context;
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int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, uint32_t count);
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int dsp5680xx_f_erase_check(struct target * target,uint8_t * erased);
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int dsp5680xx_f_erase(struct target * target, int first, int last);
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int dsp5680xx_f_protect_check(struct target * target, uint8_t * protected);
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int dsp5680xx_f_lock(struct target * target);
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int dsp5680xx_f_unlock(struct target * target);
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#endif // dsp5680xx.h
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@ -81,6 +81,7 @@ extern struct target_type arm11_target;
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extern struct target_type mips_m4k_target;
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extern struct target_type avr_target;
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extern struct target_type dsp563xx_target;
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extern struct target_type dsp5680xx_target;
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extern struct target_type testee_target;
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extern struct target_type avr32_ap7k_target;
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@ -103,6 +104,7 @@ static struct target_type *target_types[] =
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&mips_m4k_target,
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&avr_target,
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&dsp563xx_target,
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&dsp5680xx_target,
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&testee_target,
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&avr32_ap7k_target,
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NULL,
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@ -0,0 +1,73 @@
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# Script for freescale DSP568013
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME dsp568013
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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# this defaults to a big endian
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set _ENDIAN little
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# force an error till we get a good number
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set _CPUTAPID 0x01f2401d
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}
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#jtag speed
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adapter_khz 800
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reset_config srst_only
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#MASTER tap
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jtag newtap $_CHIPNAME chp -irlen 8 -ircapture 1 -irmask 0x03 -expected-id $_CPUTAPID
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#CORE tap
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x03 -disable -expected-id 0x02211004
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#target configuration - There is only 1 tap at a time, hence only 1 target is defined.
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME
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# Setup the interesting tap
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jtag configure $_CHIPNAME.chp -event setup "jtag tapenable $_TARGETNAME"
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#select CORE tap by modifying the TLM register.
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#to be used when MASTER tap is selected.
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jtag configure $_TARGETNAME -event tap-enable "
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irscan $_CHIPNAME.chp 0x05;
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drscan $_CHIPNAME.chp 4 0x02;
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jtag tapdisable $_CHIPNAME.chp;
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"
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#select MASTER tap by modifying the TLM register.
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#to be used when CORE tap is selected.
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jtag configure $_CHIPNAME.chp -event tap-enable "
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irscan $_TARGETNAME 0x08;
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drscan $_TARGETNAME 4 0x1;
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jtag tapdisable $_TARGETNAME;
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"
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#disables the master tap
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jtag configure $_TARGETNAME -event tap-disable "
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"
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#TODO FIND SMARTER WAY.
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jtag configure $_CHIPNAME.chp -event tap-disable "
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"
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#TODO FIND SMARTER WAY.
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#working area at base of ram
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$_TARGETNAME configure -work-area-virt 0
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#setup flash
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#set _FLASHNAME $_CHIPNAME.flash
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#flash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME
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@ -0,0 +1,73 @@
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# Script for freescale DSP568037
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME dsp568037
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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# this defaults to a big endian
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set _ENDIAN little
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# force an error till we get a good number
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set _CPUTAPID 0x01f2801d
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}
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#jtag speed
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adapter_khz 800
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reset_config srst_only
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#MASTER tap
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jtag newtap $_CHIPNAME chp -irlen 8 -ircapture 1 -irmask 0x03 -expected-id $_CPUTAPID
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#CORE tap
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x03 -disable -expected-id 0x02211004
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#target configuration - There is only 1 tap at a time, hence only 1 target is defined.
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME
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# Setup the interesting tap
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jtag configure $_CHIPNAME.chp -event setup "jtag tapenable $_TARGETNAME"
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#select CORE tap by modifying the TLM register.
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#to be used when MASTER tap is selected.
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jtag configure $_TARGETNAME -event tap-enable "
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irscan $_CHIPNAME.chp 0x05;
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drscan $_CHIPNAME.chp 4 0x02;
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jtag tapdisable $_CHIPNAME.chp;
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"
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#select MASTER tap by modifying the TLM register.
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#to be used when CORE tap is selected.
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jtag configure $_CHIPNAME.chp -event tap-enable "
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irscan $_TARGETNAME 0x08;
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drscan $_TARGETNAME 4 0x1;
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jtag tapdisable $_TARGETNAME;
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"
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#disables the master tap
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jtag configure $_TARGETNAME -event tap-disable "
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"
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#TODO FIND SMARTER WAY.
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jtag configure $_CHIPNAME.chp -event tap-disable "
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"
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#TODO FIND SMARTER WAY.
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#working area at base of ram
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$_TARGETNAME configure -work-area-virt 0
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#setup flash
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#set _FLASHNAME $_CHIPNAME.flash
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#flash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME
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