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Merge pull request #13 from sifive/disable_interrupts 

riscv: Globally disable interrupts when running algorithms.
__archive__
Tim Newsome 2017-01-26 10:45:13 -08:00 committed by GitHub
parent 193f630948 5d82a395f1
commit 9bab0782d3
1 changed files with 18 additions and 0 deletions
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18
src/target/riscv/riscv.c
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@ -2696,6 +2696,19 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
}
}
// Disable Interrupts before attempting to run the algorithm.
uint64_t current_mstatus;
uint8_t mstatus_bytes[8];
LOG_DEBUG("Disabling Interrupts");
register_get(&target->reg_cache->reg_list[REG_MSTATUS]);
current_mstatus = buf_get_u64(target->reg_cache->reg_list[REG_MSTATUS].value, 0, info->xlen);
uint64_t ie_mask = MSTATUS_MIE | MSTATUS_HIE | MSTATUS_SIE | MSTATUS_UIE;
buf_set_u64(mstatus_bytes, 0, info->xlen, set_field(current_mstatus, ie_mask, 0));
register_set(&target->reg_cache->reg_list[REG_MSTATUS], mstatus_bytes);
/// Run algorithm
LOG_DEBUG("resume at 0x%x", entry_point);
if (riscv_resume(target, 0, entry_point, 0, 0) != ERROR_OK) {
@ -2729,6 +2742,11 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
return ERROR_FAIL;
}
// Restore Interrupts
LOG_DEBUG("Restoring Interrupts");
buf_set_u64(mstatus_bytes, 0, info->xlen, current_mstatus);
register_set(&target->reg_cache->reg_list[REG_MSTATUS], mstatus_bytes);
/// Restore registers
uint8_t buf[8];
buf_set_u64(buf, 0, info->xlen, saved_pc);