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stm32.cfg can expect one of 4 id's. 

git-svn-id: svn://svn.berlios.de/openocd/trunk@1516 b42882b7-edfa-0310-969c-e2dbd0fdcd60
__archive__
oharboe 2009-04-23 14:03:42 +00:00
parent 90ff84a2dd
commit 9b7bd65883
2 changed files with 8 additions and 6 deletions
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4
doc/openocd.texi
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@ -1606,7 +1606,9 @@ bits long, during Capture-IR 0x42 is loaded into the IR, and bits
@itemize @bullet
@item @b{-expected-id NUMBER}
@* By default it is zero. If non-zero represents the
expected tap ID used when the JTAG chain is examined. See below.
expected tap ID used when the JTAG chain is examined. Repeat
the option as many times as required if multiple id's can be
expected. See below.
@item @b{-disable}
@item @b{-enable}
@* By default not specified the tap is enabled. Some chips have a

10
src/target/target/stm32.cfg
View File

@ -37,15 +37,15 @@ if { [info exists BSTAPID ] } {
# See STM Document RM0008
# Section 26.6.2
# Low density devices, Rev A
set _BSTAPID 0x06412041
set _BSTAPID1 0x06412041
# Medium density devices, Rev A
set _BSTAPID 0x06410041
set _BSTAPID2 0x06410041
# Medium density devices, Rev B and Rev Z
set _BSTAPID 0x16410041
set _BSTAPID3 0x16410041
# High density devices, Rev A
set _BSTAPID 0x06414041
set _BSTAPID4 0x06414041
}
jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 -expected-id $_BSTAPID4
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME