From 99f2f5a27291312f11ee9851631cd3b0c183bc4e Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Mon, 9 Apr 2018 11:26:31 -0700 Subject: [PATCH] Change #ifdef SIM_ON to be a run-time arg --- src/target/riscv/riscv-013.c | 104 +++++++++++++++++------------------ src/target/riscv/riscv.c | 13 +++-- src/target/riscv/riscv.h | 2 + 3 files changed, 63 insertions(+), 56 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 664c31c68..ba5a0743b 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -2816,7 +2816,7 @@ void riscv013_fill_dmi_nop_u64(struct target *target, char *buf) buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, 0); } -static int get_max_sbaccess(struct target *target) +static uint32_t get_max_sbaccess(struct target *target) { RISCV013_INFO(info); @@ -2854,7 +2854,7 @@ static int riscv013_test_sba_config_reg(struct target *target, int max_sbaccess = get_max_sbaccess(target); - if (max_sbaccess == ERROR_FAIL) { + if (max_sbaccess == -1) { LOG_ERROR("System Bus Access not supported in this config."); return ERROR_FAIL; } @@ -2869,7 +2869,7 @@ static int riscv013_test_sba_config_reg(struct target *target, sbcs = set_field(sbcs_orig, DMI_SBCS_SBAUTOINCREMENT, 0); dmi_write(target, DMI_SBCS, sbcs); - for (int sbaccess = 0; sbaccess <= max_sbaccess; sbaccess++) { + for (uint32_t sbaccess = 0; sbaccess <= (uint32_t)max_sbaccess; sbaccess++) { sbcs = set_field(sbcs, DMI_SBCS_SBACCESS, sbaccess); dmi_write(target, DMI_SBCS, sbcs); @@ -2897,7 +2897,7 @@ static int riscv013_test_sba_config_reg(struct target *target, sbcs = set_field(sbcs_orig, DMI_SBCS_SBAUTOINCREMENT, 1); dmi_write(target, DMI_SBCS, sbcs); - for (int sbaccess = 0; sbaccess <= max_sbaccess; sbaccess++) { + for (uint32_t sbaccess = 0; sbaccess <= (uint32_t)max_sbaccess; sbaccess++) { sbcs = set_field(sbcs, DMI_SBCS_SBACCESS, sbaccess); dmi_write(target, DMI_SBCS, sbcs); @@ -2991,57 +2991,57 @@ static int riscv013_test_sba_config_reg(struct target *target, /* Test 6: Set sbbusyerror, only run this case in simulation as it is likely * impossible to hit otherwise */ -#ifdef SIM_ON - sbcs = set_field(sbcs_orig, DMI_SBCS_SBREADONADDR, 1); - dmi_write(target, DMI_SBCS, sbcs); - - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - - dmi_read(target, &rd_val, DMI_SBCS); - if (get_field(rd_val, DMI_SBCS_SBBUSYERROR)) { - sbcs = set_field(sbcs_orig, DMI_SBCS_SBBUSYERROR, 1); + if (run_sim_only_tests) { + sbcs = set_field(sbcs_orig, DMI_SBCS_SBREADONADDR, 1); dmi_write(target, DMI_SBCS, sbcs); + + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_read(target, &rd_val, DMI_SBCS); - if (get_field(rd_val, DMI_SBCS_SBBUSYERROR) == 0) - LOG_INFO("System Bus Access Test 6: SBCS sbbusyerror test PASSED"); - else - LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to clear to 0"); - } else { - LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to set"); + if (get_field(rd_val, DMI_SBCS_SBBUSYERROR)) { + sbcs = set_field(sbcs_orig, DMI_SBCS_SBBUSYERROR, 1); + dmi_write(target, DMI_SBCS, sbcs); + dmi_read(target, &rd_val, DMI_SBCS); + if (get_field(rd_val, DMI_SBCS_SBBUSYERROR) == 0) + LOG_INFO("System Bus Access Test 6: SBCS sbbusyerror test PASSED"); + else + LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to clear to 0"); + } else { + LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to set"); + } } -#endif return ERROR_OK; diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 21fb5b47f..4ca474bd1 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -190,6 +190,8 @@ uint64_t riscv_scratch_ram_address; bool riscv_prefer_sba; +bool run_sim_only_tests; + /* In addition to the ones in the standard spec, we'll also expose additional * CSRs in this list. * The list is either NULL, or a series of ranges (inclusive), terminated with @@ -1430,8 +1432,8 @@ COMMAND_HANDLER(riscv_dmi_write) COMMAND_HANDLER(riscv_test_sba_config_reg) { - if (CMD_ARGC != 2) { - LOG_ERROR("Command takes exactly 2 arguments"); + if (CMD_ARGC != 3) { + LOG_ERROR("Command takes exactly 3 arguments"); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -1442,6 +1444,7 @@ COMMAND_HANDLER(riscv_test_sba_config_reg) target_addr_t illegal_address; COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], legal_address); COMMAND_PARSE_NUMBER(u64, CMD_ARGV[1], illegal_address); + COMMAND_PARSE_ON_OFF(CMD_ARGV[2], run_sim_only_tests); if (r->test_sba_config_reg) { return r->test_sba_config_reg(target, legal_address, illegal_address); @@ -1522,10 +1525,12 @@ static const struct command_registration riscv_exec_command_handlers[] = { .name = "test_sba_config_reg", .handler = riscv_test_sba_config_reg, .mode = COMMAND_ANY, - .usage = "riscv test_sba_config_reg legal_address illegal_address", + .usage = "riscv test_sba_config_reg legal_address" + "illegal_address run_sim_only_tests[on/off]", .help = "Perform a series of tests on the SBCS register." "Inputs are a legal address for read/write tests," - "and an illegal address for error flag/handling cases." + "an illegal address for error flag/handling cases, and" + "whether sim_only tests should be run." }, COMMAND_REGISTRATION_DONE }; diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index 8ac4f86cb..367b67023 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -133,6 +133,8 @@ extern uint64_t riscv_scratch_ram_address; extern bool riscv_prefer_sba; +extern bool run_sim_only_tests; + /* Everything needs the RISC-V specific info structure, so here's a nice macro * that provides that. */ static inline riscv_info_t *riscv_info(const struct target *target) __attribute__((unused));