riscv: translate virtual address to physical address. (#425)
* riscv: translate virtual address to physical address. * riscv: fix formatting errors. * riscv: fix build errors. * riscv: Remove redundant command for virtual address access. * Revert "riscv: Remove redundant command for virtual address access." This reverts commit 990d09eac37d2effcfc5c0d0b5c99678f45e7d7f. * riscv: Change command disable_virt2phys to set_enable_virt2phys 1. Avoid double negative logic to make users easy to use. 2. Add document about new comomand 'riscv set_enable_virt2phys on|off'busy
Hsiangkai
Tim Newsome
parent
aec5cca15b
commit
9886f77374
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@ -9472,12 +9472,18 @@ When on, prefer to use System Bus Access to access memory. When off, prefer to
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use the Program Buffer to access memory.
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@end deffn
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@deffn Command {riscv riscv_enable_virtual} on|off
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@deffn Command {riscv set_enable_virtual} on|off
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When on, memory accesses are performed on physical or virtual memory depending
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on the current system configuration. When off, all memory accessses are performed
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on physical memory.
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@end deffn
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@deffn Command {riscv set_enable_virt2phys} on|off
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When on, memory accesses are performed on physical or virtual memory depending
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on the current satp configuration. When off, all memory accessses are performed
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on physical memory.
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@end deffn
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@deffn Command {riscv resume_order} normal|reversed
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Some software assumes all harts are executing nearly continuously. Such
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software may be sensitive to the order that harts are resumed in. On harts
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@ -86,6 +86,7 @@ enum gdb_regno {
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GDB_REGNO_MSTATUS = CSR_MSTATUS + GDB_REGNO_CSR0,
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GDB_REGNO_MEPC = CSR_MEPC + GDB_REGNO_CSR0,
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GDB_REGNO_MCAUSE = CSR_MCAUSE + GDB_REGNO_CSR0,
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GDB_REGNO_SATP = CSR_SATP + GDB_REGNO_CSR0,
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GDB_REGNO_CSR4095 = GDB_REGNO_CSR0 + 4095,
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GDB_REGNO_PRIV = 4161,
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GDB_REGNO_COUNT
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@ -251,6 +251,7 @@ int riscv_command_timeout_sec = DEFAULT_COMMAND_TIMEOUT_SEC;
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int riscv_reset_timeout_sec = DEFAULT_RESET_TIMEOUT_SEC;
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bool riscv_prefer_sba;
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bool riscv_enable_virt2phys = true;
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bool riscv_enable_virtual;
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@ -271,6 +272,39 @@ static enum {
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RO_REVERSED
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} resume_order;
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virt2phys_info_t sv32 = {
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.level = 2,
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.pte_shift = 2,
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.vpn_shift = {12, 22},
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.vpn_mask = {0x3ff, 0x3ff},
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.pte_ppn_shift = {10, 20},
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.pte_ppn_mask = {0x3ff, 0xfff},
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.pa_ppn_shift = {12, 22},
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.pa_ppn_mask = {0x3ff, 0xfff},
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};
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virt2phys_info_t sv39 = {
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.level = 3,
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.pte_shift = 3,
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.vpn_shift = {12, 21, 30},
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.vpn_mask = {0x1ff, 0x1ff, 0x1ff},
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.pte_ppn_shift = {10, 19, 28},
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.pte_ppn_mask = {0x1ff, 0x1ff, 0x3ffffff},
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.pa_ppn_shift = {12, 21, 30},
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.pa_ppn_mask = {0x1ff, 0x1ff, 0x3ffffff},
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};
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virt2phys_info_t sv48 = {
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.level = 4,
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.pte_shift = 3,
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.vpn_shift = {12, 21, 30, 39},
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.vpn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ff},
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.pte_ppn_shift = {10, 19, 28, 37},
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.pte_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
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.pa_ppn_shift = {12, 21, 30, 39},
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.pa_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
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};
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static int riscv_resume_go_all_harts(struct target *target);
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void select_dmi_via_bscan(struct target *target)
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@ -1328,20 +1362,184 @@ static int riscv_select_current_hart(struct target *target)
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return riscv_set_current_hartid(target, target->coreid);
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}
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static int riscv_mmu(struct target *target, int *enabled)
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{
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if (riscv_rtos_enabled(target))
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riscv_set_current_hartid(target, target->rtos->current_thread - 1);
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riscv_reg_t value;
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int result = riscv_get_register(target, &value, GDB_REGNO_SATP);
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if (result != ERROR_OK) {
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LOG_DEBUG("Couldn't read SATP.");
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return result;
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}
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if (get_field(value, RISCV_SATP_MODE(riscv_xlen(target))) == SATP_MODE_OFF) {
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LOG_DEBUG("MMU is disabled.");
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*enabled = 0;
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} else {
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LOG_DEBUG("MMU is enabled.");
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*enabled = 1;
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}
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return ERROR_OK;
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}
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static int riscv_address_translate(struct target *target,
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target_addr_t virtual, target_addr_t *physical)
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{
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riscv_reg_t satp_value;
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int mode;
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uint64_t ppn_value;
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target_addr_t table_address;
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virt2phys_info_t *info;
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struct target_type *tt = get_target_type(target);
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uint64_t pte;
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int i;
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if (riscv_rtos_enabled(target))
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riscv_set_current_hartid(target, target->rtos->current_thread - 1);
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int result = riscv_get_register(target, &satp_value, GDB_REGNO_SATP);
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if (result != ERROR_OK)
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return result;
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mode = get_field(satp_value, RISCV_SATP_MODE(riscv_xlen(target)));
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switch (mode) {
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case SATP_MODE_SV32:
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LOG_DEBUG("Translation mode: SV32");
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info = &sv32;
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break;
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case SATP_MODE_SV39:
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LOG_DEBUG("Translation mode: SV39");
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info = &sv39;
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break;
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case SATP_MODE_SV48:
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LOG_DEBUG("Translation mode: SV48");
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info = &sv48;
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break;
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case SATP_MODE_OFF:
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LOG_ERROR("No translation or protection." \
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" (satp: 0x%" PRIx64")", satp_value);
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return ERROR_FAIL;
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default:
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LOG_ERROR("The translation mode is not supported." \
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" (satp: 0x%" PRIx64")", satp_value);
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return ERROR_FAIL;
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}
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ppn_value = get_field(satp_value, RISCV_SATP_PPN(riscv_xlen(target)));
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table_address = ppn_value << RISCV_PGSHIFT;
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i = info->level - 1;
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while (i >= 0) {
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uint64_t vpn = virtual >> info->vpn_shift[i];
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vpn &= info->vpn_mask[i];
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target_addr_t pte_address = table_address +
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(vpn << info->pte_shift);
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uint8_t buffer[8];
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assert(info->pte_shift <= 3);
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int retval = tt->read_memory(target, pte_address,
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4, (1 << info->pte_shift) / 4, buffer);
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if (retval != ERROR_OK)
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return ERROR_FAIL;
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if (info->pte_shift == 2)
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pte = buf_get_u32(buffer, 0, 32);
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else
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pte = buf_get_u64(buffer, 0, 64);
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if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W)))
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return ERROR_FAIL;
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if ((pte & PTE_R) || (pte & PTE_X)) /* Found leaf PTE. */
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break;
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i--;
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if (i < 0)
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break;
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ppn_value = pte >> PTE_PPN_SHIFT;
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table_address = ppn_value << RISCV_PGSHIFT;
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}
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if (i < 0) {
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LOG_ERROR("Couldn't find the PTE.");
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return ERROR_FAIL;
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}
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*physical = virtual;
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while (i < info->level) {
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ppn_value = pte >> info->pte_ppn_shift[i];
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ppn_value &= info->pte_ppn_mask[i];
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*physical &= ~(info->pa_ppn_mask[i] << info->pa_ppn_shift[i]);
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*physical |= (ppn_value << info->pa_ppn_shift[i]);
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i++;
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}
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LOG_DEBUG("Virtual address: 0x%" TARGET_PRIxADDR, virtual);
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LOG_DEBUG("Physical address: 0x%" TARGET_PRIxADDR, *physical);
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return ERROR_OK;
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}
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static int riscv_virt2phys(struct target *target, target_addr_t virtual, target_addr_t *physical)
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{
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if (!riscv_enable_virt2phys)
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return ERROR_FAIL;
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int enabled;
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if (riscv_mmu(target, &enabled) == ERROR_OK) {
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if (!enabled)
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return ERROR_FAIL;
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if (riscv_address_translate(target, virtual, physical) == ERROR_OK)
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return ERROR_OK;
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}
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return ERROR_FAIL;
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}
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static int riscv_read_phys_memory(struct target *target, target_addr_t phys_address,
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uint32_t size, uint32_t count, uint8_t *buffer)
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{
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if (riscv_select_current_hart(target) != ERROR_OK)
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return ERROR_FAIL;
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struct target_type *tt = get_target_type(target);
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return tt->read_memory(target, phys_address, size, count, buffer);
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}
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static int riscv_read_memory(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, uint8_t *buffer)
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{
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if (riscv_select_current_hart(target) != ERROR_OK)
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return ERROR_FAIL;
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target_addr_t physical_addr;
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if (target->type->virt2phys(target, address, &physical_addr) == ERROR_OK)
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address = physical_addr;
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struct target_type *tt = get_target_type(target);
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return tt->read_memory(target, address, size, count, buffer);
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}
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static int riscv_write_phys_memory(struct target *target, target_addr_t phys_address,
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uint32_t size, uint32_t count, const uint8_t *buffer)
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{
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if (riscv_select_current_hart(target) != ERROR_OK)
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return ERROR_FAIL;
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struct target_type *tt = get_target_type(target);
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return tt->write_memory(target, phys_address, size, count, buffer);
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}
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static int riscv_write_memory(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, const uint8_t *buffer)
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{
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if (riscv_select_current_hart(target) != ERROR_OK)
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return ERROR_FAIL;
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target_addr_t physical_addr;
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if (target->type->virt2phys(target, address, &physical_addr) == ERROR_OK)
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address = physical_addr;
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struct target_type *tt = get_target_type(target);
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return tt->write_memory(target, address, size, count, buffer);
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}
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@ -2251,6 +2449,16 @@ COMMAND_HANDLER(riscv_use_bscan_tunnel)
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return ERROR_OK;
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}
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COMMAND_HANDLER(riscv_set_enable_virt2phys)
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{
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if (CMD_ARGC != 1) {
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LOG_ERROR("Command takes exactly 1 parameter");
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return ERROR_COMMAND_SYNTAX_ERROR;
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}
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COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_enable_virt2phys);
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return ERROR_OK;
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}
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static const struct command_registration riscv_exec_command_handlers[] = {
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{
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.name = "test_compliance",
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@ -2386,6 +2594,13 @@ static const struct command_registration riscv_exec_command_handlers[] = {
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"(optional) to indicate Bscan Tunnel Type {0:(default) NESTED_TAP , "
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"1: DATA_REGISTER}"
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},
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{
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.name = "set_enable_virt2phys",
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.handler = riscv_set_enable_virt2phys,
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.mode = COMMAND_ANY,
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.usage = "riscv set_enable_virt2phys on|off",
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.help = "Enable translation from virtual address to physical address."
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},
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COMMAND_REGISTRATION_DONE
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};
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@ -2489,9 +2704,14 @@ struct target_type riscv_target = {
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.read_memory = riscv_read_memory,
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.write_memory = riscv_write_memory,
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.read_phys_memory = riscv_read_phys_memory,
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.write_phys_memory = riscv_write_phys_memory,
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.checksum_memory = riscv_checksum_memory,
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.mmu = riscv_mmu,
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.virt2phys = riscv_virt2phys,
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.get_gdb_reg_list = riscv_get_gdb_reg_list,
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.get_gdb_reg_list_noread = riscv_get_gdb_reg_list_noread,
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@ -3001,6 +3221,8 @@ const char *gdb_regno_name(enum gdb_regno regno)
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return "mcause";
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case GDB_REGNO_PRIV:
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return "priv";
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case GDB_REGNO_SATP:
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return "satp";
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default:
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if (regno <= GDB_REGNO_XPR31)
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sprintf(buf, "x%d", regno - GDB_REGNO_ZERO);
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@ -17,6 +17,12 @@ struct riscv_program;
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#define DEFAULT_COMMAND_TIMEOUT_SEC 2
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#define DEFAULT_RESET_TIMEOUT_SEC 30
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#define RISCV_SATP_MODE(xlen) ((xlen) == 32 ? SATP32_MODE : SATP64_MODE)
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#define RISCV_SATP_PPN(xlen) ((xlen) == 32 ? SATP32_PPN : SATP64_PPN)
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#define RISCV_PGSHIFT 12
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# define PG_MAX_LEVEL 4
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extern struct target_type riscv011_target;
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extern struct target_type riscv013_target;
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@ -149,6 +155,16 @@ typedef struct {
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struct scan_field tunneled_dr[4];
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} riscv_bscan_tunneled_scan_context_t;
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typedef struct {
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int level;
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unsigned pte_shift;
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unsigned vpn_shift[PG_MAX_LEVEL];
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unsigned vpn_mask[PG_MAX_LEVEL];
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unsigned pte_ppn_shift[PG_MAX_LEVEL];
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unsigned pte_ppn_mask[PG_MAX_LEVEL];
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unsigned pa_ppn_shift[PG_MAX_LEVEL];
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unsigned pa_ppn_mask[PG_MAX_LEVEL];
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} virt2phys_info_t;
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/* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
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extern int riscv_command_timeout_sec;
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Reference in New Issue