fix eol native
git-svn-id: svn://svn.berlios.de/openocd/trunk@2353 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
oharboe
parent
1f28b934ce
commit
974d5f8391
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@ -1,97 +1,97 @@
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#
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# Texas Instruments DaVinci family: TMS320DM365
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#
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME dm365
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}
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#
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# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
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# are enabled without making ICEpick route ARM and ETB into the JTAG chain.
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#
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# Also note: when running without RTCK before the PLLs are set up, you
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# may need to slow the JTAG clock down quite a lot (under 2 MHz).
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#
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source [find target/icepick.cfg]
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set EMU01 "-enable"
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#set EMU01 "-disable"
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# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
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if { [info exists ETB_TAPID ] } {
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set _ETB_TAPID $ETB_TAPID
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} else {
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set _ETB_TAPID 0x2b900f0f
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}
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jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
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-expected-id $_ETB_TAPID $EMU01
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jtag configure $_CHIPNAME.etb -event tap-enable \
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"icepick_c_tapenable $_CHIPNAME.jrc 1"
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# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
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if { [info exists CPU_TAPID ] } {
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set _CPU_TAPID $CPU_TAPID
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} else {
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set _CPU_TAPID 0x0792602f
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}
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jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
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-expected-id $_CPU_TAPID $EMU01
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jtag configure $_CHIPNAME.arm -event tap-enable \
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"icepick_c_tapenable $_CHIPNAME.jrc 0"
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# Primary TAP: ICEpick (JTAG route controller) and boundary scan
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if { [info exists JRC_TAPID ] } {
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set _JRC_TAPID $JRC_TAPID
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} else {
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set _JRC_TAPID 0x0b83e02f
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}
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jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
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-expected-id $_JRC_TAPID
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################
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# various symbol definitions, to avoid hard-wiring addresses
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# and enable some sharing of DaVinci-family utility code
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global dm365
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set dm365 [ dict create ]
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# Physical addresses for controllers and memory
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# (Some of these are valid for many DaVinci family chips)
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dict set dm365 sram0 0x00010000
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dict set dm365 sram1 0x00014000
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dict set dm365 sysbase 0x01c40000
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dict set dm365 pllc1 0x01c40800
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dict set dm365 pllc2 0x01c40c00
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dict set dm365 psc 0x01c41000
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dict set dm365 gpio 0x01c67000
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dict set dm365 a_emif 0x01d10000
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dict set dm365 a_emif_cs0 0x02000000
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dict set dm365 a_emif_cs1 0x04000000
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dict set dm365 ddr_emif 0x20000000
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dict set dm365 ddr 0x80000000
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source [find target/davinci.cfg]
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################
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# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
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# and the ETB memory (4K) are other options, while trace is unused.
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set _TARGETNAME $_CHIPNAME.arm
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target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
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# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
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# and that the work area is used only with a kernel mmu context ...
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$_TARGETNAME configure \
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-work-area-virt [expr 0xfffe0000 + 0x4000] \
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-work-area-phys [dict get $dm365 sram1] \
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-work-area-size 0x4000 \
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-work-area-backup 0
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arm7_9 dbgrq enable
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arm7_9 fast_memory_access enable
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arm7_9 dcc_downloads enable
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# trace setup
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etm config $_TARGETNAME 16 normal full etb
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etb config $_TARGETNAME $_CHIPNAME.etb
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#
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# Texas Instruments DaVinci family: TMS320DM365
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#
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME dm365
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}
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#
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# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
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# are enabled without making ICEpick route ARM and ETB into the JTAG chain.
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#
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# Also note: when running without RTCK before the PLLs are set up, you
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# may need to slow the JTAG clock down quite a lot (under 2 MHz).
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#
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source [find target/icepick.cfg]
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set EMU01 "-enable"
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#set EMU01 "-disable"
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# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
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if { [info exists ETB_TAPID ] } {
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set _ETB_TAPID $ETB_TAPID
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} else {
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set _ETB_TAPID 0x2b900f0f
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}
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jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
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-expected-id $_ETB_TAPID $EMU01
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jtag configure $_CHIPNAME.etb -event tap-enable \
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"icepick_c_tapenable $_CHIPNAME.jrc 1"
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# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
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if { [info exists CPU_TAPID ] } {
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set _CPU_TAPID $CPU_TAPID
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} else {
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set _CPU_TAPID 0x0792602f
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}
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jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
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-expected-id $_CPU_TAPID $EMU01
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jtag configure $_CHIPNAME.arm -event tap-enable \
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"icepick_c_tapenable $_CHIPNAME.jrc 0"
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# Primary TAP: ICEpick (JTAG route controller) and boundary scan
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if { [info exists JRC_TAPID ] } {
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set _JRC_TAPID $JRC_TAPID
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} else {
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set _JRC_TAPID 0x0b83e02f
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}
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jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
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-expected-id $_JRC_TAPID
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################
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# various symbol definitions, to avoid hard-wiring addresses
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# and enable some sharing of DaVinci-family utility code
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global dm365
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set dm365 [ dict create ]
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# Physical addresses for controllers and memory
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# (Some of these are valid for many DaVinci family chips)
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dict set dm365 sram0 0x00010000
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dict set dm365 sram1 0x00014000
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dict set dm365 sysbase 0x01c40000
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dict set dm365 pllc1 0x01c40800
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dict set dm365 pllc2 0x01c40c00
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dict set dm365 psc 0x01c41000
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dict set dm365 gpio 0x01c67000
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dict set dm365 a_emif 0x01d10000
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dict set dm365 a_emif_cs0 0x02000000
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dict set dm365 a_emif_cs1 0x04000000
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dict set dm365 ddr_emif 0x20000000
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dict set dm365 ddr 0x80000000
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source [find target/davinci.cfg]
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################
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# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
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# and the ETB memory (4K) are other options, while trace is unused.
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set _TARGETNAME $_CHIPNAME.arm
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target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
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# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
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# and that the work area is used only with a kernel mmu context ...
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$_TARGETNAME configure \
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-work-area-virt [expr 0xfffe0000 + 0x4000] \
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-work-area-phys [dict get $dm365 sram1] \
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-work-area-size 0x4000 \
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-work-area-backup 0
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arm7_9 dbgrq enable
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arm7_9 fast_memory_access enable
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arm7_9 dcc_downloads enable
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# trace setup
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etm config $_TARGETNAME 16 normal full etb
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etb config $_TARGETNAME $_CHIPNAME.etb
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