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armv4_5: Integrate build of checksum code 

Add rules to build armv4_5_crc.inc, and convert the code to target
endianness the least intrusive way.

Change-Id: I7452b2c7e679dae14f9cda5f89bc81c16fc12cad
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3473
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
__archive__
Andreas Färber 2016-05-08 20:12:12 +02:00 committed by Andreas Fritiofson
parent 18f7a2d072
commit 9728ac3fba
3 changed files with 25 additions and 34 deletions
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11
contrib/loaders/checksum/Makefile
View File

@ -4,7 +4,16 @@ ARM_CROSS_COMPILE ?= arm-none-eabi-
ARM_AS ?= $(ARM_CROSS_COMPILE)as
ARM_OBJCOPY ?= $(ARM_CROSS_COMPILE)objcopy
arm: armv7m_crc.inc
arm: armv4_5_crc.inc armv7m_crc.inc
armv4_5_%.elf: armv4_5_%.s
$(ARM_AS) $< -o $@
armv4_5_%.bin: armv4_5_%.elf
$(ARM_OBJCOPY) -Obinary $< $@
armv4_5_%.inc: armv4_5_%.bin
$(BIN2C) < $< > $@
armv7m_%.elf: armv7m_%.s
$(ARM_AS) $< -o $@

7
contrib/loaders/checksum/armv4_5_crc.inc Normal file
View File

@ -0,0 +1,7 @@
/* Autogenerated with ../../../src/helper/bin2char.sh */
0x00,0x20,0xa0,0xe1,0x00,0x00,0xe0,0xe3,0x01,0x30,0xa0,0xe1,0x00,0x40,0xa0,0xe3,
0x0b,0x00,0x00,0xea,0x04,0x10,0xd2,0xe7,0x30,0x70,0x9f,0xe5,0x01,0x0c,0x20,0xe0,
0x00,0x50,0xa0,0xe3,0x00,0x00,0x50,0xe3,0x80,0x60,0xa0,0xe1,0x01,0x50,0x85,0xe2,
0x06,0x00,0xa0,0xe1,0x07,0x00,0x26,0xb0,0x08,0x00,0x55,0xe3,0xf8,0xff,0xff,0x1a,
0x01,0x40,0x84,0xe2,0x03,0x00,0x54,0xe1,0xf1,0xff,0xff,0x1a,0x70,0x00,0x20,0xe1,
0xb7,0x1d,0xc1,0x04,

41
src/target/armv4_5.c
View File

@ -1425,47 +1425,22 @@ int arm_checksum_memory(struct target *target,
uint32_t i;
uint32_t exit_var = 0;
/* see contrib/loaders/checksum/armv4_5_crc.s for src */
static const uint32_t arm_crc_code[] = {
0xE1A02000, /* mov r2, r0 */
0xE3E00000, /* mov r0, #0xffffffff */
0xE1A03001, /* mov r3, r1 */
0xE3A04000, /* mov r4, #0 */
0xEA00000B, /* b ncomp */
/* nbyte: */
0xE7D21004, /* ldrb r1, [r2, r4] */
0xE59F7030, /* ldr r7, CRC32XOR */
0xE0200C01, /* eor r0, r0, r1, asl 24 */
0xE3A05000, /* mov r5, #0 */
/* loop: */
0xE3500000, /* cmp r0, #0 */
0xE1A06080, /* mov r6, r0, asl #1 */
0xE2855001, /* add r5, r5, #1 */
0xE1A00006, /* mov r0, r6 */
0xB0260007, /* eorlt r0, r6, r7 */
0xE3550008, /* cmp r5, #8 */
0x1AFFFFF8, /* bne loop */
0xE2844001, /* add r4, r4, #1 */
/* ncomp: */
0xE1540003, /* cmp r4, r3 */
0x1AFFFFF1, /* bne nbyte */
/* end: */
0xe1200070, /* bkpt #0 */
/* CRC32XOR: */
0x04C11DB7 /* .word 0x04C11DB7 */
static const uint8_t arm_crc_code_le[] = {
#include "../../contrib/loaders/checksum/armv4_5_crc.inc"
};
assert(sizeof(arm_crc_code_le) % 4 == 0);
retval = target_alloc_working_area(target,
sizeof(arm_crc_code), &crc_algorithm);
sizeof(arm_crc_code_le), &crc_algorithm);
if (retval != ERROR_OK)
return retval;
/* convert code into a buffer in target endianness */
for (i = 0; i < ARRAY_SIZE(arm_crc_code); i++) {
for (i = 0; i < ARRAY_SIZE(arm_crc_code_le) / 4; i++) {
retval = target_write_u32(target,
crc_algorithm->address + i * sizeof(uint32_t),
arm_crc_code[i]);
le_to_h_u32(&arm_crc_code_le[i * 4]));
if (retval != ERROR_OK)
goto cleanup;
}
@ -1485,7 +1460,7 @@ int arm_checksum_memory(struct target *target,
/* armv4 must exit using a hardware breakpoint */
if (arm->is_armv4)
exit_var = crc_algorithm->address + sizeof(arm_crc_code) - 8;
exit_var = crc_algorithm->address + sizeof(arm_crc_code_le) - 8;
retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
crc_algorithm->address,