David Brownell <david-b@pacbell.net>:
Improve the PXA255 target config: move all that board-specific setup to the pxa255_sst board.cfg, to which it evidently belongs (it's the only PXA255 board now included). Provide the PXA255 JTAG id from Intel docs, and add a comment about how this chip is now EOL'd (last orders taken). Note that I still can't get my old PXA255 board to work. There's something broken in the reset sequence, which is preventing the TAP from coming up at all. Old mailing list posts suggest this is a longstanding bug... git-svn-id: svn://svn.berlios.de/openocd/trunk@2416 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
zwelch
parent
f0fd28a66c
commit
95da247b40
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@ -8,8 +8,91 @@
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# Flash at 0x00000000
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# Flash at 0x00000000
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#
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#
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source [find target/pxa255.cfg]
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source [find target/pxa255.cfg]
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# Target name is set by above
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# Target name is set by above
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$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
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$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
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# flash bank <driver> <base> <size> <chip_width> <bus_width> <targetNum> [options]
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flash bank cfi 0x00000000 0x80000 2 2 0 jedec_probe
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# flash bank <driver> <base> <size> <chip_width> <bus_width> <target> [options]
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flash bank cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
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proc pxa255_sst_init {} {
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xscale cp15 15 0x00002001 #Enable CP0 and CP13 access
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#
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# setup GPIO
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#
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mww 0x40E00018 0x00008000 #CPSR0
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sleep 20
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mww 0x40E0001C 0x00000002 #GPSR1
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sleep 20
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mww 0x40E00020 0x00000008 #GPSR2
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sleep 20
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mww 0x40E0000C 0x00008000 #GPDR0
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sleep 20
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mww 0x40E00054 0x80000000 #GAFR0_L
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sleep 20
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mww 0x40E00058 0x00188010 #GAFR0_H
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sleep 20
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mww 0x40E0005C 0x60908018 #GAFR1_L
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sleep 20
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mww 0x40E0000C 0x0280E000 #GPDR0
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sleep 20
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mww 0x40E00010 0x821C88B2 #GPDR1
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sleep 20
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mww 0x40E00014 0x000F03DB #GPDR2
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sleep 20
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mww 0x40E00000 0x000F03DB #GPLR0
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sleep 20
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mww 0x40F00004 0x00000020 #PSSR
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sleep 20
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#
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# setup memory controller
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#
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mww 0x48000008 0x01111998 #MSC0
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sleep 20
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mww 0x48000010 0x00047ff0 #MSC2
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sleep 20
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mww 0x48000014 0x00000000 #MECR
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sleep 20
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mww 0x48000028 0x00010504 #MCMEM0
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sleep 20
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mww 0x4800002C 0x00010504 #MCMEM1
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sleep 20
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mww 0x48000030 0x00010504 #MCATT0
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sleep 20
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mww 0x48000034 0x00010504 #MCATT1
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sleep 20
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mww 0x48000038 0x00004715 #MCIO0
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sleep 20
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mww 0x4800003C 0x00004715 #MCIO1
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sleep 20
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#
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mww 0x48000004 0x03CA4018 #MDREF
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sleep 20
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mww 0x48000004 0x004B4018 #MDREF
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sleep 20
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mww 0x48000004 0x000B4018 #MDREF
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sleep 20
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mww 0x48000004 0x000BC018 #MDREF
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sleep 20
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mww 0x48000000 0x00001AC8 #MDCNFG
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sleep 20
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sleep 20
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mww 0x48000000 0x00001AC9 #MDCNFG
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sleep 20
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mww 0x48000040 0x00000000 #MDMRS
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sleep 20
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}
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$_TARGETNAME configure -event reset-init {pxa255_sst_init}
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reset_config trst_and_srst
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jtag_nsrst_delay 200
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jtag_ntrst_delay 200
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#xscale debug_handler 0 0xFFFF0800 # debug handler base address
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@ -1,3 +1,6 @@
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# PXA255 chip ... originally from Intel, PXA line was sold to Marvell.
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# This chip is now at end-of-life. Final orders have been taken.
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if { [info exists CHIPNAME] } {
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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set _CHIPNAME $CHIPNAME
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} else {
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} else {
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@ -13,92 +16,11 @@ if { [info exists ENDIAN] } {
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if { [info exists CPUTAPID ] } {
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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set _CPUTAPID $CPUTAPID
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} else {
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} else {
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# force an error till we get a good number
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set _CPUTAPID 0x69264013
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set _CPUTAPID 0xffffffff
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}
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}
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jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
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jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1e -irmask 0x1f -expected-id $_CPUTAPID
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jtag_nsrst_delay 200
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jtag_ntrst_delay 200
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set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
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target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa255
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$_TARGETNAME configure -event reset-init {
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xscale cp15 15 0x00002001 #Enable CP0 and CP13 access
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#
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# setup GPIO
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#
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mww 0x40E00018 0x00008000 #CPSR0
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sleep 20
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mww 0x40E0001C 0x00000002 #GPSR1
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sleep 20
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mww 0x40E00020 0x00000008 #GPSR2
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sleep 20
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mww 0x40E0000C 0x00008000 #GPDR0
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sleep 20
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mww 0x40E00054 0x80000000 #GAFR0_L
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sleep 20
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mww 0x40E00058 0x00188010 #GAFR0_H
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sleep 20
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mww 0x40E0005C 0x60908018 #GAFR1_L
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sleep 20
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mww 0x40E0000C 0x0280E000 #GPDR0
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sleep 20
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mww 0x40E00010 0x821C88B2 #GPDR1
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sleep 20
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mww 0x40E00014 0x000F03DB #GPDR2
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sleep 20
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mww 0x40E00000 0x000F03DB #GPLR0
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sleep 20
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mww 0x40F00004 0x00000020 #PSSR
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sleep 20
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#
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# setup memory controller
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#
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mww 0x48000008 0x01111998 #MSC0
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sleep 20
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mww 0x48000010 0x00047ff0 #MSC2
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sleep 20
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mww 0x48000014 0x00000000 #MECR
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sleep 20
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mww 0x48000028 0x00010504 #MCMEM0
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sleep 20
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mww 0x4800002C 0x00010504 #MCMEM1
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sleep 20
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mww 0x48000030 0x00010504 #MCATT0
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sleep 20
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mww 0x48000034 0x00010504 #MCATT1
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sleep 20
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mww 0x48000038 0x00004715 #MCIO0
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sleep 20
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mww 0x4800003C 0x00004715 #MCIO1
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sleep 20
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#
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mww 0x48000004 0x03CA4018 #MDREF
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sleep 20
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mww 0x48000004 0x004B4018 #MDREF
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sleep 20
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mww 0x48000004 0x000B4018 #MDREF
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sleep 20
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mww 0x48000004 0x000BC018 #MDREF
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sleep 20
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mww 0x48000000 0x00001AC8 #MDCNFG
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sleep 20
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sleep 20
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mww 0x48000000 0x00001AC9 #MDCNFG
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sleep 20
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mww 0x48000040 0x00000000 #MDMRS
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sleep 20
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}
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reset_config trst_and_srst
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#xscale debug_handler 0 0xFFFF0800 # debug handler base address
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME
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debug_level 3
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Loading…
Reference in New Issue