riscv-compliance: incorporate review feedback
Megan Wachs
parent
34ee883aef
commit
934440b80e
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@ -3058,6 +3058,21 @@ void riscv013_clear_abstract_error(struct target *target)
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total_tests++; \
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}
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#define COMPLIANCE_MUST_PASS(b) COMPLIANCE_TEST(ERROR_OK == (b), "Regular calls must return ERROR_OK")
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#define COMPLIANCE_READ(target, addr, value) COMPLIANCE_MUST_PASS(dmi_read(target, addr, value))
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#define COMPLIANCE_WRITE(target, addr, value) COMPLIANCE_MUST_PASS(dmi_write(target, addr, value))
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#define COMPLIANCE_CHECK_RO(target, addr) \
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{ \
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uint32_t orig; \
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uint32_t inverse; \
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COMPLIANCE_READ(target, &orig, addr); \
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COMPLIANCE_WRITE(target, addr, ~orig); \
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COMPLIANCE_READ(target, &inverse, addr); \
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COMPLIANCE_TEST(orig == inverse, "Register must be read-only"); \
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}
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int riscv013_test_compliance(struct target *target)
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{
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LOG_INFO("Testing Compliance against RISC-V Debug Spec v0.13");
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@ -3077,71 +3092,48 @@ int riscv013_test_compliance(struct target *target)
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riscv_reg_t value;
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RISCV013_INFO(info);
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/* TODO: Support HARTSELLHI as well */
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dmcontrol = dmcontrol_orig | DMI_DMCONTROL_HARTSELLO;
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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dmi_read(target, &dmcontrol, DMI_DMCONTROL);
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COMPLIANCE_TEST(get_field(dmcontrol, DMI_DMCONTROL_HARTSELLO) == (uint32_t) ((1 << info->hartsellen) - 1),
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"DMCONTROL.hartsello should hold all the harts allowed by its hartsellen.");
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dmcontrol = set_field(dmcontrol_orig, DMI_DMCONTROL_HARTSELLO, 0);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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dmi_read(target, &dmcontrol, DMI_DMCONTROL);
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COMPLIANCE_TEST(get_field(dmcontrol, DMI_DMCONTROL_HARTSELLO) == 0,
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"DMCONTROL.hartsello should hold Hart ID 0");
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/* All the bits of HARTSEL is covered by the examine sequence. */
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/* hartreset */
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/* This field is optional. Either we can read and write it to 1/0,
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or it is tied to 0. */
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dmcontrol = set_field(dmcontrol_orig, DMI_DMCONTROL_HARTRESET, 1);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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dmi_read(target, &dmcontrol, DMI_DMCONTROL);
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testvar = get_field(dmcontrol, DMI_DMCONTROL_HARTRESET);
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dmcontrol = set_field(dmcontrol_orig, DMI_DMCONTROL_HARTRESET, 0);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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dmi_read(target, &dmcontrol, DMI_DMCONTROL);
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COMPLIANCE_TEST(((testvar == 0) || (get_field(dmcontrol, DMI_DMCONTROL_HARTRESET)) == 0),
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"DMCONTROL.hartreset can be 0 or RW.");
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or it is tied to 0. This check doesn't really do anything, but
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it does attempt to set the bit to 1 and then back to 0, which needs to
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work if its implemented. */
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COMPLIANCE_WRITE(target, DMI_DMCONTROL, set_field(dmcontrol_orig, DMI_DMCONTROL_HARTRESET, 1));
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COMPLIANCE_WRITE(target, DMI_DMCONTROL, set_field(dmcontrol_orig, DMI_DMCONTROL_HARTRESET, 0));
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COMPLIANCE_READ(target, &dmcontrol, DMI_DMCONTROL);
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COMPLIANCE_TEST((get_field(dmcontrol, DMI_DMCONTROL_HARTRESET) == 0),
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"DMCONTROL.hartreset can be 0 or RW.");
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/* hasel */
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dmcontrol = set_field(dmcontrol_orig, DMI_DMCONTROL_HASEL, 1);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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dmi_read(target, &dmcontrol, DMI_DMCONTROL);
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testvar = get_field(dmcontrol, DMI_DMCONTROL_HASEL);
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dmcontrol = set_field(dmcontrol_orig, DMI_DMCONTROL_HASEL, 0);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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dmi_read(target, &dmcontrol, DMI_DMCONTROL);
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COMPLIANCE_TEST(((testvar == 0) || (get_field(dmcontrol, DMI_DMCONTROL_HASEL)) == 0),
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COMPLIANCE_WRITE(target, DMI_DMCONTROL, set_field(dmcontrol_orig, DMI_DMCONTROL_HASEL, 1));
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COMPLIANCE_WRITE(target, DMI_DMCONTROL, set_field(dmcontrol_orig, DMI_DMCONTROL_HASEL, 0));
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COMPLIANCE_READ(target, &dmcontrol, DMI_DMCONTROL);
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COMPLIANCE_TEST((get_field(dmcontrol, DMI_DMCONTROL_HASEL) == 0),
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"DMCONTROL.hasel can be 0 or RW.");
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/* TODO: test that hamask registers exist if hasel does. */
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/* haltreq */
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riscv_halt_all_harts(target);
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COMPLIANCE_MUST_PASS(riscv_halt_all_harts(target));
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/* This bit is not actually readable according to the spec, so nothing to check.*/
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/* DMSTATUS */
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uint32_t dmstatus, dmstatus_read;
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dmi_read(target, &dmstatus, DMI_DMSTATUS);
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dmi_write(target, DMI_DMSTATUS, ~dmstatus);
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dmi_read(target, &dmstatus_read, DMI_DMSTATUS);
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COMPLIANCE_TEST(dmstatus_read == dmstatus, "DMSTATUS is R/O");
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COMPLIANCE_CHECK_RO(target, DMI_DMSTATUS);
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/* resumereq */
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/* This bit is not actually readable according to the spec, so nothing to check.*/
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riscv_resume_all_harts(target);
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COMPLIANCE_MUST_PASS(riscv_resume_all_harts(target));
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/* Halt all harts again so the test can continue.*/
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riscv_halt_all_harts(target);
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COMPLIANCE_MUST_PASS(riscv_halt_all_harts(target));
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/* HARTINFO: Read-Only. This is per-hart, so need to adjust hartsel. */
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uint32_t hartinfo;
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COMPLIANCE_READ(target, &hartinfo, DMI_HARTINFO);
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for (int hartsel = 0; hartsel < riscv_count_harts(target); hartsel++) {
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riscv_set_current_hartid(target, hartsel);
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COMPLIANCE_MUST_PASS(riscv_set_current_hartid(target, hartsel));
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uint32_t hartinfo, hartinfo_read;
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dmi_read(target, &hartinfo, DMI_HARTINFO);
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dmi_write(target, DMI_HARTINFO, ~hartinfo);
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dmi_read(target, &hartinfo_read, DMI_HARTINFO);
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COMPLIANCE_TEST((hartinfo_read == hartinfo), "DMHARTINFO should be Read-Only.");
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COMPLIANCE_CHECK_RO(target, DMI_HARTINFO);
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/* $dscratch CSRs */
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uint32_t nscratch = get_field(hartinfo, DMI_HARTINFO_NSCRATCH);
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@ -3195,16 +3187,16 @@ int riscv013_test_compliance(struct target *target)
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for (int i = 0; i < MIN(riscv_count_harts(target), 32); i++)
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expected_haltsum0 |= (1 << i);
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dmi_read(target, &testvar_read, DMI_HALTSUM0);
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COMPLIANCE_READ(target, &testvar_read, DMI_HALTSUM0);
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COMPLIANCE_TEST(testvar_read == expected_haltsum0,
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"HALTSUM0 should report summary of up to 32 halted harts");
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dmi_write(target, DMI_HALTSUM0, 0xffffffff);
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dmi_read(target, &testvar_read, DMI_HALTSUM0);
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COMPLIANCE_WRITE(target, DMI_HALTSUM0, 0xffffffff);
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COMPLIANCE_READ(target, &testvar_read, DMI_HALTSUM0);
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COMPLIANCE_TEST(testvar_read == expected_haltsum0, "HALTSUM0 should be R/O");
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dmi_write(target, DMI_HALTSUM0, 0x0);
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dmi_read(target, &testvar_read, DMI_HALTSUM0);
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COMPLIANCE_WRITE(target, DMI_HALTSUM0, 0x0);
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COMPLIANCE_READ(target, &testvar_read, DMI_HALTSUM0);
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COMPLIANCE_TEST(testvar_read == expected_haltsum0, "HALTSUM0 should be R/O");
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/* HALTSUM1 */
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@ -3212,16 +3204,16 @@ int riscv013_test_compliance(struct target *target)
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for (int i = 0; i < MIN(riscv_count_harts(target), 1024); i += 32)
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expected_haltsum1 |= (1 << (i/32));
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dmi_read(target, &testvar_read, DMI_HALTSUM1);
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COMPLIANCE_READ(target, &testvar_read, DMI_HALTSUM1);
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COMPLIANCE_TEST(testvar_read == expected_haltsum1,
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"HALTSUM1 should report summary of up to 1024 halted harts");
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dmi_write(target, DMI_HALTSUM1, 0xffffffff);
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dmi_read(target, &testvar_read, DMI_HALTSUM1);
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COMPLIANCE_WRITE(target, DMI_HALTSUM1, 0xffffffff);
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COMPLIANCE_READ(target, &testvar_read, DMI_HALTSUM1);
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COMPLIANCE_TEST(testvar_read == expected_haltsum1, "HALTSUM1 should be R/O");
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dmi_write(target, DMI_HALTSUM1, 0x0);
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dmi_read(target, &testvar_read, DMI_HALTSUM1);
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COMPLIANCE_WRITE(target, DMI_HALTSUM1, 0x0);
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COMPLIANCE_READ(target, &testvar_read, DMI_HALTSUM1);
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COMPLIANCE_TEST(testvar_read == expected_haltsum1, "HALTSUM1 should be R/O");
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/* TODO: HAWINDOWSEL */
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@ -3231,7 +3223,7 @@ int riscv013_test_compliance(struct target *target)
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/* ABSTRACTCS */
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uint32_t abstractcs;
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dmi_read(target, &abstractcs, DMI_ABSTRACTCS);
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COMPLIANCE_READ(target, &abstractcs, DMI_ABSTRACTCS);
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/* Check that all reported Data Words are really R/W */
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for (int invert = 0; invert < 2; invert++) {
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@ -3239,13 +3231,13 @@ int riscv013_test_compliance(struct target *target)
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testvar = (i + 1) * 0x11111111;
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if (invert)
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testvar = ~testvar;
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dmi_write(target, DMI_DATA0 + i, testvar);
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COMPLIANCE_WRITE(target, DMI_DATA0 + i, testvar);
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}
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for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_DATACOUNT); i++) {
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testvar = (i + 1) * 0x11111111;
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if (invert)
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testvar = ~testvar;
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dmi_read(target, &testvar_read, DMI_DATA0 + i);
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COMPLIANCE_READ(target, &testvar_read, DMI_DATA0 + i);
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COMPLIANCE_TEST(testvar_read == testvar, "All reported DATA words must be R/W");
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}
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}
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@ -3256,13 +3248,13 @@ int riscv013_test_compliance(struct target *target)
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testvar = (i + 1) * 0x11111111;
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if (invert)
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testvar = ~testvar;
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dmi_write(target, DMI_PROGBUF0 + i, testvar);
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COMPLIANCE_WRITE(target, DMI_PROGBUF0 + i, testvar);
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}
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for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_PROGBUFSIZE); i++) {
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testvar = (i + 1) * 0x11111111;
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if (invert)
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testvar = ~testvar;
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dmi_read(target, &testvar_read, DMI_PROGBUF0 + i);
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COMPLIANCE_READ(target, &testvar_read, DMI_PROGBUF0 + i);
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COMPLIANCE_TEST(testvar_read == testvar, "All reported PROGBUF words must be R/W");
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}
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}
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@ -3272,18 +3264,17 @@ int riscv013_test_compliance(struct target *target)
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/* COMMAND
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According to the spec, this register is only W, so can't really check the read result.
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But at any rate, this is not legal and should cause an error. */
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dmi_write(target, DMI_COMMAND, 0xAAAAAAAA);
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dmi_read(target, &testvar_read, DMI_COMMAND);
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dmi_read(target, &testvar_read, DMI_ABSTRACTCS);
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COMPLIANCE_WRITE(target, DMI_COMMAND, 0xAAAAAAAA);
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COMPLIANCE_READ(target, &testvar_read, DMI_ABSTRACTCS);
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COMPLIANCE_TEST(get_field(testvar_read, DMI_ABSTRACTCS_CMDERR) == CMDERR_NOT_SUPPORTED, \
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"Illegal COMMAND should result in UNSUPPORTED");
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dmi_write(target, DMI_ABSTRACTCS, DMI_ABSTRACTCS_CMDERR);
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dmi_write(target, DMI_COMMAND, 0x55555555);
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dmi_read(target, &testvar_read, DMI_COMMAND);
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dmi_read(target, &testvar_read, DMI_ABSTRACTCS);
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COMPLIANCE_WRITE(target, DMI_ABSTRACTCS, DMI_ABSTRACTCS_CMDERR);
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COMPLIANCE_WRITE(target, DMI_COMMAND, 0x55555555);
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COMPLIANCE_READ(target, &testvar_read, DMI_ABSTRACTCS);
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COMPLIANCE_TEST(get_field(testvar_read, DMI_ABSTRACTCS_CMDERR) == CMDERR_NOT_SUPPORTED, \
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"Illegal COMMAND should result in UNSUPPORTED");
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dmi_write(target, DMI_ABSTRACTCS, DMI_ABSTRACTCS_CMDERR);
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COMPLIANCE_WRITE(target, DMI_ABSTRACTCS, DMI_ABSTRACTCS_CMDERR);
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/* Basic Abstract Commands */
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for (unsigned int i = 1; i < 32; i = i << 1) {
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@ -3291,7 +3282,7 @@ int riscv013_test_compliance(struct target *target)
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riscv_reg_t testval_read;
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COMPLIANCE_TEST(ERROR_OK == register_write_direct(target, GDB_REGNO_ZERO + i, testval),
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"GPR Writes should be supported.");
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write_abstract_arg(target, 0, 0xDEADBEEFDEADBEEF, 64);
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COMPLIANCE_MUST_PASS(write_abstract_arg(target, 0, 0xDEADBEEFDEADBEEF, 64));
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COMPLIANCE_TEST(ERROR_OK == register_read_direct(target, &testval_read, GDB_REGNO_ZERO + i),
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"GPR Reads should be supported.");
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if (riscv_xlen(target) > 32) {
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@ -3305,11 +3296,11 @@ int riscv013_test_compliance(struct target *target)
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/* ABSTRACTAUTO
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See which bits are actually writable */
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dmi_write(target, DMI_ABSTRACTAUTO, 0xFFFFFFFF);
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COMPLIANCE_WRITE(target, DMI_ABSTRACTAUTO, 0xFFFFFFFF);
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uint32_t abstractauto;
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uint32_t busy;
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dmi_read(target, &abstractauto, DMI_ABSTRACTAUTO);
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dmi_write(target, DMI_ABSTRACTAUTO, 0x0);
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COMPLIANCE_READ(target, &abstractauto, DMI_ABSTRACTAUTO);
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COMPLIANCE_WRITE(target, DMI_ABSTRACTAUTO, 0x0);
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if (abstractauto > 0) {
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/* This mechanism only works when you have a reasonable sized progbuf, which is not
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a true compliance requirement. */
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@ -3319,22 +3310,22 @@ int riscv013_test_compliance(struct target *target)
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COMPLIANCE_TEST(ERROR_OK == register_write_direct(target, GDB_REGNO_S0, 0),
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"Need to be able to write S0 to test ABSTRACTAUTO");
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struct riscv_program program;
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riscv_program_init(&program, target);
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COMPLIANCE_MUST_PASS(riscv_program_init(&program, target));
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/* This is also testing that WFI() is a NOP during debug mode. */
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riscv_program_insert(&program, wfi());
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riscv_program_addi(&program, GDB_REGNO_S0, GDB_REGNO_S0, 1);
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riscv_program_ebreak(&program);
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dmi_write(target, DMI_ABSTRACTAUTO, 0x0);
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riscv_program_exec(&program, target);
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COMPLIANCE_MUST_PASS(riscv_program_insert(&program, wfi()));
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COMPLIANCE_MUST_PASS(riscv_program_addi(&program, GDB_REGNO_S0, GDB_REGNO_S0, 1));
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COMPLIANCE_MUST_PASS(riscv_program_ebreak(&program));
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COMPLIANCE_WRITE(target, DMI_ABSTRACTAUTO, 0x0);
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COMPLIANCE_MUST_PASS(riscv_program_exec(&program, target));
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testvar++;
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dmi_write(target, DMI_ABSTRACTAUTO, 0xFFFFFFFF);
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dmi_read(target, &abstractauto, DMI_ABSTRACTAUTO);
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COMPLIANCE_WRITE(target, DMI_ABSTRACTAUTO, 0xFFFFFFFF);
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COMPLIANCE_READ(target, &abstractauto, DMI_ABSTRACTAUTO);
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uint32_t autoexec_data = get_field(abstractauto, DMI_ABSTRACTAUTO_AUTOEXECDATA);
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uint32_t autoexec_progbuf = get_field(abstractauto, DMI_ABSTRACTAUTO_AUTOEXECPROGBUF);
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for (unsigned int i = 0; i < 12; i++) {
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dmi_read(target, &testvar_read, DMI_DATA0 + i);
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COMPLIANCE_READ(target, &testvar_read, DMI_DATA0 + i);
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do {
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dmi_read(target, &testvar_read, DMI_ABSTRACTCS);
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COMPLIANCE_READ(target, &testvar_read, DMI_ABSTRACTCS);
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busy = get_field(testvar_read, DMI_ABSTRACTCS_BUSY);
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} while (busy);
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if (autoexec_data & (1 << i)) {
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@ -3344,9 +3335,9 @@ int riscv013_test_compliance(struct target *target)
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}
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}
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for (unsigned int i = 0; i < 16; i++) {
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dmi_read(target, &testvar_read, DMI_PROGBUF0 + i);
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COMPLIANCE_READ(target, &testvar_read, DMI_PROGBUF0 + i);
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do {
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dmi_read(target, &testvar_read, DMI_ABSTRACTCS);
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COMPLIANCE_READ(target, &testvar_read, DMI_ABSTRACTCS);
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busy = get_field(testvar_read, DMI_ABSTRACTCS_BUSY);
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} while (busy);
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if (autoexec_progbuf & (1 << i)) {
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@ -3356,7 +3347,7 @@ int riscv013_test_compliance(struct target *target)
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}
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}
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dmi_write(target, DMI_ABSTRACTAUTO, 0);
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COMPLIANCE_WRITE(target, DMI_ABSTRACTAUTO, 0);
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COMPLIANCE_TEST(ERROR_OK == register_read_direct(target, &value, GDB_REGNO_S0),
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"Need to be able to read S0 to test ABSTRACTAUTO");
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@ -3367,24 +3358,24 @@ int riscv013_test_compliance(struct target *target)
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/* Single-Step each hart. */
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for (int hartsel = 0; hartsel < riscv_count_harts(target); hartsel++) {
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riscv_set_current_hartid(target, hartsel);
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riscv013_on_step(target);
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riscv013_step_current_hart(target);
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COMPLIANCE_TEST(riscv_halt_reason(target, hartsel) == RISCV_HALT_SINGLESTEP,
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COMPLIANCE_MUST_PASS(riscv_set_current_hartid(target, hartsel));
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COMPLIANCE_MUST_PASS(riscv013_on_step(target));
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COMPLIANCE_MUST_PASS(riscv013_step_current_hart(target));
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COMPLIANCE_TEST(riscv_halt_reason(target, hartsel) == RISCV_HALT_SINGLESTEP,
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"Single Step should result in SINGLESTEP");
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}
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||||
|
||||
/* Core Register Tests */
|
||||
uint64_t bogus_dpc = 0xdeadbeef;
|
||||
for (int hartsel = 0; hartsel < riscv_count_harts(target); hartsel++) {
|
||||
riscv_set_current_hartid(target, hartsel);
|
||||
COMPLIANCE_MUST_PASS(riscv_set_current_hartid(target, hartsel));
|
||||
|
||||
/* DCSR Tests */
|
||||
register_write_direct(target, GDB_REGNO_DCSR, 0x0);
|
||||
register_read_direct(target, &value, GDB_REGNO_DCSR);
|
||||
COMPLIANCE_MUST_PASS(register_write_direct(target, GDB_REGNO_DCSR, 0x0));
|
||||
COMPLIANCE_MUST_PASS(register_read_direct(target, &value, GDB_REGNO_DCSR));
|
||||
COMPLIANCE_TEST(value != 0, "Not all bits in DCSR are writable by Debugger");
|
||||
register_write_direct(target, GDB_REGNO_DCSR, 0xFFFFFFFF);
|
||||
register_read_direct(target, &value, GDB_REGNO_DCSR);
|
||||
COMPLIANCE_MUST_PASS(register_write_direct(target, GDB_REGNO_DCSR, 0xFFFFFFFF));
|
||||
COMPLIANCE_MUST_PASS(register_read_direct(target, &value, GDB_REGNO_DCSR));
|
||||
COMPLIANCE_TEST(value != 0, "At least some bits in DCSR must be 1");
|
||||
|
||||
/* DPC. Note that DPC is sign-extended. */
|
||||
|
|
@ -3397,12 +3388,12 @@ int riscv013_test_compliance(struct target *target)
|
|||
if (riscv_supports_extension(target, riscv_current_hartid(target), 'C'))
|
||||
dpcmask |= 0x2;
|
||||
|
||||
register_write_direct(target, GDB_REGNO_DPC, dpcmask);
|
||||
register_read_direct(target, &dpc, GDB_REGNO_DPC);
|
||||
COMPLIANCE_MUST_PASS(register_write_direct(target, GDB_REGNO_DPC, dpcmask));
|
||||
COMPLIANCE_MUST_PASS(register_read_direct(target, &dpc, GDB_REGNO_DPC));
|
||||
COMPLIANCE_TEST(dpcmask == dpc,
|
||||
"DPC must be sign-extended to XLEN and writable to all-1s (except the least significant bits)");
|
||||
register_write_direct(target, GDB_REGNO_DPC, 0);
|
||||
register_read_direct(target, &dpc, GDB_REGNO_DPC);
|
||||
COMPLIANCE_MUST_PASS(register_write_direct(target, GDB_REGNO_DPC, 0));
|
||||
COMPLIANCE_MUST_PASS(register_read_direct(target, &dpc, GDB_REGNO_DPC));
|
||||
COMPLIANCE_TEST(dpc == 0, "DPC must be writable to 0.");
|
||||
if (hartsel == 0)
|
||||
bogus_dpc = dpc; /* For a later test step */
|
||||
|
|
@ -3415,49 +3406,47 @@ int riscv013_test_compliance(struct target *target)
|
|||
*/
|
||||
|
||||
/* Write some registers. They should not be impacted by ndmreset. */
|
||||
dmi_write(target, DMI_COMMAND, 0xFFFFFFFF);
|
||||
COMPLIANCE_WRITE(target, DMI_COMMAND, 0xFFFFFFFF);
|
||||
|
||||
for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_PROGBUFSIZE); i++) {
|
||||
testvar = (i + 1) * 0x11111111;
|
||||
dmi_write(target, DMI_PROGBUF0 + i, testvar);
|
||||
COMPLIANCE_WRITE(target, DMI_PROGBUF0 + i, testvar);
|
||||
}
|
||||
|
||||
for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_DATACOUNT); i++) {
|
||||
testvar = (i + 1) * 0x11111111;
|
||||
dmi_write(target, DMI_DATA0 + i, testvar);
|
||||
COMPLIANCE_WRITE(target, DMI_DATA0 + i, testvar);
|
||||
}
|
||||
|
||||
dmi_write(target, DMI_ABSTRACTAUTO, 0xFFFFFFFF);
|
||||
dmi_read(target, &abstractauto, DMI_ABSTRACTAUTO);
|
||||
COMPLIANCE_WRITE(target, DMI_ABSTRACTAUTO, 0xFFFFFFFF);
|
||||
COMPLIANCE_READ(target, &abstractauto, DMI_ABSTRACTAUTO);
|
||||
|
||||
/* Pulse reset. */
|
||||
target->reset_halt = true;
|
||||
riscv_set_current_hartid(target, 0);
|
||||
COMPLIANCE_MUST_PASS(riscv_set_current_hartid(target, 0));
|
||||
COMPLIANCE_TEST(ERROR_OK == assert_reset(target), "Must be able to assert NDMRESET");
|
||||
COMPLIANCE_TEST(ERROR_OK == deassert_reset(target), "Must be able to deassert NDMRESET");
|
||||
|
||||
/* Verify that most stuff is not affected by ndmreset. */
|
||||
dmi_read(target, &testvar_read, DMI_COMMAND);
|
||||
COMPLIANCE_TEST(testvar_read == 0xFFFFFFFF, "NDMRESET should not affect DMI_COMMAND");
|
||||
dmi_read(target, &testvar_read, DMI_ABSTRACTCS);
|
||||
COMPLIANCE_READ(target, &testvar_read, DMI_ABSTRACTCS);
|
||||
COMPLIANCE_TEST(get_field(testvar_read, DMI_ABSTRACTCS_CMDERR) == CMDERR_NOT_SUPPORTED,
|
||||
"NDMRESET should not affect DMI_ABSTRACTCS");
|
||||
dmi_read(target, &testvar_read, DMI_ABSTRACTAUTO);
|
||||
COMPLIANCE_READ(target, &testvar_read, DMI_ABSTRACTAUTO);
|
||||
COMPLIANCE_TEST(testvar_read == abstractauto, "NDMRESET should not affect DMI_ABSTRACTAUTO");
|
||||
|
||||
/* Clean up to avoid future test failures */
|
||||
dmi_write(target, DMI_ABSTRACTCS, DMI_ABSTRACTCS_CMDERR);
|
||||
dmi_write(target, DMI_ABSTRACTAUTO, 0);
|
||||
COMPLIANCE_WRITE(target, DMI_ABSTRACTCS, DMI_ABSTRACTCS_CMDERR);
|
||||
COMPLIANCE_WRITE(target, DMI_ABSTRACTAUTO, 0);
|
||||
|
||||
for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_PROGBUFSIZE); i++) {
|
||||
testvar = (i + 1) * 0x11111111;
|
||||
dmi_read(target, &testvar_read, DMI_PROGBUF0 + i);
|
||||
COMPLIANCE_READ(target, &testvar_read, DMI_PROGBUF0 + i);
|
||||
COMPLIANCE_TEST(testvar_read == testvar, "PROGBUF words must not be affected by NDMRESET");
|
||||
}
|
||||
|
||||
for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_DATACOUNT); i++) {
|
||||
testvar = (i + 1) * 0x11111111;
|
||||
dmi_read(target, &testvar_read, DMI_DATA0 + i);
|
||||
COMPLIANCE_READ(target, &testvar_read, DMI_DATA0 + i);
|
||||
COMPLIANCE_TEST(testvar_read == testvar, "DATA words must not be affected by NDMRESET");
|
||||
}
|
||||
|
||||
|
|
@ -3465,7 +3454,7 @@ int riscv013_test_compliance(struct target *target)
|
|||
just verify that at least it's not the bogus value anymore. */
|
||||
|
||||
COMPLIANCE_TEST(bogus_dpc != 0xdeadbeef, "BOGUS DPC should have been set somehow (bug in compliance test)");
|
||||
register_read_direct(target, &value, GDB_REGNO_DPC);
|
||||
COMPLIANCE_MUST_PASS(register_read_direct(target, &value, GDB_REGNO_DPC));
|
||||
COMPLIANCE_TEST(bogus_dpc != value, "NDMRESET should move DPC to reset value.");
|
||||
|
||||
COMPLIANCE_TEST(riscv_halt_reason(target, 0) == RISCV_HALT_INTERRUPT,
|
||||
|
|
@ -3474,24 +3463,20 @@ int riscv013_test_compliance(struct target *target)
|
|||
/* DMACTIVE -- deasserting DMACTIVE should reset all the above values. */
|
||||
|
||||
/* Toggle dmactive */
|
||||
dmi_write(target, DMI_DMCONTROL, 0);
|
||||
dmi_write(target, DMI_DMCONTROL, DMI_DMCONTROL_DMACTIVE);
|
||||
dmi_read(target, &testvar_read, DMI_COMMAND);
|
||||
COMPLIANCE_TEST(testvar_read == 0, "DMI_COMMAND should reset to 0");
|
||||
dmi_read(target, &testvar_read, DMI_ABSTRACTCS);
|
||||
COMPLIANCE_WRITE(target, DMI_DMCONTROL, 0);
|
||||
COMPLIANCE_WRITE(target, DMI_DMCONTROL, DMI_DMCONTROL_DMACTIVE);
|
||||
COMPLIANCE_READ(target, &testvar_read, DMI_ABSTRACTCS);
|
||||
COMPLIANCE_TEST(get_field(testvar_read, DMI_ABSTRACTCS_CMDERR) == 0, "ABSTRACTCS.cmderr should reset to 0");
|
||||
dmi_read(target, &testvar_read, DMI_ABSTRACTAUTO);
|
||||
COMPLIANCE_READ(target, &testvar_read, DMI_ABSTRACTAUTO);
|
||||
COMPLIANCE_TEST(testvar_read == 0, "ABSTRACTAUTO should reset to 0");
|
||||
|
||||
for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_PROGBUFSIZE); i++) {
|
||||
testvar = (i + 1) * 0x11111111;
|
||||
dmi_read(target, &testvar_read, DMI_PROGBUF0 + i);
|
||||
COMPLIANCE_READ(target, &testvar_read, DMI_PROGBUF0 + i);
|
||||
COMPLIANCE_TEST(testvar_read == 0, "PROGBUF words should reset to 0");
|
||||
}
|
||||
|
||||
for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_DATACOUNT); i++) {
|
||||
testvar = (i + 1) * 0x11111111;
|
||||
dmi_read(target, &testvar_read, DMI_DATA0 + i);
|
||||
COMPLIANCE_READ(target, &testvar_read, DMI_DATA0 + i);
|
||||
COMPLIANCE_TEST(testvar_read == 0, "DATA words should reset to 0");
|
||||
}
|
||||
|
||||
|
|
@ -3505,7 +3490,7 @@ int riscv013_test_compliance(struct target *target)
|
|||
*/
|
||||
|
||||
/* Halt every hart for any follow-up tests*/
|
||||
riscv_halt_all_harts(target);
|
||||
COMPLIANCE_MUST_PASS(riscv_halt_all_harts(target));
|
||||
|
||||
LOG_INFO("PASSED %d of %d TESTS\n", passed_tests, total_tests);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue