Merge pull request #66 from riscv/whitespace
Fix indentation to match OpenOCD style.gitignore-build
commit
91c3dcc197
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@ -6,31 +6,31 @@
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/*** Version-independent functions that we don't want in the main address space. ***/
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/*** Version-independent functions that we don't want in the main address space. ***/
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static uint32_t load(const struct target *target, unsigned int rd,
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static uint32_t load(const struct target *target, unsigned int rd,
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unsigned int base, uint16_t offset) __attribute__ ((unused));
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unsigned int base, uint16_t offset) __attribute__ ((unused));
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static uint32_t load(const struct target *target, unsigned int rd,
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static uint32_t load(const struct target *target, unsigned int rd,
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unsigned int base, uint16_t offset)
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unsigned int base, uint16_t offset)
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{
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{
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switch (riscv_xlen(target)) {
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switch (riscv_xlen(target)) {
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case 32:
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case 32:
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return lw(rd, base, offset);
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return lw(rd, base, offset);
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case 64:
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case 64:
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return ld(rd, base, offset);
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return ld(rd, base, offset);
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}
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}
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assert(0);
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assert(0);
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}
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}
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static uint32_t store(const struct target *target, unsigned int src,
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static uint32_t store(const struct target *target, unsigned int src,
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unsigned int base, uint16_t offset) __attribute__ ((unused));
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unsigned int base, uint16_t offset) __attribute__ ((unused));
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static uint32_t store(const struct target *target, unsigned int src,
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static uint32_t store(const struct target *target, unsigned int src,
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unsigned int base, uint16_t offset)
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unsigned int base, uint16_t offset)
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{
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{
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switch (riscv_xlen(target)) {
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switch (riscv_xlen(target)) {
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case 32:
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case 32:
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return sw(src, base, offset);
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return sw(src, base, offset);
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case 64:
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case 64:
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return sd(src, base, offset);
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return sd(src, base, offset);
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}
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}
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assert(0);
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assert(0);
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}
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}
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#endif
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#endif
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@ -123,34 +123,34 @@ void riscv_batch_add_nop(struct riscv_batch *batch)
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void dump_field(const struct scan_field *field)
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void dump_field(const struct scan_field *field)
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{
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{
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static const char *op_string[] = {"-", "r", "w", "?"};
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static const char *op_string[] = {"-", "r", "w", "?"};
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static const char *status_string[] = {"+", "?", "F", "b"};
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static const char *status_string[] = {"+", "?", "F", "b"};
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if (debug_level < LOG_LVL_DEBUG)
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if (debug_level < LOG_LVL_DEBUG)
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return;
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return;
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assert(field->out_value != NULL);
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assert(field->out_value != NULL);
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uint64_t out = buf_get_u64(field->out_value, 0, field->num_bits);
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uint64_t out = buf_get_u64(field->out_value, 0, field->num_bits);
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unsigned int out_op = get_field(out, DTM_DMI_OP);
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unsigned int out_op = get_field(out, DTM_DMI_OP);
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unsigned int out_data = get_field(out, DTM_DMI_DATA);
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unsigned int out_data = get_field(out, DTM_DMI_DATA);
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unsigned int out_address = out >> DTM_DMI_ADDRESS_OFFSET;
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unsigned int out_address = out >> DTM_DMI_ADDRESS_OFFSET;
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if (field->in_value) {
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if (field->in_value) {
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uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
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uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
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unsigned int in_op = get_field(in, DTM_DMI_OP);
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unsigned int in_op = get_field(in, DTM_DMI_OP);
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unsigned int in_data = get_field(in, DTM_DMI_DATA);
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unsigned int in_data = get_field(in, DTM_DMI_DATA);
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unsigned int in_address = in >> DTM_DMI_ADDRESS_OFFSET;
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unsigned int in_address = in >> DTM_DMI_ADDRESS_OFFSET;
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log_printf_lf(LOG_LVL_DEBUG,
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log_printf_lf(LOG_LVL_DEBUG,
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__FILE__, __LINE__, __PRETTY_FUNCTION__,
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__FILE__, __LINE__, __PRETTY_FUNCTION__,
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"%db %s %08x @%02x -> %s %08x @%02x [0x%p -> 0x%p]",
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"%db %s %08x @%02x -> %s %08x @%02x [0x%p -> 0x%p]",
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field->num_bits,
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field->num_bits,
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op_string[out_op], out_data, out_address,
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op_string[out_op], out_data, out_address,
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status_string[in_op], in_data, in_address,
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status_string[in_op], in_data, in_address,
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field->out_value, field->in_value);
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field->out_value, field->in_value);
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} else {
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} else {
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log_printf_lf(LOG_LVL_DEBUG,
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log_printf_lf(LOG_LVL_DEBUG,
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__FILE__, __LINE__, __PRETTY_FUNCTION__, "%db %s %08x @%02x -> ?",
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__FILE__, __LINE__, __PRETTY_FUNCTION__, "%db %s %08x @%02x -> ?",
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field->num_bits, op_string[out_op], out_data, out_address);
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field->num_bits, op_string[out_op], out_data, out_address);
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}
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}
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}
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}
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@ -2,27 +2,27 @@
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#define TARGET__RISCV__GDB_REGS_H
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#define TARGET__RISCV__GDB_REGS_H
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enum gdb_regno {
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enum gdb_regno {
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GDB_REGNO_XPR0 = 0,
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GDB_REGNO_XPR0 = 0,
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GDB_REGNO_X0 = GDB_REGNO_XPR0 + 0,
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GDB_REGNO_X0 = GDB_REGNO_XPR0 + 0,
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GDB_REGNO_ZERO = GDB_REGNO_XPR0 + 0,
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GDB_REGNO_ZERO = GDB_REGNO_XPR0 + 0,
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GDB_REGNO_S0 = GDB_REGNO_XPR0 + 8,
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GDB_REGNO_S0 = GDB_REGNO_XPR0 + 8,
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GDB_REGNO_S1 = GDB_REGNO_XPR0 + 9,
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GDB_REGNO_S1 = GDB_REGNO_XPR0 + 9,
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GDB_REGNO_XPR31 = GDB_REGNO_XPR0 + 31,
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GDB_REGNO_XPR31 = GDB_REGNO_XPR0 + 31,
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GDB_REGNO_PC = 32,
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GDB_REGNO_PC = 32,
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GDB_REGNO_FPR0 = 33,
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GDB_REGNO_FPR0 = 33,
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GDB_REGNO_FPR31 = GDB_REGNO_FPR0 + 31,
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GDB_REGNO_FPR31 = GDB_REGNO_FPR0 + 31,
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GDB_REGNO_CSR0 = 65,
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GDB_REGNO_CSR0 = 65,
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GDB_REGNO_TSELECT = CSR_TSELECT + GDB_REGNO_CSR0,
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GDB_REGNO_TSELECT = CSR_TSELECT + GDB_REGNO_CSR0,
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GDB_REGNO_TDATA1 = CSR_TDATA1 + GDB_REGNO_CSR0,
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GDB_REGNO_TDATA1 = CSR_TDATA1 + GDB_REGNO_CSR0,
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GDB_REGNO_TDATA2 = CSR_TDATA2 + GDB_REGNO_CSR0,
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GDB_REGNO_TDATA2 = CSR_TDATA2 + GDB_REGNO_CSR0,
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GDB_REGNO_MISA = CSR_MISA + GDB_REGNO_CSR0,
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GDB_REGNO_MISA = CSR_MISA + GDB_REGNO_CSR0,
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GDB_REGNO_DPC = CSR_DPC + GDB_REGNO_CSR0,
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GDB_REGNO_DPC = CSR_DPC + GDB_REGNO_CSR0,
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GDB_REGNO_DCSR = CSR_DCSR + GDB_REGNO_CSR0,
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GDB_REGNO_DCSR = CSR_DCSR + GDB_REGNO_CSR0,
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GDB_REGNO_DSCRATCH = CSR_DSCRATCH + GDB_REGNO_CSR0,
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GDB_REGNO_DSCRATCH = CSR_DSCRATCH + GDB_REGNO_CSR0,
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GDB_REGNO_MSTATUS = CSR_MSTATUS + GDB_REGNO_CSR0,
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GDB_REGNO_MSTATUS = CSR_MSTATUS + GDB_REGNO_CSR0,
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GDB_REGNO_CSR4095 = GDB_REGNO_CSR0 + 4095,
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GDB_REGNO_CSR4095 = GDB_REGNO_CSR0 + 4095,
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GDB_REGNO_PRIV = 4161,
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GDB_REGNO_PRIV = 4161,
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GDB_REGNO_COUNT
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GDB_REGNO_COUNT
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};
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};
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#endif
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#endif
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@ -6,203 +6,203 @@
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#define S1 9
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#define S1 9
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static uint32_t bits(uint32_t value, unsigned int hi, unsigned int lo) {
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static uint32_t bits(uint32_t value, unsigned int hi, unsigned int lo) {
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return (value >> lo) & ((1 << (hi+1-lo)) - 1);
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return (value >> lo) & ((1 << (hi+1-lo)) - 1);
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}
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}
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static uint32_t bit(uint32_t value, unsigned int b) {
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static uint32_t bit(uint32_t value, unsigned int b) {
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return (value >> b) & 1;
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return (value >> b) & 1;
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}
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}
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static uint32_t jal(unsigned int rd, uint32_t imm) __attribute__ ((unused));
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static uint32_t jal(unsigned int rd, uint32_t imm) __attribute__ ((unused));
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static uint32_t jal(unsigned int rd, uint32_t imm) {
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static uint32_t jal(unsigned int rd, uint32_t imm) {
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return (bit(imm, 20) << 31) |
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return (bit(imm, 20) << 31) |
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(bits(imm, 10, 1) << 21) |
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(bits(imm, 10, 1) << 21) |
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(bit(imm, 11) << 20) |
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(bit(imm, 11) << 20) |
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(bits(imm, 19, 12) << 12) |
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(bits(imm, 19, 12) << 12) |
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(rd << 7) |
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(rd << 7) |
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MATCH_JAL;
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MATCH_JAL;
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}
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}
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static uint32_t csrsi(unsigned int csr, uint16_t imm) __attribute__ ((unused));
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static uint32_t csrsi(unsigned int csr, uint16_t imm) __attribute__ ((unused));
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static uint32_t csrsi(unsigned int csr, uint16_t imm) {
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static uint32_t csrsi(unsigned int csr, uint16_t imm) {
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return (csr << 20) |
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return (csr << 20) |
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(bits(imm, 4, 0) << 15) |
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(bits(imm, 4, 0) << 15) |
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MATCH_CSRRSI;
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MATCH_CSRRSI;
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}
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}
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static uint32_t sw(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused));
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static uint32_t sw(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused));
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static uint32_t sw(unsigned int src, unsigned int base, uint16_t offset)
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static uint32_t sw(unsigned int src, unsigned int base, uint16_t offset)
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{
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{
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return (bits(offset, 11, 5) << 25) |
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return (bits(offset, 11, 5) << 25) |
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(src << 20) |
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(src << 20) |
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(base << 15) |
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(base << 15) |
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(bits(offset, 4, 0) << 7) |
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(bits(offset, 4, 0) << 7) |
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MATCH_SW;
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MATCH_SW;
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}
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}
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static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused));
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static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused));
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static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset)
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static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset)
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{
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{
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return (bits(offset, 11, 5) << 25) |
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return (bits(offset, 11, 5) << 25) |
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(src << 20) |
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(src << 20) |
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(base << 15) |
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(base << 15) |
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(bits(offset, 4, 0) << 7) |
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(bits(offset, 4, 0) << 7) |
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MATCH_SD;
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MATCH_SD;
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}
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}
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static uint32_t sh(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused));
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static uint32_t sh(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused));
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static uint32_t sh(unsigned int src, unsigned int base, uint16_t offset)
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static uint32_t sh(unsigned int src, unsigned int base, uint16_t offset)
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{
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{
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return (bits(offset, 11, 5) << 25) |
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return (bits(offset, 11, 5) << 25) |
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(src << 20) |
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(src << 20) |
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(base << 15) |
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(base << 15) |
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(bits(offset, 4, 0) << 7) |
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(bits(offset, 4, 0) << 7) |
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MATCH_SH;
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MATCH_SH;
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}
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}
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static uint32_t sb(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused));
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static uint32_t sb(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused));
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static uint32_t sb(unsigned int src, unsigned int base, uint16_t offset)
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static uint32_t sb(unsigned int src, unsigned int base, uint16_t offset)
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{
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{
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return (bits(offset, 11, 5) << 25) |
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return (bits(offset, 11, 5) << 25) |
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(src << 20) |
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(src << 20) |
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(base << 15) |
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(base << 15) |
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(bits(offset, 4, 0) << 7) |
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(bits(offset, 4, 0) << 7) |
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MATCH_SB;
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MATCH_SB;
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}
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}
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static uint32_t ld(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused));
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static uint32_t ld(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused));
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static uint32_t ld(unsigned int rd, unsigned int base, uint16_t offset)
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static uint32_t ld(unsigned int rd, unsigned int base, uint16_t offset)
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{
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{
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return (bits(offset, 11, 0) << 20) |
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return (bits(offset, 11, 0) << 20) |
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(base << 15) |
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(base << 15) |
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(bits(rd, 4, 0) << 7) |
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(bits(rd, 4, 0) << 7) |
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MATCH_LD;
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MATCH_LD;
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}
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}
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static uint32_t lw(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused));
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static uint32_t lw(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused));
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static uint32_t lw(unsigned int rd, unsigned int base, uint16_t offset)
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static uint32_t lw(unsigned int rd, unsigned int base, uint16_t offset)
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{
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{
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return (bits(offset, 11, 0) << 20) |
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return (bits(offset, 11, 0) << 20) |
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(base << 15) |
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(base << 15) |
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(bits(rd, 4, 0) << 7) |
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(bits(rd, 4, 0) << 7) |
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MATCH_LW;
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MATCH_LW;
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}
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}
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static uint32_t lh(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused));
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static uint32_t lh(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused));
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static uint32_t lh(unsigned int rd, unsigned int base, uint16_t offset)
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static uint32_t lh(unsigned int rd, unsigned int base, uint16_t offset)
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{
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{
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return (bits(offset, 11, 0) << 20) |
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return (bits(offset, 11, 0) << 20) |
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(base << 15) |
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(base << 15) |
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(bits(rd, 4, 0) << 7) |
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(bits(rd, 4, 0) << 7) |
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MATCH_LH;
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MATCH_LH;
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}
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}
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static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused));
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static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused));
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static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset)
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static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset)
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{
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{
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return (bits(offset, 11, 0) << 20) |
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return (bits(offset, 11, 0) << 20) |
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(base << 15) |
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(base << 15) |
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(bits(rd, 4, 0) << 7) |
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(bits(rd, 4, 0) << 7) |
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MATCH_LB;
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MATCH_LB;
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}
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}
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||||||
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static uint32_t csrw(unsigned int source, unsigned int csr) __attribute__ ((unused));
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static uint32_t csrw(unsigned int source, unsigned int csr) __attribute__ ((unused));
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static uint32_t csrw(unsigned int source, unsigned int csr) {
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static uint32_t csrw(unsigned int source, unsigned int csr) {
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return (csr << 20) | (source << 15) | MATCH_CSRRW;
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return (csr << 20) | (source << 15) | MATCH_CSRRW;
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}
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}
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|
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static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm) __attribute__ ((unused));
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static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm) __attribute__ ((unused));
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static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm)
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static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm)
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{
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{
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return (bits(imm, 11, 0) << 20) |
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return (bits(imm, 11, 0) << 20) |
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(src << 15) |
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(src << 15) |
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(dest << 7) |
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(dest << 7) |
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MATCH_ADDI;
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MATCH_ADDI;
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||||||
}
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}
|
||||||
|
|
||||||
static uint32_t csrr(unsigned int rd, unsigned int csr) __attribute__ ((unused));
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static uint32_t csrr(unsigned int rd, unsigned int csr) __attribute__ ((unused));
|
||||||
static uint32_t csrr(unsigned int rd, unsigned int csr) {
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static uint32_t csrr(unsigned int rd, unsigned int csr) {
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return (csr << 20) | (rd << 7) | MATCH_CSRRS;
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return (csr << 20) | (rd << 7) | MATCH_CSRRS;
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||||||
}
|
}
|
||||||
|
|
||||||
static uint32_t csrrs(unsigned int rd, unsigned int rs, unsigned int csr) __attribute__ ((unused));
|
static uint32_t csrrs(unsigned int rd, unsigned int rs, unsigned int csr) __attribute__ ((unused));
|
||||||
static uint32_t csrrs(unsigned int rd, unsigned int rs, unsigned int csr) {
|
static uint32_t csrrs(unsigned int rd, unsigned int rs, unsigned int csr) {
|
||||||
return (csr << 20) | (rs << 15) | (rd << 7) | MATCH_CSRRS;
|
return (csr << 20) | (rs << 15) | (rd << 7) | MATCH_CSRRS;
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint32_t csrrw(unsigned int rd, unsigned int rs, unsigned int csr) __attribute__ ((unused));
|
static uint32_t csrrw(unsigned int rd, unsigned int rs, unsigned int csr) __attribute__ ((unused));
|
||||||
static uint32_t csrrw(unsigned int rd, unsigned int rs, unsigned int csr) {
|
static uint32_t csrrw(unsigned int rd, unsigned int rs, unsigned int csr) {
|
||||||
return (csr << 20) | (rs << 15) | (rd << 7) | MATCH_CSRRW;
|
return (csr << 20) | (rs << 15) | (rd << 7) | MATCH_CSRRW;
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused));
|
static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused));
|
||||||
static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset)
|
static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset)
|
||||||
{
|
{
|
||||||
return (bits(offset, 11, 5) << 25) |
|
return (bits(offset, 11, 5) << 25) |
|
||||||
(bits(src, 4, 0) << 20) |
|
(bits(src, 4, 0) << 20) |
|
||||||
(base << 15) |
|
(base << 15) |
|
||||||
(bits(offset, 4, 0) << 7) |
|
(bits(offset, 4, 0) << 7) |
|
||||||
MATCH_FSW;
|
MATCH_FSW;
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused));
|
static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused));
|
||||||
static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset)
|
static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset)
|
||||||
{
|
{
|
||||||
return (bits(offset, 11, 5) << 25) |
|
return (bits(offset, 11, 5) << 25) |
|
||||||
(bits(src, 4, 0) << 20) |
|
(bits(src, 4, 0) << 20) |
|
||||||
(base << 15) |
|
(base << 15) |
|
||||||
(bits(offset, 4, 0) << 7) |
|
(bits(offset, 4, 0) << 7) |
|
||||||
MATCH_FSD;
|
MATCH_FSD;
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint32_t flw(unsigned int dest, unsigned int base, uint16_t offset) __attribute__ ((unused));
|
static uint32_t flw(unsigned int dest, unsigned int base, uint16_t offset) __attribute__ ((unused));
|
||||||
static uint32_t flw(unsigned int dest, unsigned int base, uint16_t offset)
|
static uint32_t flw(unsigned int dest, unsigned int base, uint16_t offset)
|
||||||
{
|
{
|
||||||
return (bits(offset, 11, 0) << 20) |
|
return (bits(offset, 11, 0) << 20) |
|
||||||
(base << 15) |
|
(base << 15) |
|
||||||
(bits(dest, 4, 0) << 7) |
|
(bits(dest, 4, 0) << 7) |
|
||||||
MATCH_FLW;
|
MATCH_FLW;
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint32_t fld(unsigned int dest, unsigned int base, uint16_t offset) __attribute__ ((unused));
|
static uint32_t fld(unsigned int dest, unsigned int base, uint16_t offset) __attribute__ ((unused));
|
||||||
static uint32_t fld(unsigned int dest, unsigned int base, uint16_t offset)
|
static uint32_t fld(unsigned int dest, unsigned int base, uint16_t offset)
|
||||||
{
|
{
|
||||||
return (bits(offset, 11, 0) << 20) |
|
return (bits(offset, 11, 0) << 20) |
|
||||||
(base << 15) |
|
(base << 15) |
|
||||||
(bits(dest, 4, 0) << 7) |
|
(bits(dest, 4, 0) << 7) |
|
||||||
MATCH_FLD;
|
MATCH_FLD;
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint32_t fmv_x_s(unsigned dest, unsigned src) __attribute__ ((unused));
|
static uint32_t fmv_x_s(unsigned dest, unsigned src) __attribute__ ((unused));
|
||||||
static uint32_t fmv_x_s(unsigned dest, unsigned src)
|
static uint32_t fmv_x_s(unsigned dest, unsigned src)
|
||||||
{
|
{
|
||||||
return src << 15 |
|
return src << 15 |
|
||||||
dest << 7 |
|
dest << 7 |
|
||||||
MATCH_FMV_X_S;
|
MATCH_FMV_X_S;
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint32_t fmv_x_d(unsigned dest, unsigned src) __attribute__ ((unused));
|
static uint32_t fmv_x_d(unsigned dest, unsigned src) __attribute__ ((unused));
|
||||||
static uint32_t fmv_x_d(unsigned dest, unsigned src)
|
static uint32_t fmv_x_d(unsigned dest, unsigned src)
|
||||||
{
|
{
|
||||||
return src << 15 |
|
return src << 15 |
|
||||||
dest << 7 |
|
dest << 7 |
|
||||||
MATCH_FMV_X_D;
|
MATCH_FMV_X_D;
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint32_t fmv_s_x(unsigned dest, unsigned src) __attribute__ ((unused));
|
static uint32_t fmv_s_x(unsigned dest, unsigned src) __attribute__ ((unused));
|
||||||
static uint32_t fmv_s_x(unsigned dest, unsigned src)
|
static uint32_t fmv_s_x(unsigned dest, unsigned src)
|
||||||
{
|
{
|
||||||
return src << 15 |
|
return src << 15 |
|
||||||
dest << 7 |
|
dest << 7 |
|
||||||
MATCH_FMV_S_X;
|
MATCH_FMV_S_X;
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint32_t fmv_d_x(unsigned dest, unsigned src) __attribute__ ((unused));
|
static uint32_t fmv_d_x(unsigned dest, unsigned src) __attribute__ ((unused));
|
||||||
static uint32_t fmv_d_x(unsigned dest, unsigned src)
|
static uint32_t fmv_d_x(unsigned dest, unsigned src)
|
||||||
{
|
{
|
||||||
return src << 15 |
|
return src << 15 |
|
||||||
dest << 7 |
|
dest << 7 |
|
||||||
MATCH_FMV_D_X;
|
MATCH_FMV_D_X;
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint32_t ebreak(void) __attribute__ ((unused));
|
static uint32_t ebreak(void) __attribute__ ((unused));
|
||||||
|
@ -213,15 +213,15 @@ static uint32_t ebreak_c(void) { return MATCH_C_EBREAK; }
|
||||||
static uint32_t fence_i(void) __attribute__ ((unused));
|
static uint32_t fence_i(void) __attribute__ ((unused));
|
||||||
static uint32_t fence_i(void)
|
static uint32_t fence_i(void)
|
||||||
{
|
{
|
||||||
return MATCH_FENCE_I;
|
return MATCH_FENCE_I;
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint32_t lui(unsigned int dest, uint32_t imm) __attribute__ ((unused));
|
static uint32_t lui(unsigned int dest, uint32_t imm) __attribute__ ((unused));
|
||||||
static uint32_t lui(unsigned int dest, uint32_t imm)
|
static uint32_t lui(unsigned int dest, uint32_t imm)
|
||||||
{
|
{
|
||||||
return (bits(imm, 19, 0) << 12) |
|
return (bits(imm, 19, 0) << 12) |
|
||||||
(dest << 7) |
|
(dest << 7) |
|
||||||
MATCH_LUI;
|
MATCH_LUI;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -267,10 +267,10 @@ static uint32_t nop(void)
|
||||||
static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm) __attribute__ ((unused));
|
static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm) __attribute__ ((unused));
|
||||||
static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm)
|
static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm)
|
||||||
{
|
{
|
||||||
return (bits(imm, 11, 0) << 20) |
|
return (bits(imm, 11, 0) << 20) |
|
||||||
(src << 15) |
|
(src << 15) |
|
||||||
(dest << 7) |
|
(dest << 7) |
|
||||||
MATCH_XORI;
|
MATCH_XORI;
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint32_t srli(unsigned int dest, unsigned int src, uint8_t shamt) __attribute__ ((unused));
|
static uint32_t srli(unsigned int dest, unsigned int src, uint8_t shamt) __attribute__ ((unused));
|
||||||
|
|
|
@ -201,17 +201,17 @@ static void dump_field(const struct scan_field *field)
|
||||||
unsigned int out_data = get_field(out, DTM_DMI_DATA);
|
unsigned int out_data = get_field(out, DTM_DMI_DATA);
|
||||||
unsigned int out_address = out >> DTM_DMI_ADDRESS_OFFSET;
|
unsigned int out_address = out >> DTM_DMI_ADDRESS_OFFSET;
|
||||||
|
|
||||||
uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
|
uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
|
||||||
unsigned int in_op = get_field(in, DTM_DMI_OP);
|
unsigned int in_op = get_field(in, DTM_DMI_OP);
|
||||||
unsigned int in_data = get_field(in, DTM_DMI_DATA);
|
unsigned int in_data = get_field(in, DTM_DMI_DATA);
|
||||||
unsigned int in_address = in >> DTM_DMI_ADDRESS_OFFSET;
|
unsigned int in_address = in >> DTM_DMI_ADDRESS_OFFSET;
|
||||||
|
|
||||||
log_printf_lf(LOG_LVL_DEBUG,
|
log_printf_lf(LOG_LVL_DEBUG,
|
||||||
__FILE__, __LINE__, "scan",
|
__FILE__, __LINE__, "scan",
|
||||||
"%db %s %08x @%02x -> %s %08x @%02x",
|
"%db %s %08x @%02x -> %s %08x @%02x",
|
||||||
field->num_bits,
|
field->num_bits,
|
||||||
op_string[out_op], out_data, out_address,
|
op_string[out_op], out_data, out_address,
|
||||||
status_string[in_op], in_data, in_address);
|
status_string[in_op], in_data, in_address);
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -321,7 +321,7 @@ static dmi_status_t dmi_scan(struct target *target, uint16_t *address_in,
|
||||||
struct scan_field field = {
|
struct scan_field field = {
|
||||||
.num_bits = info->abits + DTM_DMI_OP_LENGTH + DTM_DMI_DATA_LENGTH,
|
.num_bits = info->abits + DTM_DMI_OP_LENGTH + DTM_DMI_DATA_LENGTH,
|
||||||
.out_value = out,
|
.out_value = out,
|
||||||
.in_value = in
|
.in_value = in
|
||||||
};
|
};
|
||||||
|
|
||||||
assert(info->abits != 0);
|
assert(info->abits != 0);
|
||||||
|
@ -375,7 +375,7 @@ static uint64_t dmi_read(struct target *target, uint16_t address)
|
||||||
// it is actually due to the Previous dmi_read or dmi_write.
|
// it is actually due to the Previous dmi_read or dmi_write.
|
||||||
for (i = 0; i < 256; i++) {
|
for (i = 0; i < 256; i++) {
|
||||||
status = dmi_scan(target, NULL, NULL, DMI_OP_READ, address, 0,
|
status = dmi_scan(target, NULL, NULL, DMI_OP_READ, address, 0,
|
||||||
false);
|
false);
|
||||||
if (status == DMI_STATUS_BUSY) {
|
if (status == DMI_STATUS_BUSY) {
|
||||||
increase_dmi_busy_delay(target);
|
increase_dmi_busy_delay(target);
|
||||||
} else if (status == DMI_STATUS_SUCCESS) {
|
} else if (status == DMI_STATUS_SUCCESS) {
|
||||||
|
@ -423,39 +423,39 @@ static void dmi_write(struct target *target, uint16_t address, uint64_t value)
|
||||||
dmi_status_t status = DMI_STATUS_BUSY;
|
dmi_status_t status = DMI_STATUS_BUSY;
|
||||||
unsigned i = 0;
|
unsigned i = 0;
|
||||||
|
|
||||||
// The first loop ensures that we successfully sent the write request.
|
// The first loop ensures that we successfully sent the write request.
|
||||||
for (i = 0; i < 256; i++) {
|
for (i = 0; i < 256; i++) {
|
||||||
status = dmi_scan(target, NULL, NULL, DMI_OP_WRITE, address, value,
|
status = dmi_scan(target, NULL, NULL, DMI_OP_WRITE, address, value,
|
||||||
address == DMI_COMMAND);
|
address == DMI_COMMAND);
|
||||||
if (status == DMI_STATUS_BUSY) {
|
if (status == DMI_STATUS_BUSY) {
|
||||||
increase_dmi_busy_delay(target);
|
increase_dmi_busy_delay(target);
|
||||||
} else if (status == DMI_STATUS_SUCCESS) {
|
} else if (status == DMI_STATUS_SUCCESS) {
|
||||||
break;
|
break;
|
||||||
} else {
|
} else {
|
||||||
LOG_ERROR("failed write to 0x%x, status=%d\n", address, status);
|
LOG_ERROR("failed write to 0x%x, status=%d\n", address, status);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if (status != DMI_STATUS_SUCCESS) {
|
if (status != DMI_STATUS_SUCCESS) {
|
||||||
LOG_ERROR("Failed write to 0x%x;, status=%d\n",
|
LOG_ERROR("Failed write to 0x%x;, status=%d\n",
|
||||||
address, status);
|
address, status);
|
||||||
abort();
|
abort();
|
||||||
}
|
}
|
||||||
|
|
||||||
// The second loop isn't strictly necessary, but would ensure that
|
// The second loop isn't strictly necessary, but would ensure that
|
||||||
// the write is complete/ has no non-busy errors before returning from this function.
|
// the write is complete/ has no non-busy errors before returning from this function.
|
||||||
for (i = 0; i < 256; i++) {
|
for (i = 0; i < 256; i++) {
|
||||||
status = dmi_scan(target, NULL, NULL, DMI_OP_NOP, address, 0,
|
status = dmi_scan(target, NULL, NULL, DMI_OP_NOP, address, 0,
|
||||||
false);
|
false);
|
||||||
if (status == DMI_STATUS_BUSY) {
|
if (status == DMI_STATUS_BUSY) {
|
||||||
increase_dmi_busy_delay(target);
|
increase_dmi_busy_delay(target);
|
||||||
} else if (status == DMI_STATUS_SUCCESS) {
|
} else if (status == DMI_STATUS_SUCCESS) {
|
||||||
break;
|
break;
|
||||||
} else {
|
} else {
|
||||||
LOG_ERROR("failed write (NOP) at 0x%x, status=%d\n", address, status);
|
LOG_ERROR("failed write (NOP) at 0x%x, status=%d\n", address, status);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if (status != DMI_STATUS_SUCCESS) {
|
if (status != DMI_STATUS_SUCCESS) {
|
||||||
LOG_ERROR("failed to write (NOP) 0x%" PRIx64 " to 0x%x; status=%d\n", value, address, status);
|
LOG_ERROR("failed to write (NOP) 0x%" PRIx64 " to 0x%x; status=%d\n", value, address, status);
|
||||||
|
@ -1101,10 +1101,10 @@ static int examine(struct target *target)
|
||||||
LOG_DEBUG("found program buffer at 0x%08lx", (long)(r->debug_buffer_addr[i]));
|
LOG_DEBUG("found program buffer at 0x%08lx", (long)(r->debug_buffer_addr[i]));
|
||||||
|
|
||||||
if (riscv_program_gah(&program64, r->debug_buffer_addr[i])) {
|
if (riscv_program_gah(&program64, r->debug_buffer_addr[i])) {
|
||||||
LOG_ERROR("This implementation will not work with hart %d with debug_buffer_addr of 0x%lx\n", i,
|
LOG_ERROR("This implementation will not work with hart %d with debug_buffer_addr of 0x%lx\n", i,
|
||||||
(long)r->debug_buffer_addr[i]);
|
(long)r->debug_buffer_addr[i]);
|
||||||
abort();
|
abort();
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Check to see if we can use the data words as an extended
|
/* Check to see if we can use the data words as an extended
|
||||||
* program buffer or not. */
|
* program buffer or not. */
|
||||||
|
@ -1132,79 +1132,77 @@ static int examine(struct target *target)
|
||||||
riscv_resume_all_harts(target);
|
riscv_resume_all_harts(target);
|
||||||
target_set_examined(target);
|
target_set_examined(target);
|
||||||
|
|
||||||
// This print is used by some regression suites to know when
|
// This print is used by some regression suites to know when
|
||||||
// they can connect with gdb/telnet.
|
// they can connect with gdb/telnet.
|
||||||
// We will need to update those suites if we want to remove this line.
|
// We will need to update those suites if we want to remove this line.
|
||||||
LOG_INFO("Examined RISC-V core");
|
LOG_INFO("Examined RISC-V core");
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int assert_reset(struct target *target)
|
static int assert_reset(struct target *target)
|
||||||
{
|
{
|
||||||
/*FIXME -- this only works for single-hart.*/
|
/*FIXME -- this only works for single-hart.*/
|
||||||
RISCV_INFO(r);
|
RISCV_INFO(r);
|
||||||
assert(r->current_hartid == 0);
|
assert(r->current_hartid == 0);
|
||||||
|
|
||||||
select_dmi(target);
|
select_dmi(target);
|
||||||
LOG_DEBUG("ASSERTING NDRESET");
|
LOG_DEBUG("ASSERTING NDRESET");
|
||||||
uint32_t control = dmi_read(target, DMI_DMCONTROL);
|
uint32_t control = dmi_read(target, DMI_DMCONTROL);
|
||||||
control = set_field(control, DMI_DMCONTROL_NDMRESET, 1);
|
control = set_field(control, DMI_DMCONTROL_NDMRESET, 1);
|
||||||
if (target->reset_halt) {
|
if (target->reset_halt) {
|
||||||
LOG_DEBUG("TARGET RESET HALT SET, ensuring halt is set during reset.");
|
LOG_DEBUG("TARGET RESET HALT SET, ensuring halt is set during reset.");
|
||||||
control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);
|
control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);
|
||||||
} else {
|
} else {
|
||||||
LOG_DEBUG("TARGET RESET HALT NOT SET");
|
LOG_DEBUG("TARGET RESET HALT NOT SET");
|
||||||
control = set_field(control, DMI_DMCONTROL_HALTREQ, 0);
|
control = set_field(control, DMI_DMCONTROL_HALTREQ, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
dmi_write(target, DMI_DMCONTROL,
|
dmi_write(target, DMI_DMCONTROL, control);
|
||||||
control);
|
|
||||||
|
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int deassert_reset(struct target *target)
|
static int deassert_reset(struct target *target)
|
||||||
{
|
{
|
||||||
RISCV_INFO(r);
|
RISCV_INFO(r);
|
||||||
RISCV013_INFO(info);
|
RISCV013_INFO(info);
|
||||||
|
select_dmi(target);
|
||||||
|
|
||||||
select_dmi(target);
|
/*FIXME -- this only works for Single Hart*/
|
||||||
|
assert(r->current_hartid == 0);
|
||||||
|
|
||||||
/*FIXME -- this only works for Single Hart*/
|
/*FIXME -- is there bookkeeping we need to do here*/
|
||||||
assert(r->current_hartid == 0);
|
|
||||||
|
|
||||||
/*FIXME -- is there bookkeeping we need to do here*/
|
uint32_t control = dmi_read(target, DMI_DMCONTROL);
|
||||||
|
|
||||||
uint32_t control = dmi_read(target, DMI_DMCONTROL);
|
// Clear the reset, but make sure haltreq is still set
|
||||||
|
if (target->reset_halt) {
|
||||||
|
control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);
|
||||||
|
}
|
||||||
|
|
||||||
// Clear the reset, but make sure haltreq is still set
|
control = set_field(control, DMI_DMCONTROL_NDMRESET, 0);
|
||||||
if (target->reset_halt) {
|
dmi_write(target, DMI_DMCONTROL, control);
|
||||||
control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);
|
|
||||||
}
|
|
||||||
|
|
||||||
control = set_field(control, DMI_DMCONTROL_NDMRESET, 0);
|
uint32_t status;
|
||||||
dmi_write(target, DMI_DMCONTROL, control);
|
int dmi_busy_delay = info->dmi_busy_delay;
|
||||||
|
if (target->reset_halt) {
|
||||||
uint32_t status;
|
LOG_DEBUG("DEASSERTING RESET, waiting for hart to be halted.");
|
||||||
int dmi_busy_delay = info->dmi_busy_delay;
|
do {
|
||||||
if (target->reset_halt) {
|
status = dmi_read(target, DMI_DMSTATUS);
|
||||||
LOG_DEBUG("DEASSERTING RESET, waiting for hart to be halted.");
|
} while (get_field(status, DMI_DMSTATUS_ALLHALTED) == 0);
|
||||||
do {
|
} else {
|
||||||
status = dmi_read(target, DMI_DMSTATUS);
|
LOG_DEBUG("DEASSERTING RESET, waiting for hart to be running.");
|
||||||
} while (get_field(status, DMI_DMSTATUS_ALLHALTED) == 0);
|
do {
|
||||||
} else {
|
status = dmi_read(target, DMI_DMSTATUS);
|
||||||
LOG_DEBUG("DEASSERTING RESET, waiting for hart to be running.");
|
if (get_field(status, DMI_DMSTATUS_ANYHALTED) ||
|
||||||
do {
|
get_field(status, DMI_DMSTATUS_ANYUNAVAIL)) {
|
||||||
status = dmi_read(target, DMI_DMSTATUS);
|
LOG_ERROR("Unexpected hart status during reset.");
|
||||||
if (get_field(status, DMI_DMSTATUS_ANYHALTED) ||
|
abort();
|
||||||
get_field(status, DMI_DMSTATUS_ANYUNAVAIL)) {
|
}
|
||||||
LOG_ERROR("Unexpected hart status during reset.");
|
} while (get_field(status, DMI_DMSTATUS_ALLRUNNING) == 0);
|
||||||
abort();
|
}
|
||||||
}
|
info->dmi_busy_delay = dmi_busy_delay;
|
||||||
} while (get_field(status, DMI_DMSTATUS_ALLRUNNING) == 0);
|
return ERROR_OK;
|
||||||
}
|
|
||||||
info->dmi_busy_delay = dmi_busy_delay;
|
|
||||||
return ERROR_OK;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int read_memory(struct target *target, target_addr_t address,
|
static int read_memory(struct target *target, target_addr_t address,
|
||||||
|
@ -1317,8 +1315,8 @@ static int read_memory(struct target *target, target_addr_t address,
|
||||||
assert(prev_addr < cur_addr);
|
assert(prev_addr < cur_addr);
|
||||||
prev_addr = cur_addr;
|
prev_addr = cur_addr;
|
||||||
riscv_addr_t start = (cur_addr - address) / size;
|
riscv_addr_t start = (cur_addr - address) / size;
|
||||||
assert (cur_addr >= address);
|
assert (cur_addr >= address);
|
||||||
struct riscv_batch *batch = riscv_batch_alloc(
|
struct riscv_batch *batch = riscv_batch_alloc(
|
||||||
target,
|
target,
|
||||||
32,
|
32,
|
||||||
info->dmi_busy_delay + info->ac_busy_delay);
|
info->dmi_busy_delay + info->ac_busy_delay);
|
||||||
|
@ -1371,10 +1369,10 @@ static int read_memory(struct target *target, target_addr_t address,
|
||||||
|
|
||||||
riscv_batch_free(batch);
|
riscv_batch_free(batch);
|
||||||
|
|
||||||
// Note that if the scan resulted in a Busy DMI response, it
|
// Note that if the scan resulted in a Busy DMI response, it
|
||||||
// is this read to abstractcs that will cause the dmi_busy_delay
|
// is this read to abstractcs that will cause the dmi_busy_delay
|
||||||
// to be incremented if necessary. The loop condition above
|
// to be incremented if necessary. The loop condition above
|
||||||
// catches the case where no writes went through at all.
|
// catches the case where no writes went through at all.
|
||||||
|
|
||||||
uint32_t abstractcs = dmi_read(target, DMI_ABSTRACTCS);
|
uint32_t abstractcs = dmi_read(target, DMI_ABSTRACTCS);
|
||||||
while (get_field(abstractcs, DMI_ABSTRACTCS_BUSY))
|
while (get_field(abstractcs, DMI_ABSTRACTCS_BUSY))
|
||||||
|
@ -1512,8 +1510,8 @@ static int write_memory(struct target *target, target_addr_t address,
|
||||||
while ((cur_addr = riscv_read_debug_buffer_x(target, d_addr)) < fin_addr) {
|
while ((cur_addr = riscv_read_debug_buffer_x(target, d_addr)) < fin_addr) {
|
||||||
LOG_DEBUG("transferring burst starting at address 0x%016lx", cur_addr);
|
LOG_DEBUG("transferring burst starting at address 0x%016lx", cur_addr);
|
||||||
riscv_addr_t start = (cur_addr - address) / size;
|
riscv_addr_t start = (cur_addr - address) / size;
|
||||||
assert (cur_addr > address);
|
assert (cur_addr > address);
|
||||||
struct riscv_batch *batch = riscv_batch_alloc(
|
struct riscv_batch *batch = riscv_batch_alloc(
|
||||||
target,
|
target,
|
||||||
32,
|
32,
|
||||||
info->dmi_busy_delay + info->ac_busy_delay);
|
info->dmi_busy_delay + info->ac_busy_delay);
|
||||||
|
@ -1555,10 +1553,10 @@ static int write_memory(struct target *target, target_addr_t address,
|
||||||
riscv_batch_run(batch);
|
riscv_batch_run(batch);
|
||||||
riscv_batch_free(batch);
|
riscv_batch_free(batch);
|
||||||
|
|
||||||
// Note that if the scan resulted in a Busy DMI response, it
|
// Note that if the scan resulted in a Busy DMI response, it
|
||||||
// is this read to abstractcs that will cause the dmi_busy_delay
|
// is this read to abstractcs that will cause the dmi_busy_delay
|
||||||
// to be incremented if necessary. The loop condition above
|
// to be incremented if necessary. The loop condition above
|
||||||
// catches the case where no writes went through at all.
|
// catches the case where no writes went through at all.
|
||||||
|
|
||||||
uint32_t abstractcs = dmi_read(target, DMI_ABSTRACTCS);
|
uint32_t abstractcs = dmi_read(target, DMI_ABSTRACTCS);
|
||||||
while (get_field(abstractcs, DMI_ABSTRACTCS_BUSY))
|
while (get_field(abstractcs, DMI_ABSTRACTCS_BUSY))
|
||||||
|
@ -1819,26 +1817,26 @@ int riscv013_execute_debug_buffer(struct target *target)
|
||||||
|
|
||||||
void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d)
|
void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d)
|
||||||
{
|
{
|
||||||
RISCV013_INFO(info);
|
RISCV013_INFO(info);
|
||||||
buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_WRITE);
|
buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_WRITE);
|
||||||
buf_set_u64((unsigned char *)buf, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, d);
|
buf_set_u64((unsigned char *)buf, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, d);
|
||||||
buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, a);
|
buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, a);
|
||||||
}
|
}
|
||||||
|
|
||||||
void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a)
|
void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a)
|
||||||
{
|
{
|
||||||
RISCV013_INFO(info);
|
RISCV013_INFO(info);
|
||||||
buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_READ);
|
buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_READ);
|
||||||
buf_set_u64((unsigned char *)buf, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, 0);
|
buf_set_u64((unsigned char *)buf, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, 0);
|
||||||
buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, a);
|
buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, a);
|
||||||
}
|
}
|
||||||
|
|
||||||
void riscv013_fill_dmi_nop_u64(struct target *target, char *buf)
|
void riscv013_fill_dmi_nop_u64(struct target *target, char *buf)
|
||||||
{
|
{
|
||||||
RISCV013_INFO(info);
|
RISCV013_INFO(info);
|
||||||
buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_NOP);
|
buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_NOP);
|
||||||
buf_set_u64((unsigned char *)buf, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, 0);
|
buf_set_u64((unsigned char *)buf, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, 0);
|
||||||
buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, 0);
|
buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
int riscv013_dmi_write_u64_bits(struct target *target)
|
int riscv013_dmi_write_u64_bits(struct target *target)
|
||||||
|
@ -1849,19 +1847,19 @@ int riscv013_dmi_write_u64_bits(struct target *target)
|
||||||
|
|
||||||
void riscv013_reset_current_hart(struct target *target)
|
void riscv013_reset_current_hart(struct target *target)
|
||||||
{
|
{
|
||||||
select_dmi(target);
|
select_dmi(target);
|
||||||
uint32_t control = dmi_read(target, DMI_DMCONTROL);
|
uint32_t control = dmi_read(target, DMI_DMCONTROL);
|
||||||
control = set_field(control, DMI_DMCONTROL_NDMRESET, 1);
|
control = set_field(control, DMI_DMCONTROL_NDMRESET, 1);
|
||||||
control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);
|
control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);
|
||||||
dmi_write(target, DMI_DMCONTROL, control);
|
dmi_write(target, DMI_DMCONTROL, control);
|
||||||
|
|
||||||
control = set_field(control, DMI_DMCONTROL_NDMRESET, 0);
|
control = set_field(control, DMI_DMCONTROL_NDMRESET, 0);
|
||||||
dmi_write(target, DMI_DMCONTROL, control);
|
dmi_write(target, DMI_DMCONTROL, control);
|
||||||
|
|
||||||
while (get_field(dmi_read(target, DMI_DMSTATUS), DMI_DMSTATUS_ALLHALTED) == 0);
|
while (get_field(dmi_read(target, DMI_DMSTATUS), DMI_DMSTATUS_ALLHALTED) == 0);
|
||||||
|
|
||||||
control = set_field(control, DMI_DMCONTROL_HALTREQ, 0);
|
control = set_field(control, DMI_DMCONTROL_HALTREQ, 0);
|
||||||
dmi_write(target, DMI_DMCONTROL, control);
|
dmi_write(target, DMI_DMCONTROL, control);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Helper Functions. */
|
/* Helper Functions. */
|
||||||
|
|
|
@ -172,18 +172,18 @@ enum {
|
||||||
|
|
||||||
uint8_t ir_dtmcontrol[1] = {DTMCONTROL};
|
uint8_t ir_dtmcontrol[1] = {DTMCONTROL};
|
||||||
struct scan_field select_dtmcontrol = {
|
struct scan_field select_dtmcontrol = {
|
||||||
.in_value = NULL,
|
.in_value = NULL,
|
||||||
.out_value = ir_dtmcontrol
|
.out_value = ir_dtmcontrol
|
||||||
};
|
};
|
||||||
uint8_t ir_dbus[1] = {DBUS};
|
uint8_t ir_dbus[1] = {DBUS};
|
||||||
struct scan_field select_dbus = {
|
struct scan_field select_dbus = {
|
||||||
.in_value = NULL,
|
.in_value = NULL,
|
||||||
.out_value = ir_dbus
|
.out_value = ir_dbus
|
||||||
};
|
};
|
||||||
uint8_t ir_idcode[1] = {0x1};
|
uint8_t ir_idcode[1] = {0x1};
|
||||||
struct scan_field select_idcode = {
|
struct scan_field select_idcode = {
|
||||||
.in_value = NULL,
|
.in_value = NULL,
|
||||||
.out_value = ir_idcode
|
.out_value = ir_idcode
|
||||||
};
|
};
|
||||||
|
|
||||||
struct trigger {
|
struct trigger {
|
||||||
|
@ -309,10 +309,10 @@ static int oldriscv_step(struct target *target, int current, uint32_t address,
|
||||||
}
|
}
|
||||||
|
|
||||||
static int old_or_new_riscv_step(
|
static int old_or_new_riscv_step(
|
||||||
struct target *target,
|
struct target *target,
|
||||||
int current,
|
int current,
|
||||||
target_addr_t address,
|
target_addr_t address,
|
||||||
int handle_breakpoints
|
int handle_breakpoints
|
||||||
){
|
){
|
||||||
RISCV_INFO(r);
|
RISCV_INFO(r);
|
||||||
if (r->is_halted == NULL)
|
if (r->is_halted == NULL)
|
||||||
|
@ -326,7 +326,7 @@ static int riscv_examine(struct target *target)
|
||||||
{
|
{
|
||||||
LOG_DEBUG("riscv_examine()");
|
LOG_DEBUG("riscv_examine()");
|
||||||
if (target_was_examined(target)) {
|
if (target_was_examined(target)) {
|
||||||
LOG_DEBUG("Target was already examined.\n");
|
LOG_DEBUG("Target was already examined.\n");
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -375,14 +375,14 @@ static int old_or_new_riscv_halt(struct target *target)
|
||||||
|
|
||||||
static int oldriscv_assert_reset(struct target *target)
|
static int oldriscv_assert_reset(struct target *target)
|
||||||
{
|
{
|
||||||
LOG_DEBUG("RISCV ASSERT RESET");
|
LOG_DEBUG("RISCV ASSERT RESET");
|
||||||
struct target_type *tt = get_target_type(target);
|
struct target_type *tt = get_target_type(target);
|
||||||
return tt->assert_reset(target);
|
return tt->assert_reset(target);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int oldriscv_deassert_reset(struct target *target)
|
static int oldriscv_deassert_reset(struct target *target)
|
||||||
{
|
{
|
||||||
LOG_DEBUG("RISCV DEASSERT RESET");
|
LOG_DEBUG("RISCV DEASSERT RESET");
|
||||||
struct target_type *tt = get_target_type(target);
|
struct target_type *tt = get_target_type(target);
|
||||||
return tt->deassert_reset(target);
|
return tt->deassert_reset(target);
|
||||||
}
|
}
|
||||||
|
@ -415,11 +415,11 @@ static int oldriscv_resume(struct target *target, int current, uint32_t address,
|
||||||
}
|
}
|
||||||
|
|
||||||
static int old_or_new_riscv_resume(
|
static int old_or_new_riscv_resume(
|
||||||
struct target *target,
|
struct target *target,
|
||||||
int current,
|
int current,
|
||||||
target_addr_t address,
|
target_addr_t address,
|
||||||
int handle_breakpoints,
|
int handle_breakpoints,
|
||||||
int debug_execution
|
int debug_execution
|
||||||
){
|
){
|
||||||
RISCV_INFO(r);
|
RISCV_INFO(r);
|
||||||
if (r->is_halted == NULL)
|
if (r->is_halted == NULL)
|
||||||
|
@ -626,11 +626,11 @@ memory. Not yet implemented.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static int riscv_checksum_memory(struct target *target,
|
static int riscv_checksum_memory(struct target *target,
|
||||||
target_addr_t address, uint32_t count,
|
target_addr_t address, uint32_t count,
|
||||||
uint32_t* checksum)
|
uint32_t* checksum)
|
||||||
{
|
{
|
||||||
*checksum = 0xFFFFFFFF;
|
*checksum = 0xFFFFFFFF;
|
||||||
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Should run code on the target to check whether a memory
|
/* Should run code on the target to check whether a memory
|
||||||
|
@ -640,13 +640,13 @@ Not yet implemented.
|
||||||
*/
|
*/
|
||||||
int riscv_blank_check_memory(struct target * target,
|
int riscv_blank_check_memory(struct target * target,
|
||||||
target_addr_t address,
|
target_addr_t address,
|
||||||
uint32_t count,
|
uint32_t count,
|
||||||
uint32_t * blank,
|
uint32_t * blank,
|
||||||
uint8_t erased_value)
|
uint8_t erased_value)
|
||||||
{
|
{
|
||||||
*blank = 0;
|
*blank = 0;
|
||||||
|
|
||||||
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*** OpenOCD Helper Functions ***/
|
/*** OpenOCD Helper Functions ***/
|
||||||
|
@ -760,11 +760,11 @@ int riscv_openocd_halt(struct target *target)
|
||||||
}
|
}
|
||||||
|
|
||||||
int riscv_openocd_resume(
|
int riscv_openocd_resume(
|
||||||
struct target *target,
|
struct target *target,
|
||||||
int current,
|
int current,
|
||||||
target_addr_t address,
|
target_addr_t address,
|
||||||
int handle_breakpoints,
|
int handle_breakpoints,
|
||||||
int debug_execution
|
int debug_execution
|
||||||
) {
|
) {
|
||||||
LOG_DEBUG("resuming all harts");
|
LOG_DEBUG("resuming all harts");
|
||||||
|
|
||||||
|
@ -785,10 +785,10 @@ int riscv_openocd_resume(
|
||||||
}
|
}
|
||||||
|
|
||||||
int riscv_openocd_step(
|
int riscv_openocd_step(
|
||||||
struct target *target,
|
struct target *target,
|
||||||
int current,
|
int current,
|
||||||
target_addr_t address,
|
target_addr_t address,
|
||||||
int handle_breakpoints
|
int handle_breakpoints
|
||||||
) {
|
) {
|
||||||
LOG_DEBUG("stepping rtos hart");
|
LOG_DEBUG("stepping rtos hart");
|
||||||
|
|
||||||
|
@ -1026,9 +1026,9 @@ void riscv_set_current_hartid(struct target *target, int hartid)
|
||||||
|
|
||||||
/* Avoid invalidating the register cache all the time. */
|
/* Avoid invalidating the register cache all the time. */
|
||||||
if (r->registers_initialized
|
if (r->registers_initialized
|
||||||
&& (!riscv_rtos_enabled(target) || (previous_hartid == hartid))
|
&& (!riscv_rtos_enabled(target) || (previous_hartid == hartid))
|
||||||
&& target->reg_cache->reg_list[GDB_REGNO_XPR0].size == (long)riscv_xlen(target)
|
&& target->reg_cache->reg_list[GDB_REGNO_XPR0].size == (long)riscv_xlen(target)
|
||||||
&& (!riscv_rtos_enabled(target) || (r->rtos_hartid != -1))) {
|
&& (!riscv_rtos_enabled(target) || (r->rtos_hartid != -1))) {
|
||||||
LOG_DEBUG("registers already initialized, skipping");
|
LOG_DEBUG("registers already initialized, skipping");
|
||||||
return;
|
return;
|
||||||
} else
|
} else
|
||||||
|
|
Loading…
Reference in New Issue