tcl: add Zynq-7000 target and Zedboard board configs

Change-Id: Ia7f2a57d1b32dda9936ad87e22635f7749ff3ce1
Signed-off-by: Tim Sander <tim@krieglstein.org>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2061
Tested-by: jenkins
__archive__
Tim Sander 2014-03-21 17:43:04 +01:00 committed by Paul Fertser
parent 6f62e2428e
commit 91a36fcf0a
2 changed files with 36 additions and 0 deletions

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#
# Digilent Zedboard Rev.C, Rev.D with Xilinx Zynq chip
#
# http://zedboard.com/product/zedboard
#
source [find interface/ftdi/digilent_jtag_smt2.cfg]
reset_config srst_only srst_push_pull
source [find target/zynq_7000.cfg]

25
tcl/target/zynq_7000.cfg Normal file
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#
# Xilinx Zynq-7000 All Programmable SoC
#
# http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm
#
set _CHIPNAME zynq
set _TARGETNAME $_CHIPNAME.cpu
jtag newtap zynq_pl bs -irlen 6 -ircapture 0x1 -irmask 0x03 \
-expected-id 0x23727093 \
-expected-id 0x03727093
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477
target create ${_TARGETNAME}0 cortex_a -chain-position $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x80090000
target create ${_TARGETNAME}1 cortex_a -chain-position $_CHIPNAME.dap \
-coreid 1 -dbgbase 0x80092000
target smp ${_TARGETNAME}0 ${_TARGETNAME}1
adapter_khz 1000
${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"