Create a init_board procedure for the ea dev board.
Signed-off-by: Chris Morgan <chmorgan@gmail.com> Change-Id: I082b0d3092c7f3b2ee6b68af64d48c78b31f1dbf Reviewed-on: http://openocd.zylin.com/510 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>__archive__
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4aa63d59bd
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8fc35a696f
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@ -1,24 +1,10 @@
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# Embedded Artists eval board for LPC2478
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# http://www.embeddedartists.com/
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# Delays on reset lines
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adapter_nsrst_delay 500
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jtag_ntrst_delay 1
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# Adaptive JTAG clocking through RTCK.
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#
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jtag_rclk 20
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# Target device: LPC2478
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set CCLK 72000
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source [find target/lpc2478.cfg]
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# A working area will help speeding the flash programming
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$_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr 0x10000-0x200-0x20] -work-area-backup 0
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# External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB)
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flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe
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# Helper
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#
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proc read_register {register} {
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@ -27,56 +13,32 @@ proc read_register {register} {
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return $result(0)
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}
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proc init_board {} {
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# Delays on reset lines
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adapter_nsrst_delay 500
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jtag_ntrst_delay 1
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# Enable the PLL.
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# Generate maximum CPU clock (72 MHz) Run from internal RC oscillator.
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# Note: The PLL output runs at a frequency N times the desired CPU clock.
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# It in unavoidable that the CPU clock drops down to (4 MHz/N) during
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# the initialization!
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# Here: N=4
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# Note that if the PLL is already active at the time this script is
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# called, the effective value of N is the value of CCLKCFG at that time!
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#
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proc enable_pll {} {
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# Disconnect PLL in case it is already connected
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if {[expr [read_register 0xE01FC080] & 0x03] == 3} {
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# Disconnect it, but leave it enabled
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# (This MUST be done in two steps)
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mww 0xE01FC080 0x00000001 ;# PLLCON: disconnect PLL
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mww 0xE01FC08C 0x000000AA ;# PLLFEED
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mww 0xE01FC08C 0x00000055 ;# PLLFEED
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}
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# Disable PLL (as it might already be enabled at this time!)
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mww 0xE01FC080 0x00000000 ;# PLLCON: disable PLL
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mww 0xE01FC08C 0x000000AA ;# PLLFEED
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mww 0xE01FC08C 0x00000055 ;# PLLFEED
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# Adaptive JTAG clocking through RTCK.
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#
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jtag_rclk 20
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# Setup PLL to generate 288 MHz from internal RC oscillator
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mww 0xE01FC10C 0x00000000 ;# CLKSRCSEL: IRC
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mww 0xE01FC084 0x00000023 ;# PLLCFG: N=1, M=36
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mww 0xE01FC08C 0x000000AA ;# PLLFEED
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mww 0xE01FC08C 0x00000055 ;# PLLFEED
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mww 0xE01FC080 0x00000001 ;# PLLCON: enable PLL
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mww 0xE01FC08C 0x000000AA ;# PLLFEED
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mww 0xE01FC08C 0x00000055 ;# PLLFEED
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sleep 100
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mww 0xE01FC104 0x00000003 ;# CCLKCFG: divide by 4 (72 MHz)
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mww 0xE01FC080 0x00000003 ;# PLLCON: connect PLL
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mww 0xE01FC08C 0x000000AA ;# PLLFEED
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mww 0xE01FC08C 0x00000055 ;# PLLFEED
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}
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global _TARGETNAME
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global _CHIPNAME
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# A working area will help speeding the flash programming
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$_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr 0x10000-0x200-0x20] -work-area-backup 0
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# Event handlers
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#
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$_TARGETNAME configure -event reset-start {
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# External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB)
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flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe
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# Event handlers
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#
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$_TARGETNAME configure -event reset-start {
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# Back to the slow JTAG clock
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jtag_rclk 20
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}
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$_TARGETNAME configure -event reset-init {
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}
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$_TARGETNAME configure -event reset-init {
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arm core_state arm
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arm7_9 dcc_downloads enable ;# Speed up downloads by using DCC transfer
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arm7_9 fast_memory_access enable
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@ -144,5 +106,49 @@ $_TARGETNAME configure -event reset-init {
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mdw 0xA0011000 1 ;# Set SDRAM mode register
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mww 0xFFE08020 0x00000000 ;# EMCDynamicControl: NORMAL
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mww 0xFFE08100 0x00085488 ;# EMCDynamicConfig0: Enable buffers
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}
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$_TARGETNAME configure -event gdb-attach {
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# Without this gdb-attach will first time as probe will fail
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reset init
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}
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}
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# Enable the PLL.
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# Generate maximum CPU clock (72 MHz) Run from internal RC oscillator.
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# Note: The PLL output runs at a frequency N times the desired CPU clock.
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# It in unavoidable that the CPU clock drops down to (4 MHz/N) during
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# the initialization!
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# Here: N=4
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# Note that if the PLL is already active at the time this script is
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# called, the effective value of N is the value of CCLKCFG at that time!
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#
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proc enable_pll {} {
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# Disconnect PLL in case it is already connected
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if {[expr [read_register 0xE01FC080] & 0x03] == 3} {
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# Disconnect it, but leave it enabled
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# (This MUST be done in two steps)
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mww 0xE01FC080 0x00000001 ;# PLLCON: disconnect PLL
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mww 0xE01FC08C 0x000000AA ;# PLLFEED
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mww 0xE01FC08C 0x00000055 ;# PLLFEED
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}
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# Disable PLL (as it might already be enabled at this time!)
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mww 0xE01FC080 0x00000000 ;# PLLCON: disable PLL
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mww 0xE01FC08C 0x000000AA ;# PLLFEED
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mww 0xE01FC08C 0x00000055 ;# PLLFEED
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# Setup PLL to generate 288 MHz from internal RC oscillator
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mww 0xE01FC10C 0x00000000 ;# CLKSRCSEL: IRC
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mww 0xE01FC084 0x00000023 ;# PLLCFG: N=1, M=36
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mww 0xE01FC08C 0x000000AA ;# PLLFEED
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mww 0xE01FC08C 0x00000055 ;# PLLFEED
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mww 0xE01FC080 0x00000001 ;# PLLCON: enable PLL
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mww 0xE01FC08C 0x000000AA ;# PLLFEED
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mww 0xE01FC08C 0x00000055 ;# PLLFEED
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sleep 100
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mww 0xE01FC104 0x00000003 ;# CCLKCFG: divide by 4 (72 MHz)
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mww 0xE01FC080 0x00000003 ;# PLLCON: connect PLL
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mww 0xE01FC08C 0x000000AA ;# PLLFEED
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mww 0xE01FC08C 0x00000055 ;# PLLFEED
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}
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