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Create a init_board procedure for the ea dev board. 

Signed-off-by: Chris Morgan <chmorgan@gmail.com>
Change-Id: I082b0d3092c7f3b2ee6b68af64d48c78b31f1dbf
Reviewed-on: http://openocd.zylin.com/510
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
__archive__
Chris Morgan 2012-03-08 14:58:41 -05:00 committed by Spencer Oliver
parent 4aa63d59bd
commit 8fc35a696f
1 changed files with 100 additions and 94 deletions
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108
tcl/board/embedded-artists_lpc2478-32.cfg
View File

@ -1,24 +1,10 @@
# Embedded Artists eval board for LPC2478 # Embedded Artists eval board for LPC2478
# http://www.embeddedartists.com/ # http://www.embeddedartists.com/
# Delays on reset lines
adapter_nsrst_delay 500
jtag_ntrst_delay 1
# Adaptive JTAG clocking through RTCK.
#
jtag_rclk 20
# Target device: LPC2478 # Target device: LPC2478
set CCLK 72000 set CCLK 72000
source [find target/lpc2478.cfg] source [find target/lpc2478.cfg]
# A working area will help speeding the flash programming
$_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr 0x10000-0x200-0x20] -work-area-backup 0
# External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB)
flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe
# Helper # Helper
# #
proc read_register {register} { proc read_register {register} {
@ -27,45 +13,23 @@ proc read_register {register} {
return $result(0) return $result(0)
} }
proc init_board {} {
# Delays on reset lines
adapter_nsrst_delay 500
jtag_ntrst_delay 1
# Enable the PLL. # Adaptive JTAG clocking through RTCK.
# Generate maximum CPU clock (72 MHz) Run from internal RC oscillator.
# Note: The PLL output runs at a frequency N times the desired CPU clock.
# It in unavoidable that the CPU clock drops down to (4 MHz/N) during
# the initialization!
# Here: N=4
# Note that if the PLL is already active at the time this script is
# called, the effective value of N is the value of CCLKCFG at that time!
# #
proc enable_pll {} { jtag_rclk 20
# Disconnect PLL in case it is already connected
if {[expr [read_register 0xE01FC080] & 0x03] == 3} {
# Disconnect it, but leave it enabled
# (This MUST be done in two steps)
mww 0xE01FC080 0x00000001 ;# PLLCON: disconnect PLL
mww 0xE01FC08C 0x000000AA ;# PLLFEED
mww 0xE01FC08C 0x00000055 ;# PLLFEED
}
# Disable PLL (as it might already be enabled at this time!)
mww 0xE01FC080 0x00000000 ;# PLLCON: disable PLL
mww 0xE01FC08C 0x000000AA ;# PLLFEED
mww 0xE01FC08C 0x00000055 ;# PLLFEED
# Setup PLL to generate 288 MHz from internal RC oscillator global _TARGETNAME
mww 0xE01FC10C 0x00000000 ;# CLKSRCSEL: IRC global _CHIPNAME
mww 0xE01FC084 0x00000023 ;# PLLCFG: N=1, M=36
mww 0xE01FC08C 0x000000AA ;# PLLFEED
mww 0xE01FC08C 0x00000055 ;# PLLFEED
mww 0xE01FC080 0x00000001 ;# PLLCON: enable PLL
mww 0xE01FC08C 0x000000AA ;# PLLFEED
mww 0xE01FC08C 0x00000055 ;# PLLFEED
sleep 100
mww 0xE01FC104 0x00000003 ;# CCLKCFG: divide by 4 (72 MHz)
mww 0xE01FC080 0x00000003 ;# PLLCON: connect PLL
mww 0xE01FC08C 0x000000AA ;# PLLFEED
mww 0xE01FC08C 0x00000055 ;# PLLFEED
}
# A working area will help speeding the flash programming
$_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr 0x10000-0x200-0x20] -work-area-backup 0
# External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB)
flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe
# Event handlers # Event handlers
# #
@ -74,9 +38,7 @@ $_TARGETNAME configure -event reset-start {
jtag_rclk 20 jtag_rclk 20
} }
$_TARGETNAME configure -event reset-init { $_TARGETNAME configure -event reset-init {
arm core_state arm arm core_state arm
arm7_9 dcc_downloads enable ;# Speed up downloads by using DCC transfer arm7_9 dcc_downloads enable ;# Speed up downloads by using DCC transfer
arm7_9 fast_memory_access enable arm7_9 fast_memory_access enable
@ -146,3 +108,47 @@ $_TARGETNAME configure -event reset-init {
mww 0xFFE08100 0x00085488 ;# EMCDynamicConfig0: Enable buffers mww 0xFFE08100 0x00085488 ;# EMCDynamicConfig0: Enable buffers
} }
$_TARGETNAME configure -event gdb-attach {
# Without this gdb-attach will first time as probe will fail
reset init
}
}
# Enable the PLL.
# Generate maximum CPU clock (72 MHz) Run from internal RC oscillator.
# Note: The PLL output runs at a frequency N times the desired CPU clock.
# It in unavoidable that the CPU clock drops down to (4 MHz/N) during
# the initialization!
# Here: N=4
# Note that if the PLL is already active at the time this script is
# called, the effective value of N is the value of CCLKCFG at that time!
#
proc enable_pll {} {
# Disconnect PLL in case it is already connected
if {[expr [read_register 0xE01FC080] & 0x03] == 3} {
# Disconnect it, but leave it enabled
# (This MUST be done in two steps)
mww 0xE01FC080 0x00000001 ;# PLLCON: disconnect PLL
mww 0xE01FC08C 0x000000AA ;# PLLFEED
mww 0xE01FC08C 0x00000055 ;# PLLFEED
}
# Disable PLL (as it might already be enabled at this time!)
mww 0xE01FC080 0x00000000 ;# PLLCON: disable PLL
mww 0xE01FC08C 0x000000AA ;# PLLFEED
mww 0xE01FC08C 0x00000055 ;# PLLFEED
# Setup PLL to generate 288 MHz from internal RC oscillator
mww 0xE01FC10C 0x00000000 ;# CLKSRCSEL: IRC
mww 0xE01FC084 0x00000023 ;# PLLCFG: N=1, M=36
mww 0xE01FC08C 0x000000AA ;# PLLFEED
mww 0xE01FC08C 0x00000055 ;# PLLFEED
mww 0xE01FC080 0x00000001 ;# PLLCON: enable PLL
mww 0xE01FC08C 0x000000AA ;# PLLFEED
mww 0xE01FC08C 0x00000055 ;# PLLFEED
sleep 100
mww 0xE01FC104 0x00000003 ;# CCLKCFG: divide by 4 (72 MHz)
mww 0xE01FC080 0x00000003 ;# PLLCON: connect PLL
mww 0xE01FC08C 0x000000AA ;# PLLFEED
mww 0xE01FC08C 0x00000055 ;# PLLFEED
}