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Cortex-M3: minor cleanup 

There's no reason to read which interrupts are enabled from
the NVIC; that state isn't used.  Plus, it's highly dynamic
since firmware can change it at any time; remove the support
for those state records.

Remove duplicate definition of DWT_CTRL address; shrink a line.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
__archive__
David Brownell 2009-11-05 01:03:54 -08:00
parent 7acb2607ff
commit 8fb2baaa6b
2 changed files with 4 additions and 16 deletions
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14
src/target/cortex_m3.c
View File

@ -1495,7 +1495,7 @@ static int cortex_m3_init_target(struct command_context_s *cmd_ctx,
static int cortex_m3_examine(struct target_s *target) static int cortex_m3_examine(struct target_s *target)
{ {
int retval; int retval;
uint32_t cpuid, fpcr, dwtcr, ictr; uint32_t cpuid, fpcr, dwtcr;
int i; int i;
/* get pointers to arch-specific information */ /* get pointers to arch-specific information */
@ -1511,21 +1511,15 @@ static int cortex_m3_examine(struct target_s *target)
target_set_examined(target); target_set_examined(target);
/* Read from Device Identification Registers */ /* Read from Device Identification Registers */
if ((retval = target_read_u32(target, CPUID, &cpuid)) != ERROR_OK) retval = target_read_u32(target, CPUID, &cpuid);
if (retval != ERROR_OK)
return retval; return retval;
if (((cpuid >> 4) & 0xc3f) == 0xc23) if (((cpuid >> 4) & 0xc3f) == 0xc23)
LOG_DEBUG("CORTEX-M3 processor detected"); LOG_DEBUG("CORTEX-M3 processor detected");
LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid); LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
target_read_u32(target, NVIC_ICTR, &ictr); /* NOTE: FPB and DWT are both optional. */
cortex_m3->intlinesnum = (ictr & 0x1F) + 1;
cortex_m3->intsetenable = calloc(cortex_m3->intlinesnum, 4);
for (i = 0; i < cortex_m3->intlinesnum; i++)
{
target_read_u32(target, NVIC_ISE0 + 4 * i, cortex_m3->intsetenable + i);
LOG_DEBUG("interrupt enable[%i] = 0x%8.8" PRIx32 "", i, cortex_m3->intsetenable[i]);
}
/* Setup FPB */ /* Setup FPB */
target_read_u32(target, FP_CTRL, &fpcr); target_read_u32(target, FP_CTRL, &fpcr);

6
src/target/cortex_m3.h
View File

@ -60,8 +60,6 @@
#define FP_COMP6 0xE0002020 #define FP_COMP6 0xE0002020
#define FP_COMP7 0xE0002024 #define FP_COMP7 0xE0002024
#define DWT_CTRL 0xE0001000
/* DCB_DHCSR bit and field definitions */ /* DCB_DHCSR bit and field definitions */
#define DBGKEY (0xA05F << 16) #define DBGKEY (0xA05F << 16)
#define C_DEBUGEN (1 << 0) #define C_DEBUGEN (1 << 0)
@ -160,10 +158,6 @@ typedef struct cortex_m3_common_s
int dwt_comp_available; int dwt_comp_available;
cortex_m3_dwt_comparator_t *dwt_comparator_list; cortex_m3_dwt_comparator_t *dwt_comparator_list;
/* Interrupts */
int intlinesnum;
uint32_t *intsetenable;
armv7m_common_t armv7m; armv7m_common_t armv7m;
void *arch_info; void *arch_info;
} cortex_m3_common_t; } cortex_m3_common_t;