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armv7a: fix scan-build warnings 

"Value stored to 'retval' is never read": Check and propagate error
"Dereference of null pointer": Probably bogus, maybe triggered by the null
check on armv7a, so remove the check since it can't be null anyway.

Change-Id: I3bc44e52af1589ff40e6a42deda0ce7f3a25e397
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/119
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
__archive__
Andreas Fritiofson 2011-10-25 00:47:21 +02:00 committed by Øyvind Harboe
parent f80ec2aa37
commit 8f76ca05d9
1 changed files with 3 additions and 2 deletions
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5
src/target/armv7a.c
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@ -147,6 +147,8 @@ int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val)
retval = dpm->instr_read_data_r0(dpm, retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_MRC(15, 0, 0, 2, 0, ttb), ARMV4_5_MRC(15, 0, 0, 2, 0, ttb),
&ttb); &ttb);
if (retval != ERROR_OK)
return retval;
retval = armv7a->armv7a_mmu.read_physical_memory(target, retval = armv7a->armv7a_mmu.read_physical_memory(target,
(ttb & 0xffffc000) | ((va & 0xfff00000) >> 18), (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
4, 1, (uint8_t*)&first_lvl_descriptor); 4, 1, (uint8_t*)&first_lvl_descriptor);
@ -461,8 +463,6 @@ static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t
struct target *curr; struct target *curr;
struct armv7a_common *armv7a = target_to_armv7a(target); struct armv7a_common *armv7a = target_to_armv7a(target);
if (armv7a == NULL)
LOG_ERROR("not an armv7a target");
l2x_cache = calloc(1, sizeof(struct armv7a_l2x_cache)); l2x_cache = calloc(1, sizeof(struct armv7a_l2x_cache));
l2x_cache->base = base; l2x_cache->base = base;
l2x_cache->way = way; l2x_cache->way = way;
@ -616,6 +616,7 @@ int armv7a_identify_cache(struct target *target)
2, 0, /* op1, op2 */ 2, 0, /* op1, op2 */
0, 0, /* CRn, CRm */ 0, 0, /* CRn, CRm */
&cache_selected); &cache_selected);
if (retval!=ERROR_OK) goto done;
/* select instruction cache*/ /* select instruction cache*/
/* MCR p15, 2,<Rd>, c0, c0, 0; Write CSSELR */ /* MCR p15, 2,<Rd>, c0, c0, 0; Write CSSELR */
/* [0] : 1 instruction cache selection , 0 data cache selection */ /* [0] : 1 instruction cache selection , 0 data cache selection */